2 * driver/dma/ste_dma40.c
4 * Copyright (C) ST-Ericsson 2007-2010
5 * License terms: GNU General Public License (GPL) version 2
6 * Author: Per Friden <per.friden@stericsson.com>
7 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
18 #include <plat/ste_dma40.h>
20 #include "ste_dma40_ll.h"
22 #define D40_NAME "dma40"
24 #define D40_PHY_CHAN -1
26 /* For masking out/in 2 bit channel positions */
27 #define D40_CHAN_POS(chan) (2 * (chan / 2))
28 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
30 /* Maximum iterations taken before giving up suspending a channel */
31 #define D40_SUSPEND_MAX_IT 500
33 /* Hardware requirement on LCLA alignment */
34 #define LCLA_ALIGNMENT 0x40000
35 /* Attempts before giving up to trying to get pages that are aligned */
36 #define MAX_LCLA_ALLOC_ATTEMPTS 256
38 /* Bit markings for allocation map */
39 #define D40_ALLOC_FREE (1 << 31)
40 #define D40_ALLOC_PHY (1 << 30)
41 #define D40_ALLOC_LOG_FREE 0
43 /* Hardware designer of the block */
44 #define D40_PERIPHID2_DESIGNER 0x8
47 * enum 40_command - The different commands and/or statuses.
49 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
50 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
51 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
52 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 D40_DMA_SUSPEND_REQ = 2,
62 * struct d40_lli_pool - Structure for keeping LLIs in memory
64 * @base: Pointer to memory area when the pre_alloc_lli's are not large
65 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
66 * pre_alloc_lli is used.
67 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
68 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
69 * one buffer to one buffer.
74 /* Space for dst and src, plus an extra for padding */
75 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
79 * struct d40_desc - A descriptor is one DMA job.
81 * @lli_phy: LLI settings for physical channel. Both src and dst=
82 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
84 * @lli_log: Same as above but for logical channels.
85 * @lli_pool: The pool with two entries pre-allocated.
86 * @lli_len: Number of llis of current descriptor.
87 * @lli_count: Number of transfered llis.
88 * @lli_tx_len: Max number of LLIs per transfer, there can be
89 * many transfer for one descriptor.
90 * @txd: DMA engine struct. Used for among other things for communication
93 * @dir: The transfer direction of this job.
94 * @is_in_client_list: true if the client owns this descriptor.
96 * This descriptor is used for both logical and physical transfers.
101 struct d40_phy_lli_bidir lli_phy;
103 struct d40_log_lli_bidir lli_log;
105 struct d40_lli_pool lli_pool;
110 struct dma_async_tx_descriptor txd;
111 struct list_head node;
113 enum dma_data_direction dir;
114 bool is_in_client_list;
118 * struct d40_lcla_pool - LCLA pool settings and data.
120 * @base: The virtual address of LCLA. 18 bit aligned.
121 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
122 * This pointer is only there for clean-up on error.
123 * @pages: The number of pages needed for all physical channels.
124 * Only used later for clean-up on error
125 * @lock: Lock to protect the content in this struct.
126 * @alloc_map: Bitmap mapping between physical channel and LCLA entries.
127 * @num_blocks: The number of entries of alloc_map. Equals to the
128 * number of physical channels.
130 struct d40_lcla_pool {
132 void *base_unaligned;
140 * struct d40_phy_res - struct for handling eventlines mapped to physical
143 * @lock: A lock protection this entity.
144 * @num: The physical channel number of this entity.
145 * @allocated_src: Bit mapped to show which src event line's are mapped to
146 * this physical channel. Can also be free or physically allocated.
147 * @allocated_dst: Same as for src but is dst.
148 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
149 * event line number. Both allocated_src and allocated_dst can not be
150 * allocated to a physical channel, since the interrupt handler has then
151 * no way of figure out which one the interrupt belongs to.
163 * struct d40_chan - Struct that describes a channel.
165 * @lock: A spinlock to protect this struct.
166 * @log_num: The logical number, if any of this channel.
167 * @completed: Starts with 1, after first interrupt it is set to dma engine's
169 * @pending_tx: The number of pending transfers. Used between interrupt handler
171 * @busy: Set to true when transfer is ongoing on this channel.
172 * @phy_chan: Pointer to physical channel which this instance runs on. If this
173 * point is NULL, then the channel is not allocated.
174 * @chan: DMA engine handle.
175 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
176 * transfer and call client callback.
177 * @client: Cliented owned descriptor list.
178 * @active: Active descriptor.
179 * @queue: Queued jobs.
180 * @dma_cfg: The client configuration of this dma channel.
181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
188 * This struct can either "be" a logical or a physical channel.
193 /* ID of the most recent completed transfer */
197 struct d40_phy_res *phy_chan;
198 struct dma_chan chan;
199 struct tasklet_struct tasklet;
200 struct list_head client;
201 struct list_head active;
202 struct list_head queue;
203 struct stedma40_chan_cfg dma_cfg;
204 struct d40_base *base;
205 /* Default register configurations */
208 struct d40_def_lcsp log_def;
209 struct d40_lcla_elem lcla;
210 struct d40_log_lli_full *lcpa;
214 * struct d40_base - The big global struct, one for each probe'd instance.
216 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
217 * @execmd_lock: Lock for execute command usage since several channels share
218 * the same physical register.
219 * @dev: The device structure.
220 * @virtbase: The virtual base address of the DMA's register.
221 * @rev: silicon revision detected.
222 * @clk: Pointer to the DMA clock structure.
223 * @phy_start: Physical memory start of the DMA registers.
224 * @phy_size: Size of the DMA register map.
225 * @irq: The IRQ number.
226 * @num_phy_chans: The number of physical channels. Read from HW. This
227 * is the number of available channels for this driver, not counting "Secure
228 * mode" allocated physical channels.
229 * @num_log_chans: The number of logical channels. Calculated from
231 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
232 * @dma_slave: dma_device channels that can do only do slave transfers.
233 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
234 * @phy_chans: Room for all possible physical channels in system.
235 * @log_chans: Room for all possible logical channels in system.
236 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
237 * to log_chans entries.
238 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
239 * to phy_chans entries.
240 * @plat_data: Pointer to provided platform_data which is the driver
242 * @phy_res: Vector containing all physical channels.
243 * @lcla_pool: lcla pool settings and data.
244 * @lcpa_base: The virtual mapped address of LCPA.
245 * @phy_lcpa: The physical address of the LCPA.
246 * @lcpa_size: The size of the LCPA area.
247 * @desc_slab: cache for descriptors.
250 spinlock_t interrupt_lock;
251 spinlock_t execmd_lock;
253 void __iomem *virtbase;
256 phys_addr_t phy_start;
257 resource_size_t phy_size;
261 struct dma_device dma_both;
262 struct dma_device dma_slave;
263 struct dma_device dma_memcpy;
264 struct d40_chan *phy_chans;
265 struct d40_chan *log_chans;
266 struct d40_chan **lookup_log_chans;
267 struct d40_chan **lookup_phy_chans;
268 struct stedma40_platform_data *plat_data;
269 /* Physical half channels */
270 struct d40_phy_res *phy_res;
271 struct d40_lcla_pool lcla_pool;
274 resource_size_t lcpa_size;
275 struct kmem_cache *desc_slab;
279 * struct d40_interrupt_lookup - lookup table for interrupt handler
281 * @src: Interrupt mask register.
282 * @clr: Interrupt clear register.
283 * @is_error: true if this is an error interrupt.
284 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
285 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
287 struct d40_interrupt_lookup {
295 * struct d40_reg_val - simple lookup struct
297 * @reg: The register.
298 * @val: The value that belongs to the register in reg.
305 static int d40_pool_lli_alloc(struct d40_desc *d40d,
306 int lli_len, bool is_log)
312 align = sizeof(struct d40_log_lli);
314 align = sizeof(struct d40_phy_lli);
317 base = d40d->lli_pool.pre_alloc_lli;
318 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
319 d40d->lli_pool.base = NULL;
321 d40d->lli_pool.size = ALIGN(lli_len * 2 * align, align);
323 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
324 d40d->lli_pool.base = base;
326 if (d40d->lli_pool.base == NULL)
331 d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base,
333 d40d->lli_log.dst = PTR_ALIGN(d40d->lli_log.src + lli_len,
336 d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base,
338 d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len,
341 d40d->lli_phy.src_addr = virt_to_phys(d40d->lli_phy.src);
342 d40d->lli_phy.dst_addr = virt_to_phys(d40d->lli_phy.dst);
348 static void d40_pool_lli_free(struct d40_desc *d40d)
350 kfree(d40d->lli_pool.base);
351 d40d->lli_pool.base = NULL;
352 d40d->lli_pool.size = 0;
353 d40d->lli_log.src = NULL;
354 d40d->lli_log.dst = NULL;
355 d40d->lli_phy.src = NULL;
356 d40d->lli_phy.dst = NULL;
357 d40d->lli_phy.src_addr = 0;
358 d40d->lli_phy.dst_addr = 0;
361 static dma_cookie_t d40_assign_cookie(struct d40_chan *d40c,
362 struct d40_desc *desc)
364 dma_cookie_t cookie = d40c->chan.cookie;
369 d40c->chan.cookie = cookie;
370 desc->txd.cookie = cookie;
375 static void d40_desc_remove(struct d40_desc *d40d)
377 list_del(&d40d->node);
380 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
385 if (!list_empty(&d40c->client)) {
386 list_for_each_entry_safe(d, _d, &d40c->client, node)
387 if (async_tx_test_ack(&d->txd)) {
388 d40_pool_lli_free(d);
393 d = kmem_cache_alloc(d40c->base->desc_slab, GFP_NOWAIT);
395 memset(d, 0, sizeof(struct d40_desc));
396 INIT_LIST_HEAD(&d->node);
402 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
404 kmem_cache_free(d40c->base->desc_slab, d40d);
407 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
409 list_add_tail(&desc->node, &d40c->active);
412 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
416 if (list_empty(&d40c->active))
419 d = list_first_entry(&d40c->active,
425 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
427 list_add_tail(&desc->node, &d40c->queue);
430 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
434 if (list_empty(&d40c->queue))
437 d = list_first_entry(&d40c->queue,
443 /* Support functions for logical channels */
445 static int d40_lcla_id_get(struct d40_chan *d40c)
449 struct d40_log_lli *lcla_lidx_base =
450 d40c->base->lcla_pool.base + d40c->phy_chan->num * 1024;
452 int lli_per_log = d40c->base->plat_data->llis_per_log;
455 if (d40c->lcla.src_id >= 0 && d40c->lcla.dst_id >= 0)
458 if (d40c->base->lcla_pool.num_blocks > 32)
461 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
463 for (i = 0; i < d40c->base->lcla_pool.num_blocks; i++) {
464 if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
466 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
472 if (src_id >= d40c->base->lcla_pool.num_blocks)
475 for (; i < d40c->base->lcla_pool.num_blocks; i++) {
476 if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
478 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
485 if (dst_id == src_id)
488 d40c->lcla.src_id = src_id;
489 d40c->lcla.dst_id = dst_id;
490 d40c->lcla.dst = lcla_lidx_base + dst_id * lli_per_log + 1;
491 d40c->lcla.src = lcla_lidx_base + src_id * lli_per_log + 1;
493 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
496 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
501 static int d40_channel_execute_command(struct d40_chan *d40c,
502 enum d40_command command)
505 void __iomem *active_reg;
510 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
512 if (d40c->phy_chan->num % 2 == 0)
513 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
515 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
517 if (command == D40_DMA_SUSPEND_REQ) {
518 status = (readl(active_reg) &
519 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
520 D40_CHAN_POS(d40c->phy_chan->num);
522 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
526 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
527 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
530 if (command == D40_DMA_SUSPEND_REQ) {
532 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
533 status = (readl(active_reg) &
534 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
535 D40_CHAN_POS(d40c->phy_chan->num);
539 * Reduce the number of bus accesses while
540 * waiting for the DMA to suspend.
544 if (status == D40_DMA_STOP ||
545 status == D40_DMA_SUSPENDED)
549 if (i == D40_SUSPEND_MAX_IT) {
550 dev_err(&d40c->chan.dev->device,
551 "[%s]: unable to suspend the chl %d (log: %d) status %x\n",
552 __func__, d40c->phy_chan->num, d40c->log_num,
560 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
564 static void d40_term_all(struct d40_chan *d40c)
566 struct d40_desc *d40d;
569 /* Release active descriptors */
570 while ((d40d = d40_first_active_get(d40c))) {
571 d40_desc_remove(d40d);
573 /* Return desc to free-list */
574 d40_desc_free(d40c, d40d);
577 /* Release queued descriptors waiting for transfer */
578 while ((d40d = d40_first_queued(d40c))) {
579 d40_desc_remove(d40d);
581 /* Return desc to free-list */
582 d40_desc_free(d40c, d40d);
585 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
587 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
588 (~(0x1 << d40c->lcla.dst_id));
589 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
590 (~(0x1 << d40c->lcla.src_id));
592 d40c->lcla.src_id = -1;
593 d40c->lcla.dst_id = -1;
595 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
597 d40c->pending_tx = 0;
601 static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
606 /* Notice, that disable requires the physical channel to be stopped */
608 val = D40_ACTIVATE_EVENTLINE;
610 val = D40_DEACTIVATE_EVENTLINE;
612 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
614 /* Enable event line connected to device (or memcpy) */
615 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
616 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
617 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
619 writel((val << D40_EVENTLINE_POS(event)) |
620 ~D40_EVENTLINE_MASK(event),
621 d40c->base->virtbase + D40_DREG_PCBASE +
622 d40c->phy_chan->num * D40_DREG_PCDELTA +
625 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
626 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
628 writel((val << D40_EVENTLINE_POS(event)) |
629 ~D40_EVENTLINE_MASK(event),
630 d40c->base->virtbase + D40_DREG_PCBASE +
631 d40c->phy_chan->num * D40_DREG_PCDELTA +
635 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
638 static u32 d40_chan_has_events(struct d40_chan *d40c)
642 /* If SSLNK or SDLNK is zero all events are disabled */
643 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
644 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
645 val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
646 d40c->phy_chan->num * D40_DREG_PCDELTA +
649 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM)
650 val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
651 d40c->phy_chan->num * D40_DREG_PCDELTA +
656 static void d40_config_enable_lidx(struct d40_chan *d40c)
658 /* Set LIDX for lcla */
659 writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
660 D40_SREG_ELEM_LOG_LIDX_MASK,
661 d40c->base->virtbase + D40_DREG_PCBASE +
662 d40c->phy_chan->num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
664 writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
665 D40_SREG_ELEM_LOG_LIDX_MASK,
666 d40c->base->virtbase + D40_DREG_PCBASE +
667 d40c->phy_chan->num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
670 static int d40_config_write(struct d40_chan *d40c)
676 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
680 /* Odd addresses are even addresses + 4 */
681 addr_base = (d40c->phy_chan->num % 2) * 4;
682 /* Setup channel mode to logical or physical */
683 var = ((u32)(d40c->log_num != D40_PHY_CHAN) + 1) <<
684 D40_CHAN_POS(d40c->phy_chan->num);
685 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
687 /* Setup operational mode option register */
688 var = ((d40c->dma_cfg.channel_type >> STEDMA40_INFO_CH_MODE_OPT_POS) &
689 0x3) << D40_CHAN_POS(d40c->phy_chan->num);
691 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
693 if (d40c->log_num != D40_PHY_CHAN) {
694 /* Set default config for CFG reg */
695 writel(d40c->src_def_cfg,
696 d40c->base->virtbase + D40_DREG_PCBASE +
697 d40c->phy_chan->num * D40_DREG_PCDELTA +
699 writel(d40c->dst_def_cfg,
700 d40c->base->virtbase + D40_DREG_PCBASE +
701 d40c->phy_chan->num * D40_DREG_PCDELTA +
704 d40_config_enable_lidx(d40c);
709 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
711 if (d40d->lli_phy.dst && d40d->lli_phy.src) {
712 d40_phy_lli_write(d40c->base->virtbase,
716 } else if (d40d->lli_log.dst && d40d->lli_log.src) {
717 struct d40_log_lli *src = d40d->lli_log.src;
718 struct d40_log_lli *dst = d40d->lli_log.dst;
721 src += d40d->lli_count;
722 dst += d40d->lli_count;
723 s = d40_log_lli_write(d40c->lcpa,
724 d40c->lcla.src, d40c->lcla.dst,
726 d40c->base->plat_data->llis_per_log);
728 /* If s equals to zero, the job is not linked */
730 (void) dma_map_single(d40c->base->dev, d40c->lcla.src,
731 s * sizeof(struct d40_log_lli),
733 (void) dma_map_single(d40c->base->dev, d40c->lcla.dst,
734 s * sizeof(struct d40_log_lli),
738 d40d->lli_count += d40d->lli_tx_len;
741 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
743 struct d40_chan *d40c = container_of(tx->chan,
746 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
749 spin_lock_irqsave(&d40c->lock, flags);
751 tx->cookie = d40_assign_cookie(d40c, d40d);
753 d40_desc_queue(d40c, d40d);
755 spin_unlock_irqrestore(&d40c->lock, flags);
760 static int d40_start(struct d40_chan *d40c)
762 if (d40c->base->rev == 0) {
765 if (d40c->log_num != D40_PHY_CHAN) {
766 err = d40_channel_execute_command(d40c,
767 D40_DMA_SUSPEND_REQ);
773 if (d40c->log_num != D40_PHY_CHAN)
774 d40_config_set_event(d40c, true);
776 return d40_channel_execute_command(d40c, D40_DMA_RUN);
779 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
781 struct d40_desc *d40d;
784 /* Start queued jobs, if any */
785 d40d = d40_first_queued(d40c);
790 /* Remove from queue */
791 d40_desc_remove(d40d);
793 /* Add to active queue */
794 d40_desc_submit(d40c, d40d);
796 /* Initiate DMA job */
797 d40_desc_load(d40c, d40d);
800 err = d40_start(d40c);
809 /* called from interrupt context */
810 static void dma_tc_handle(struct d40_chan *d40c)
812 struct d40_desc *d40d;
817 /* Get first active entry from list */
818 d40d = d40_first_active_get(d40c);
823 if (d40d->lli_count < d40d->lli_len) {
825 d40_desc_load(d40c, d40d);
827 (void) d40_start(d40c);
831 if (d40_queue_start(d40c) == NULL)
835 tasklet_schedule(&d40c->tasklet);
839 static void dma_tasklet(unsigned long data)
841 struct d40_chan *d40c = (struct d40_chan *) data;
842 struct d40_desc *d40d_fin;
844 dma_async_tx_callback callback;
845 void *callback_param;
847 spin_lock_irqsave(&d40c->lock, flags);
849 /* Get first active entry from list */
850 d40d_fin = d40_first_active_get(d40c);
852 if (d40d_fin == NULL)
855 d40c->completed = d40d_fin->txd.cookie;
858 * If terminating a channel pending_tx is set to zero.
859 * This prevents any finished active jobs to return to the client.
861 if (d40c->pending_tx == 0) {
862 spin_unlock_irqrestore(&d40c->lock, flags);
866 /* Callback to client */
867 callback = d40d_fin->txd.callback;
868 callback_param = d40d_fin->txd.callback_param;
870 if (async_tx_test_ack(&d40d_fin->txd)) {
871 d40_pool_lli_free(d40d_fin);
872 d40_desc_remove(d40d_fin);
873 /* Return desc to free-list */
874 d40_desc_free(d40c, d40d_fin);
876 if (!d40d_fin->is_in_client_list) {
877 d40_desc_remove(d40d_fin);
878 list_add_tail(&d40d_fin->node, &d40c->client);
879 d40d_fin->is_in_client_list = true;
885 if (d40c->pending_tx)
886 tasklet_schedule(&d40c->tasklet);
888 spin_unlock_irqrestore(&d40c->lock, flags);
891 callback(callback_param);
896 /* Rescue manouver if receiving double interrupts */
897 if (d40c->pending_tx > 0)
899 spin_unlock_irqrestore(&d40c->lock, flags);
902 static irqreturn_t d40_handle_interrupt(int irq, void *data)
904 static const struct d40_interrupt_lookup il[] = {
905 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
906 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
907 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
908 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
909 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
910 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
911 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
912 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
913 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
914 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
918 u32 regs[ARRAY_SIZE(il)];
923 struct d40_chan *d40c;
925 struct d40_base *base = data;
927 spin_lock_irqsave(&base->interrupt_lock, flags);
929 /* Read interrupt status of both logical and physical channels */
930 for (i = 0; i < ARRAY_SIZE(il); i++)
931 regs[i] = readl(base->virtbase + il[i].src);
935 chan = find_next_bit((unsigned long *)regs,
936 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
938 /* No more set bits found? */
939 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
942 row = chan / BITS_PER_LONG;
943 idx = chan & (BITS_PER_LONG - 1);
946 tmp = readl(base->virtbase + il[row].clr);
948 writel(tmp, base->virtbase + il[row].clr);
950 if (il[row].offset == D40_PHY_CHAN)
951 d40c = base->lookup_phy_chans[idx];
953 d40c = base->lookup_log_chans[il[row].offset + idx];
954 spin_lock(&d40c->lock);
956 if (!il[row].is_error)
960 "[%s] IRQ chan: %ld offset %d idx %d\n",
961 __func__, chan, il[row].offset, idx);
963 spin_unlock(&d40c->lock);
966 spin_unlock_irqrestore(&base->interrupt_lock, flags);
972 static int d40_validate_conf(struct d40_chan *d40c,
973 struct stedma40_chan_cfg *conf)
976 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
977 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
978 bool is_log = (conf->channel_type & STEDMA40_CHANNEL_IN_OPER_MODE)
979 == STEDMA40_CHANNEL_IN_LOG_MODE;
981 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH &&
982 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
983 dev_err(&d40c->chan.dev->device, "[%s] Invalid dst\n",
988 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM &&
989 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
990 dev_err(&d40c->chan.dev->device, "[%s] Invalid src\n",
995 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
996 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
997 dev_err(&d40c->chan.dev->device,
998 "[%s] No event line\n", __func__);
1002 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1003 (src_event_group != dst_event_group)) {
1004 dev_err(&d40c->chan.dev->device,
1005 "[%s] Invalid event group\n", __func__);
1009 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1011 * DMAC HW supports it. Will be added to this driver,
1012 * in case any dma client requires it.
1014 dev_err(&d40c->chan.dev->device,
1015 "[%s] periph to periph not supported\n",
1023 static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
1024 int log_event_line, bool is_log)
1026 unsigned long flags;
1027 spin_lock_irqsave(&phy->lock, flags);
1029 /* Physical interrupts are masked per physical full channel */
1030 if (phy->allocated_src == D40_ALLOC_FREE &&
1031 phy->allocated_dst == D40_ALLOC_FREE) {
1032 phy->allocated_dst = D40_ALLOC_PHY;
1033 phy->allocated_src = D40_ALLOC_PHY;
1039 /* Logical channel */
1041 if (phy->allocated_src == D40_ALLOC_PHY)
1044 if (phy->allocated_src == D40_ALLOC_FREE)
1045 phy->allocated_src = D40_ALLOC_LOG_FREE;
1047 if (!(phy->allocated_src & (1 << log_event_line))) {
1048 phy->allocated_src |= 1 << log_event_line;
1053 if (phy->allocated_dst == D40_ALLOC_PHY)
1056 if (phy->allocated_dst == D40_ALLOC_FREE)
1057 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1059 if (!(phy->allocated_dst & (1 << log_event_line))) {
1060 phy->allocated_dst |= 1 << log_event_line;
1067 spin_unlock_irqrestore(&phy->lock, flags);
1070 spin_unlock_irqrestore(&phy->lock, flags);
1074 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1077 unsigned long flags;
1078 bool is_free = false;
1080 spin_lock_irqsave(&phy->lock, flags);
1081 if (!log_event_line) {
1082 /* Physical interrupts are masked per physical full channel */
1083 phy->allocated_dst = D40_ALLOC_FREE;
1084 phy->allocated_src = D40_ALLOC_FREE;
1089 /* Logical channel */
1091 phy->allocated_src &= ~(1 << log_event_line);
1092 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1093 phy->allocated_src = D40_ALLOC_FREE;
1095 phy->allocated_dst &= ~(1 << log_event_line);
1096 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1097 phy->allocated_dst = D40_ALLOC_FREE;
1100 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1104 spin_unlock_irqrestore(&phy->lock, flags);
1109 static int d40_allocate_channel(struct d40_chan *d40c)
1114 struct d40_phy_res *phys;
1119 bool is_log = (d40c->dma_cfg.channel_type &
1120 STEDMA40_CHANNEL_IN_OPER_MODE)
1121 == STEDMA40_CHANNEL_IN_LOG_MODE;
1124 phys = d40c->base->phy_res;
1126 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1127 dev_type = d40c->dma_cfg.src_dev_type;
1128 log_num = 2 * dev_type;
1130 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1131 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1132 /* dst event lines are used for logical memcpy */
1133 dev_type = d40c->dma_cfg.dst_dev_type;
1134 log_num = 2 * dev_type + 1;
1139 event_group = D40_TYPE_TO_GROUP(dev_type);
1140 event_line = D40_TYPE_TO_EVENT(dev_type);
1143 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1144 /* Find physical half channel */
1145 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1147 if (d40_alloc_mask_set(&phys[i], is_src,
1152 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1153 int phy_num = j + event_group * 2;
1154 for (i = phy_num; i < phy_num + 2; i++) {
1155 if (d40_alloc_mask_set(&phys[i],
1164 d40c->phy_chan = &phys[i];
1165 d40c->log_num = D40_PHY_CHAN;
1171 /* Find logical channel */
1172 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1173 int phy_num = j + event_group * 2;
1175 * Spread logical channels across all available physical rather
1176 * than pack every logical channel at the first available phy
1180 for (i = phy_num; i < phy_num + 2; i++) {
1181 if (d40_alloc_mask_set(&phys[i], is_src,
1182 event_line, is_log))
1186 for (i = phy_num + 1; i >= phy_num; i--) {
1187 if (d40_alloc_mask_set(&phys[i], is_src,
1188 event_line, is_log))
1196 d40c->phy_chan = &phys[i];
1197 d40c->log_num = log_num;
1201 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1203 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1209 static int d40_config_memcpy(struct d40_chan *d40c)
1211 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1213 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1214 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1215 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1216 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1217 memcpy[d40c->chan.chan_id];
1219 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1220 dma_has_cap(DMA_SLAVE, cap)) {
1221 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1223 dev_err(&d40c->chan.dev->device, "[%s] No memcpy\n",
1232 static int d40_free_dma(struct d40_chan *d40c)
1237 struct d40_phy_res *phy = d40c->phy_chan;
1240 struct d40_desc *_d;
1243 /* Terminate all queued and active transfers */
1246 /* Release client owned descriptors */
1247 if (!list_empty(&d40c->client))
1248 list_for_each_entry_safe(d, _d, &d40c->client, node) {
1249 d40_pool_lli_free(d);
1251 /* Return desc to free-list */
1252 d40_desc_free(d40c, d);
1256 dev_err(&d40c->chan.dev->device, "[%s] phy == null\n",
1261 if (phy->allocated_src == D40_ALLOC_FREE &&
1262 phy->allocated_dst == D40_ALLOC_FREE) {
1263 dev_err(&d40c->chan.dev->device, "[%s] channel already free\n",
1268 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1269 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1270 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1272 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1273 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1276 dev_err(&d40c->chan.dev->device,
1277 "[%s] Unknown direction\n", __func__);
1281 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1283 dev_err(&d40c->chan.dev->device, "[%s] suspend failed\n",
1288 if (d40c->log_num != D40_PHY_CHAN) {
1289 /* Release logical channel, deactivate the event line */
1291 d40_config_set_event(d40c, false);
1292 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1295 * Check if there are more logical allocation
1296 * on this phy channel.
1298 if (!d40_alloc_mask_free(phy, is_src, event)) {
1299 /* Resume the other logical channels if any */
1300 if (d40_chan_has_events(d40c)) {
1301 res = d40_channel_execute_command(d40c,
1304 dev_err(&d40c->chan.dev->device,
1305 "[%s] Executing RUN command\n",
1313 (void) d40_alloc_mask_free(phy, is_src, 0);
1316 /* Release physical channel */
1317 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1319 dev_err(&d40c->chan.dev->device,
1320 "[%s] Failed to stop channel\n", __func__);
1323 d40c->phy_chan = NULL;
1324 /* Invalidate channel type */
1325 d40c->dma_cfg.channel_type = 0;
1326 d40c->base->lookup_phy_chans[phy->num] = NULL;
1331 static int d40_pause(struct dma_chan *chan)
1333 struct d40_chan *d40c =
1334 container_of(chan, struct d40_chan, chan);
1336 unsigned long flags;
1338 spin_lock_irqsave(&d40c->lock, flags);
1340 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1342 if (d40c->log_num != D40_PHY_CHAN) {
1343 d40_config_set_event(d40c, false);
1344 /* Resume the other logical channels if any */
1345 if (d40_chan_has_events(d40c))
1346 res = d40_channel_execute_command(d40c,
1351 spin_unlock_irqrestore(&d40c->lock, flags);
1355 static bool d40_is_paused(struct d40_chan *d40c)
1357 bool is_paused = false;
1358 unsigned long flags;
1359 void __iomem *active_reg;
1363 spin_lock_irqsave(&d40c->lock, flags);
1365 if (d40c->log_num == D40_PHY_CHAN) {
1366 if (d40c->phy_chan->num % 2 == 0)
1367 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1369 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1371 status = (readl(active_reg) &
1372 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1373 D40_CHAN_POS(d40c->phy_chan->num);
1374 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1380 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1381 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
1382 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1383 else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1384 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1386 dev_err(&d40c->chan.dev->device,
1387 "[%s] Unknown direction\n", __func__);
1390 status = d40_chan_has_events(d40c);
1391 status = (status & D40_EVENTLINE_MASK(event)) >>
1392 D40_EVENTLINE_POS(event);
1394 if (status != D40_DMA_RUN)
1397 spin_unlock_irqrestore(&d40c->lock, flags);
1403 static bool d40_tx_is_linked(struct d40_chan *d40c)
1407 if (d40c->log_num != D40_PHY_CHAN)
1408 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1410 is_link = readl(d40c->base->virtbase + D40_DREG_PCBASE +
1411 d40c->phy_chan->num * D40_DREG_PCDELTA +
1412 D40_CHAN_REG_SDLNK) &
1413 D40_SREG_LNK_PHYS_LNK_MASK;
1417 static u32 d40_residue(struct d40_chan *d40c)
1421 if (d40c->log_num != D40_PHY_CHAN)
1422 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1423 >> D40_MEM_LCSP2_ECNT_POS;
1425 num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE +
1426 d40c->phy_chan->num * D40_DREG_PCDELTA +
1427 D40_CHAN_REG_SDELT) &
1428 D40_SREG_ELEM_PHY_ECNT_MASK) >>
1429 D40_SREG_ELEM_PHY_ECNT_POS;
1430 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1433 static int d40_resume(struct dma_chan *chan)
1435 struct d40_chan *d40c =
1436 container_of(chan, struct d40_chan, chan);
1438 unsigned long flags;
1440 spin_lock_irqsave(&d40c->lock, flags);
1442 if (d40c->base->rev == 0)
1443 if (d40c->log_num != D40_PHY_CHAN) {
1444 res = d40_channel_execute_command(d40c,
1445 D40_DMA_SUSPEND_REQ);
1449 /* If bytes left to transfer or linked tx resume job */
1450 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
1451 if (d40c->log_num != D40_PHY_CHAN)
1452 d40_config_set_event(d40c, true);
1453 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1457 spin_unlock_irqrestore(&d40c->lock, flags);
1461 static u32 stedma40_residue(struct dma_chan *chan)
1463 struct d40_chan *d40c =
1464 container_of(chan, struct d40_chan, chan);
1466 unsigned long flags;
1468 spin_lock_irqsave(&d40c->lock, flags);
1469 bytes_left = d40_residue(d40c);
1470 spin_unlock_irqrestore(&d40c->lock, flags);
1475 /* Public DMA functions in addition to the DMA engine framework */
1477 int stedma40_set_psize(struct dma_chan *chan,
1481 struct d40_chan *d40c =
1482 container_of(chan, struct d40_chan, chan);
1483 unsigned long flags;
1485 spin_lock_irqsave(&d40c->lock, flags);
1487 if (d40c->log_num != D40_PHY_CHAN) {
1488 d40c->log_def.lcsp1 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
1489 d40c->log_def.lcsp3 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
1490 d40c->log_def.lcsp1 |= src_psize <<
1491 D40_MEM_LCSP1_SCFG_PSIZE_POS;
1492 d40c->log_def.lcsp3 |= dst_psize <<
1493 D40_MEM_LCSP1_SCFG_PSIZE_POS;
1497 if (src_psize == STEDMA40_PSIZE_PHY_1)
1498 d40c->src_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
1500 d40c->src_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
1501 d40c->src_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
1502 D40_SREG_CFG_PSIZE_POS);
1503 d40c->src_def_cfg |= src_psize << D40_SREG_CFG_PSIZE_POS;
1506 if (dst_psize == STEDMA40_PSIZE_PHY_1)
1507 d40c->dst_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
1509 d40c->dst_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
1510 d40c->dst_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
1511 D40_SREG_CFG_PSIZE_POS);
1512 d40c->dst_def_cfg |= dst_psize << D40_SREG_CFG_PSIZE_POS;
1515 spin_unlock_irqrestore(&d40c->lock, flags);
1518 EXPORT_SYMBOL(stedma40_set_psize);
1520 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
1521 struct scatterlist *sgl_dst,
1522 struct scatterlist *sgl_src,
1523 unsigned int sgl_len,
1524 unsigned long dma_flags)
1527 struct d40_desc *d40d;
1528 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1530 unsigned long flags;
1532 if (d40c->phy_chan == NULL) {
1533 dev_err(&d40c->chan.dev->device,
1534 "[%s] Unallocated channel.\n", __func__);
1535 return ERR_PTR(-EINVAL);
1538 spin_lock_irqsave(&d40c->lock, flags);
1539 d40d = d40_desc_get(d40c);
1544 d40d->lli_len = sgl_len;
1545 d40d->lli_tx_len = d40d->lli_len;
1546 d40d->txd.flags = dma_flags;
1548 if (d40c->log_num != D40_PHY_CHAN) {
1549 if (d40d->lli_len > d40c->base->plat_data->llis_per_log)
1550 d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
1554 * Check if there is space available in lcla. If not,
1555 * split list into 1-length and run only in lcpa
1558 if (d40_lcla_id_get(d40c) != 0)
1559 d40d->lli_tx_len = 1;
1561 if (d40_pool_lli_alloc(d40d, sgl_len, true) < 0) {
1562 dev_err(&d40c->chan.dev->device,
1563 "[%s] Out of memory\n", __func__);
1567 (void) d40_log_sg_to_lli(d40c->lcla.src_id,
1571 d40c->log_def.lcsp1,
1572 d40c->dma_cfg.src_info.data_width,
1573 dma_flags & DMA_PREP_INTERRUPT,
1575 d40c->base->plat_data->llis_per_log);
1577 (void) d40_log_sg_to_lli(d40c->lcla.dst_id,
1581 d40c->log_def.lcsp3,
1582 d40c->dma_cfg.dst_info.data_width,
1583 dma_flags & DMA_PREP_INTERRUPT,
1585 d40c->base->plat_data->llis_per_log);
1589 if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
1590 dev_err(&d40c->chan.dev->device,
1591 "[%s] Out of memory\n", __func__);
1595 res = d40_phy_sg_to_lli(sgl_src,
1599 d40d->lli_phy.src_addr,
1601 d40c->dma_cfg.src_info.data_width,
1602 d40c->dma_cfg.src_info.psize,
1608 res = d40_phy_sg_to_lli(sgl_dst,
1612 d40d->lli_phy.dst_addr,
1614 d40c->dma_cfg.dst_info.data_width,
1615 d40c->dma_cfg.dst_info.psize,
1621 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1622 d40d->lli_pool.size, DMA_TO_DEVICE);
1625 dma_async_tx_descriptor_init(&d40d->txd, chan);
1627 d40d->txd.tx_submit = d40_tx_submit;
1629 spin_unlock_irqrestore(&d40c->lock, flags);
1633 spin_unlock_irqrestore(&d40c->lock, flags);
1636 EXPORT_SYMBOL(stedma40_memcpy_sg);
1638 bool stedma40_filter(struct dma_chan *chan, void *data)
1640 struct stedma40_chan_cfg *info = data;
1641 struct d40_chan *d40c =
1642 container_of(chan, struct d40_chan, chan);
1646 err = d40_validate_conf(d40c, info);
1648 d40c->dma_cfg = *info;
1650 err = d40_config_memcpy(d40c);
1654 EXPORT_SYMBOL(stedma40_filter);
1656 /* DMA ENGINE functions */
1657 static int d40_alloc_chan_resources(struct dma_chan *chan)
1660 unsigned long flags;
1661 struct d40_chan *d40c =
1662 container_of(chan, struct d40_chan, chan);
1664 spin_lock_irqsave(&d40c->lock, flags);
1666 d40c->completed = chan->cookie = 1;
1669 * If no dma configuration is set (channel_type == 0)
1670 * use default configuration (memcpy)
1672 if (d40c->dma_cfg.channel_type == 0) {
1673 err = d40_config_memcpy(d40c);
1675 dev_err(&d40c->chan.dev->device,
1676 "[%s] Failed to configure memcpy channel\n",
1681 is_free_phy = (d40c->phy_chan == NULL);
1683 err = d40_allocate_channel(d40c);
1685 dev_err(&d40c->chan.dev->device,
1686 "[%s] Failed to allocate channel\n", __func__);
1690 /* Fill in basic CFG register values */
1691 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1692 &d40c->dst_def_cfg, d40c->log_num != D40_PHY_CHAN);
1694 if (d40c->log_num != D40_PHY_CHAN) {
1695 d40_log_cfg(&d40c->dma_cfg,
1696 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1698 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1699 d40c->lcpa = d40c->base->lcpa_base +
1700 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1702 d40c->lcpa = d40c->base->lcpa_base +
1703 d40c->dma_cfg.dst_dev_type *
1704 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1708 * Only write channel configuration to the DMA if the physical
1709 * resource is free. In case of multiple logical channels
1710 * on the same physical resource, only the first write is necessary.
1713 err = d40_config_write(d40c);
1715 dev_err(&d40c->chan.dev->device,
1716 "[%s] Failed to configure channel\n",
1721 spin_unlock_irqrestore(&d40c->lock, flags);
1725 static void d40_free_chan_resources(struct dma_chan *chan)
1727 struct d40_chan *d40c =
1728 container_of(chan, struct d40_chan, chan);
1730 unsigned long flags;
1732 if (d40c->phy_chan == NULL) {
1733 dev_err(&d40c->chan.dev->device,
1734 "[%s] Cannot free unallocated channel\n", __func__);
1739 spin_lock_irqsave(&d40c->lock, flags);
1741 err = d40_free_dma(d40c);
1744 dev_err(&d40c->chan.dev->device,
1745 "[%s] Failed to free channel\n", __func__);
1746 spin_unlock_irqrestore(&d40c->lock, flags);
1749 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1753 unsigned long dma_flags)
1755 struct d40_desc *d40d;
1756 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1758 unsigned long flags;
1761 if (d40c->phy_chan == NULL) {
1762 dev_err(&d40c->chan.dev->device,
1763 "[%s] Channel is not allocated.\n", __func__);
1764 return ERR_PTR(-EINVAL);
1767 spin_lock_irqsave(&d40c->lock, flags);
1768 d40d = d40_desc_get(d40c);
1771 dev_err(&d40c->chan.dev->device,
1772 "[%s] Descriptor is NULL\n", __func__);
1776 d40d->txd.flags = dma_flags;
1778 dma_async_tx_descriptor_init(&d40d->txd, chan);
1780 d40d->txd.tx_submit = d40_tx_submit;
1782 if (d40c->log_num != D40_PHY_CHAN) {
1784 if (d40_pool_lli_alloc(d40d, 1, true) < 0) {
1785 dev_err(&d40c->chan.dev->device,
1786 "[%s] Out of memory\n", __func__);
1790 d40d->lli_tx_len = 1;
1792 d40_log_fill_lli(d40d->lli_log.src,
1796 d40c->log_def.lcsp1,
1797 d40c->dma_cfg.src_info.data_width,
1800 d40_log_fill_lli(d40d->lli_log.dst,
1804 d40c->log_def.lcsp3,
1805 d40c->dma_cfg.dst_info.data_width,
1810 if (d40_pool_lli_alloc(d40d, 1, false) < 0) {
1811 dev_err(&d40c->chan.dev->device,
1812 "[%s] Out of memory\n", __func__);
1816 err = d40_phy_fill_lli(d40d->lli_phy.src,
1819 d40c->dma_cfg.src_info.psize,
1823 d40c->dma_cfg.src_info.data_width,
1828 err = d40_phy_fill_lli(d40d->lli_phy.dst,
1831 d40c->dma_cfg.dst_info.psize,
1835 d40c->dma_cfg.dst_info.data_width,
1841 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1842 d40d->lli_pool.size, DMA_TO_DEVICE);
1845 spin_unlock_irqrestore(&d40c->lock, flags);
1849 dev_err(&d40c->chan.dev->device,
1850 "[%s] Failed filling in PHY LLI\n", __func__);
1851 d40_pool_lli_free(d40d);
1853 spin_unlock_irqrestore(&d40c->lock, flags);
1857 static int d40_prep_slave_sg_log(struct d40_desc *d40d,
1858 struct d40_chan *d40c,
1859 struct scatterlist *sgl,
1860 unsigned int sg_len,
1861 enum dma_data_direction direction,
1862 unsigned long dma_flags)
1864 dma_addr_t dev_addr = 0;
1867 if (d40_pool_lli_alloc(d40d, sg_len, true) < 0) {
1868 dev_err(&d40c->chan.dev->device,
1869 "[%s] Out of memory\n", __func__);
1873 d40d->lli_len = sg_len;
1874 if (d40d->lli_len <= d40c->base->plat_data->llis_per_log)
1875 d40d->lli_tx_len = d40d->lli_len;
1877 d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
1881 * Check if there is space available in lcla.
1882 * If not, split list into 1-length and run only
1885 if (d40_lcla_id_get(d40c) != 0)
1886 d40d->lli_tx_len = 1;
1888 if (direction == DMA_FROM_DEVICE)
1889 dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1890 else if (direction == DMA_TO_DEVICE)
1891 dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1895 total_size = d40_log_sg_to_dev(&d40c->lcla,
1899 d40c->dma_cfg.src_info.data_width,
1900 d40c->dma_cfg.dst_info.data_width,
1902 dma_flags & DMA_PREP_INTERRUPT,
1903 dev_addr, d40d->lli_tx_len,
1904 d40c->base->plat_data->llis_per_log);
1912 static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
1913 struct d40_chan *d40c,
1914 struct scatterlist *sgl,
1915 unsigned int sgl_len,
1916 enum dma_data_direction direction,
1917 unsigned long dma_flags)
1919 dma_addr_t src_dev_addr;
1920 dma_addr_t dst_dev_addr;
1923 if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
1924 dev_err(&d40c->chan.dev->device,
1925 "[%s] Out of memory\n", __func__);
1929 d40d->lli_len = sgl_len;
1930 d40d->lli_tx_len = sgl_len;
1932 if (direction == DMA_FROM_DEVICE) {
1934 src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1935 } else if (direction == DMA_TO_DEVICE) {
1936 dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1941 res = d40_phy_sg_to_lli(sgl,
1945 d40d->lli_phy.src_addr,
1947 d40c->dma_cfg.src_info.data_width,
1948 d40c->dma_cfg.src_info.psize,
1953 res = d40_phy_sg_to_lli(sgl,
1957 d40d->lli_phy.dst_addr,
1959 d40c->dma_cfg.dst_info.data_width,
1960 d40c->dma_cfg.dst_info.psize,
1965 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1966 d40d->lli_pool.size, DMA_TO_DEVICE);
1970 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
1971 struct scatterlist *sgl,
1972 unsigned int sg_len,
1973 enum dma_data_direction direction,
1974 unsigned long dma_flags)
1976 struct d40_desc *d40d;
1977 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1979 unsigned long flags;
1982 if (d40c->phy_chan == NULL) {
1983 dev_err(&d40c->chan.dev->device,
1984 "[%s] Cannot prepare unallocated channel\n", __func__);
1985 return ERR_PTR(-EINVAL);
1988 if (d40c->dma_cfg.pre_transfer)
1989 d40c->dma_cfg.pre_transfer(chan,
1990 d40c->dma_cfg.pre_transfer_data,
1993 spin_lock_irqsave(&d40c->lock, flags);
1994 d40d = d40_desc_get(d40c);
1995 spin_unlock_irqrestore(&d40c->lock, flags);
2000 if (d40c->log_num != D40_PHY_CHAN)
2001 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2002 direction, dma_flags);
2004 err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
2005 direction, dma_flags);
2007 dev_err(&d40c->chan.dev->device,
2008 "[%s] Failed to prepare %s slave sg job: %d\n",
2010 d40c->log_num != D40_PHY_CHAN ? "log" : "phy", err);
2014 d40d->txd.flags = dma_flags;
2016 dma_async_tx_descriptor_init(&d40d->txd, chan);
2018 d40d->txd.tx_submit = d40_tx_submit;
2023 static enum dma_status d40_tx_status(struct dma_chan *chan,
2024 dma_cookie_t cookie,
2025 struct dma_tx_state *txstate)
2027 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2028 dma_cookie_t last_used;
2029 dma_cookie_t last_complete;
2032 if (d40c->phy_chan == NULL) {
2033 dev_err(&d40c->chan.dev->device,
2034 "[%s] Cannot read status of unallocated channel\n",
2039 last_complete = d40c->completed;
2040 last_used = chan->cookie;
2042 if (d40_is_paused(d40c))
2045 ret = dma_async_is_complete(cookie, last_complete, last_used);
2047 dma_set_tx_state(txstate, last_complete, last_used,
2048 stedma40_residue(chan));
2053 static void d40_issue_pending(struct dma_chan *chan)
2055 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2056 unsigned long flags;
2058 if (d40c->phy_chan == NULL) {
2059 dev_err(&d40c->chan.dev->device,
2060 "[%s] Channel is not allocated!\n", __func__);
2064 spin_lock_irqsave(&d40c->lock, flags);
2066 /* Busy means that pending jobs are already being processed */
2068 (void) d40_queue_start(d40c);
2070 spin_unlock_irqrestore(&d40c->lock, flags);
2073 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2076 unsigned long flags;
2077 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2079 if (d40c->phy_chan == NULL) {
2080 dev_err(&d40c->chan.dev->device,
2081 "[%s] Channel is not allocated!\n", __func__);
2086 case DMA_TERMINATE_ALL:
2087 spin_lock_irqsave(&d40c->lock, flags);
2089 spin_unlock_irqrestore(&d40c->lock, flags);
2092 return d40_pause(chan);
2094 return d40_resume(chan);
2097 /* Other commands are unimplemented */
2101 /* Initialization functions */
2103 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2104 struct d40_chan *chans, int offset,
2108 struct d40_chan *d40c;
2110 INIT_LIST_HEAD(&dma->channels);
2112 for (i = offset; i < offset + num_chans; i++) {
2115 d40c->chan.device = dma;
2117 /* Invalidate lcla element */
2118 d40c->lcla.src_id = -1;
2119 d40c->lcla.dst_id = -1;
2121 spin_lock_init(&d40c->lock);
2123 d40c->log_num = D40_PHY_CHAN;
2125 INIT_LIST_HEAD(&d40c->active);
2126 INIT_LIST_HEAD(&d40c->queue);
2127 INIT_LIST_HEAD(&d40c->client);
2129 tasklet_init(&d40c->tasklet, dma_tasklet,
2130 (unsigned long) d40c);
2132 list_add_tail(&d40c->chan.device_node,
2137 static int __init d40_dmaengine_init(struct d40_base *base,
2138 int num_reserved_chans)
2142 d40_chan_init(base, &base->dma_slave, base->log_chans,
2143 0, base->num_log_chans);
2145 dma_cap_zero(base->dma_slave.cap_mask);
2146 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2148 base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2149 base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2150 base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
2151 base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2152 base->dma_slave.device_tx_status = d40_tx_status;
2153 base->dma_slave.device_issue_pending = d40_issue_pending;
2154 base->dma_slave.device_control = d40_control;
2155 base->dma_slave.dev = base->dev;
2157 err = dma_async_device_register(&base->dma_slave);
2161 "[%s] Failed to register slave channels\n",
2166 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2167 base->num_log_chans, base->plat_data->memcpy_len);
2169 dma_cap_zero(base->dma_memcpy.cap_mask);
2170 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2172 base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2173 base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2174 base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
2175 base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2176 base->dma_memcpy.device_tx_status = d40_tx_status;
2177 base->dma_memcpy.device_issue_pending = d40_issue_pending;
2178 base->dma_memcpy.device_control = d40_control;
2179 base->dma_memcpy.dev = base->dev;
2181 * This controller can only access address at even
2182 * 32bit boundaries, i.e. 2^2
2184 base->dma_memcpy.copy_align = 2;
2186 err = dma_async_device_register(&base->dma_memcpy);
2190 "[%s] Failed to regsiter memcpy only channels\n",
2195 d40_chan_init(base, &base->dma_both, base->phy_chans,
2196 0, num_reserved_chans);
2198 dma_cap_zero(base->dma_both.cap_mask);
2199 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2200 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2202 base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2203 base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2204 base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
2205 base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2206 base->dma_both.device_tx_status = d40_tx_status;
2207 base->dma_both.device_issue_pending = d40_issue_pending;
2208 base->dma_both.device_control = d40_control;
2209 base->dma_both.dev = base->dev;
2210 base->dma_both.copy_align = 2;
2211 err = dma_async_device_register(&base->dma_both);
2215 "[%s] Failed to register logical and physical capable channels\n",
2221 dma_async_device_unregister(&base->dma_memcpy);
2223 dma_async_device_unregister(&base->dma_slave);
2228 /* Initialization functions. */
2230 static int __init d40_phy_res_init(struct d40_base *base)
2233 int num_phy_chans_avail = 0;
2235 int odd_even_bit = -2;
2237 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2238 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2240 for (i = 0; i < base->num_phy_chans; i++) {
2241 base->phy_res[i].num = i;
2242 odd_even_bit += 2 * ((i % 2) == 0);
2243 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2244 /* Mark security only channels as occupied */
2245 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2246 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2248 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2249 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2250 num_phy_chans_avail++;
2252 spin_lock_init(&base->phy_res[i].lock);
2255 /* Mark disabled channels as occupied */
2256 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
2257 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2258 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2259 num_phy_chans_avail--;
2262 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2263 num_phy_chans_avail, base->num_phy_chans);
2265 /* Verify settings extended vs standard */
2266 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2268 for (i = 0; i < base->num_phy_chans; i++) {
2270 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2271 (val[0] & 0x3) != 1)
2273 "[%s] INFO: channel %d is misconfigured (%d)\n",
2274 __func__, i, val[0] & 0x3);
2276 val[0] = val[0] >> 2;
2279 return num_phy_chans_avail;
2282 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2284 static const struct d40_reg_val dma_id_regs[] = {
2286 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2287 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2289 * D40_DREG_PERIPHID2 Depends on HW revision:
2290 * MOP500/HREF ED has 0x0008,
2292 * HREF V1 has 0x0028
2294 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2297 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2298 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2299 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2300 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2302 struct stedma40_platform_data *plat_data;
2303 struct clk *clk = NULL;
2304 void __iomem *virtbase = NULL;
2305 struct resource *res = NULL;
2306 struct d40_base *base = NULL;
2307 int num_log_chans = 0;
2312 clk = clk_get(&pdev->dev, NULL);
2315 dev_err(&pdev->dev, "[%s] No matching clock found\n",
2322 /* Get IO for DMAC base address */
2323 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2327 if (request_mem_region(res->start, resource_size(res),
2328 D40_NAME " I/O base") == NULL)
2331 virtbase = ioremap(res->start, resource_size(res));
2335 /* HW version check */
2336 for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2337 if (dma_id_regs[i].val !=
2338 readl(virtbase + dma_id_regs[i].reg)) {
2340 "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2344 readl(virtbase + dma_id_regs[i].reg));
2349 /* Get silicon revision */
2350 val = readl(virtbase + D40_DREG_PERIPHID2);
2352 if ((val & 0xf) != D40_PERIPHID2_DESIGNER) {
2354 "[%s] Unknown designer! Got %x wanted %x\n",
2355 __func__, val & 0xf, D40_PERIPHID2_DESIGNER);
2359 /* The number of physical channels on this HW */
2360 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2362 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
2363 (val >> 4) & 0xf, res->start);
2365 plat_data = pdev->dev.platform_data;
2367 /* Count the number of logical channels in use */
2368 for (i = 0; i < plat_data->dev_len; i++)
2369 if (plat_data->dev_rx[i] != 0)
2372 for (i = 0; i < plat_data->dev_len; i++)
2373 if (plat_data->dev_tx[i] != 0)
2376 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2377 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2378 sizeof(struct d40_chan), GFP_KERNEL);
2381 dev_err(&pdev->dev, "[%s] Out of memory\n", __func__);
2385 base->rev = (val >> 4) & 0xf;
2387 base->num_phy_chans = num_phy_chans;
2388 base->num_log_chans = num_log_chans;
2389 base->phy_start = res->start;
2390 base->phy_size = resource_size(res);
2391 base->virtbase = virtbase;
2392 base->plat_data = plat_data;
2393 base->dev = &pdev->dev;
2394 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2395 base->log_chans = &base->phy_chans[num_phy_chans];
2397 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2402 base->lookup_phy_chans = kzalloc(num_phy_chans *
2403 sizeof(struct d40_chan *),
2405 if (!base->lookup_phy_chans)
2408 if (num_log_chans + plat_data->memcpy_len) {
2410 * The max number of logical channels are event lines for all
2411 * src devices and dst devices
2413 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2414 sizeof(struct d40_chan *),
2416 if (!base->lookup_log_chans)
2419 base->lcla_pool.alloc_map = kzalloc(num_phy_chans * sizeof(u32),
2421 if (!base->lcla_pool.alloc_map)
2424 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2425 0, SLAB_HWCACHE_ALIGN,
2427 if (base->desc_slab == NULL)
2440 release_mem_region(res->start,
2441 resource_size(res));
2446 kfree(base->lcla_pool.alloc_map);
2447 kfree(base->lookup_log_chans);
2448 kfree(base->lookup_phy_chans);
2449 kfree(base->phy_res);
2456 static void __init d40_hw_init(struct d40_base *base)
2459 static const struct d40_reg_val dma_init_reg[] = {
2460 /* Clock every part of the DMA block from start */
2461 { .reg = D40_DREG_GCC, .val = 0x0000ff01},
2463 /* Interrupts on all logical channels */
2464 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2465 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2466 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2467 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2468 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2469 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2470 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2471 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2472 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2473 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2474 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2475 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2478 u32 prmseo[2] = {0, 0};
2479 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2483 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2484 writel(dma_init_reg[i].val,
2485 base->virtbase + dma_init_reg[i].reg);
2487 /* Configure all our dma channels to default settings */
2488 for (i = 0; i < base->num_phy_chans; i++) {
2490 activeo[i % 2] = activeo[i % 2] << 2;
2492 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2494 activeo[i % 2] |= 3;
2498 /* Enable interrupt # */
2499 pcmis = (pcmis << 1) | 1;
2501 /* Clear interrupt # */
2502 pcicr = (pcicr << 1) | 1;
2504 /* Set channel to physical mode */
2505 prmseo[i % 2] = prmseo[i % 2] << 2;
2510 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2511 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2512 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2513 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2515 /* Write which interrupt to enable */
2516 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2518 /* Write which interrupt to clear */
2519 writel(pcicr, base->virtbase + D40_DREG_PCICR);
2523 static int __init d40_lcla_allocate(struct d40_base *base)
2525 unsigned long *page_list;
2530 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2531 * To full fill this hardware requirement without wasting 256 kb
2532 * we allocate pages until we get an aligned one.
2534 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2542 /* Calculating how many pages that are required */
2543 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2545 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2546 page_list[i] = __get_free_pages(GFP_KERNEL,
2547 base->lcla_pool.pages);
2548 if (!page_list[i]) {
2551 "[%s] Failed to allocate %d pages.\n",
2552 __func__, base->lcla_pool.pages);
2554 for (j = 0; j < i; j++)
2555 free_pages(page_list[j], base->lcla_pool.pages);
2559 if ((virt_to_phys((void *)page_list[i]) &
2560 (LCLA_ALIGNMENT - 1)) == 0)
2564 for (j = 0; j < i; j++)
2565 free_pages(page_list[j], base->lcla_pool.pages);
2567 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2568 base->lcla_pool.base = (void *)page_list[i];
2570 /* After many attempts, no succees with finding the correct
2571 * alignment try with allocating a big buffer */
2573 "[%s] Failed to get %d pages @ 18 bit align.\n",
2574 __func__, base->lcla_pool.pages);
2575 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2576 base->num_phy_chans +
2579 if (!base->lcla_pool.base_unaligned) {
2584 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2588 writel(virt_to_phys(base->lcla_pool.base),
2589 base->virtbase + D40_DREG_LCLA);
2595 static int __init d40_probe(struct platform_device *pdev)
2599 struct d40_base *base;
2600 struct resource *res = NULL;
2601 int num_reserved_chans;
2604 base = d40_hw_detect_init(pdev);
2609 num_reserved_chans = d40_phy_res_init(base);
2611 platform_set_drvdata(pdev, base);
2613 spin_lock_init(&base->interrupt_lock);
2614 spin_lock_init(&base->execmd_lock);
2616 /* Get IO for logical channel parameter address */
2617 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2621 "[%s] No \"lcpa\" memory resource\n",
2625 base->lcpa_size = resource_size(res);
2626 base->phy_lcpa = res->start;
2628 if (request_mem_region(res->start, resource_size(res),
2629 D40_NAME " I/O lcpa") == NULL) {
2632 "[%s] Failed to request LCPA region 0x%x-0x%x\n",
2633 __func__, res->start, res->end);
2637 /* We make use of ESRAM memory for this. */
2638 val = readl(base->virtbase + D40_DREG_LCPA);
2639 if (res->start != val && val != 0) {
2640 dev_warn(&pdev->dev,
2641 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2642 __func__, val, res->start);
2644 writel(res->start, base->virtbase + D40_DREG_LCPA);
2646 base->lcpa_base = ioremap(res->start, resource_size(res));
2647 if (!base->lcpa_base) {
2650 "[%s] Failed to ioremap LCPA region\n",
2655 ret = d40_lcla_allocate(base);
2657 dev_err(&pdev->dev, "[%s] Failed to allocate LCLA area\n",
2662 spin_lock_init(&base->lcla_pool.lock);
2664 base->lcla_pool.num_blocks = base->num_phy_chans;
2666 base->irq = platform_get_irq(pdev, 0);
2668 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
2671 dev_err(&pdev->dev, "[%s] No IRQ defined\n", __func__);
2675 err = d40_dmaengine_init(base, num_reserved_chans);
2681 dev_info(base->dev, "initialized\n");
2686 if (base->desc_slab)
2687 kmem_cache_destroy(base->desc_slab);
2689 iounmap(base->virtbase);
2690 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2691 free_pages((unsigned long)base->lcla_pool.base,
2692 base->lcla_pool.pages);
2693 if (base->lcla_pool.base_unaligned)
2694 kfree(base->lcla_pool.base_unaligned);
2696 release_mem_region(base->phy_lcpa,
2698 if (base->phy_start)
2699 release_mem_region(base->phy_start,
2702 clk_disable(base->clk);
2706 kfree(base->lcla_pool.alloc_map);
2707 kfree(base->lookup_log_chans);
2708 kfree(base->lookup_phy_chans);
2709 kfree(base->phy_res);
2713 dev_err(&pdev->dev, "[%s] probe failed\n", __func__);
2717 static struct platform_driver d40_driver = {
2719 .owner = THIS_MODULE,
2724 int __init stedma40_init(void)
2726 return platform_driver_probe(&d40_driver, d40_probe);
2728 arch_initcall(stedma40_init);