2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
8 #include <linux/kernel.h>
9 #include <linux/platform_data/dma-ste-dma40.h>
11 #include "ste_dma40_ll.h"
13 /* Sets up proper LCSP1 and LCSP3 register for a logical channel */
14 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
15 u32 *lcsp1, u32 *lcsp3)
20 /* src is mem? -> increase address pos */
21 if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
22 cfg->dir == STEDMA40_MEM_TO_MEM)
23 l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
25 /* dst is mem? -> increase address pos */
26 if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
27 cfg->dir == STEDMA40_MEM_TO_MEM)
28 l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
30 /* src is hw? -> master port 1 */
31 if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
32 cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
33 l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
35 /* dst is hw? -> master port 1 */
36 if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
37 cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
38 l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
40 l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
41 l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
42 l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
44 l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
45 l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
46 l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
53 void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
58 if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) ||
59 (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
60 /* Set master port to 1 */
61 src |= 1 << D40_SREG_CFG_MST_POS;
62 src |= D40_TYPE_TO_EVENT(cfg->dev_type);
64 if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
65 src |= 1 << D40_SREG_CFG_PHY_TM_POS;
67 src |= 3 << D40_SREG_CFG_PHY_TM_POS;
69 if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) ||
70 (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
71 /* Set master port to 1 */
72 dst |= 1 << D40_SREG_CFG_MST_POS;
73 dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
75 if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
76 dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
78 dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
80 /* Interrupt on end of transfer for destination */
81 dst |= 1 << D40_SREG_CFG_TIM_POS;
83 /* Generate interrupt on error */
84 src |= 1 << D40_SREG_CFG_EIM_POS;
85 dst |= 1 << D40_SREG_CFG_EIM_POS;
88 if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
89 src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
90 src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
92 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
93 dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
94 dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
98 src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
99 dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
101 /* Set the priority bit to high for the physical channel */
102 if (cfg->high_priority) {
103 src |= 1 << D40_SREG_CFG_PRI_POS;
104 dst |= 1 << D40_SREG_CFG_PRI_POS;
107 if (cfg->src_info.big_endian)
108 src |= 1 << D40_SREG_CFG_LBE_POS;
109 if (cfg->dst_info.big_endian)
110 dst |= 1 << D40_SREG_CFG_LBE_POS;
116 static int d40_phy_fill_lli(struct d40_phy_lli *lli,
121 struct stedma40_half_channel_info *info,
124 bool addr_inc = flags & LLI_ADDR_INC;
125 bool term_int = flags & LLI_TERM_INT;
126 unsigned int data_width = info->data_width;
127 int psize = info->psize;
130 if (psize == STEDMA40_PSIZE_PHY_1)
133 num_elems = 2 << psize;
135 /* Must be aligned */
136 if (!IS_ALIGNED(data, 0x1 << data_width))
139 /* Transfer size can't be smaller than (num_elms * elem_size) */
140 if (data_size < num_elems * (0x1 << data_width))
143 /* The number of elements. IE now many chunks */
144 lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
147 * Distance to next element sized entry.
148 * Usually the size of the element unless you want gaps.
151 lli->reg_elt |= (0x1 << data_width) <<
152 D40_SREG_ELEM_PHY_EIDX_POS;
154 /* Where the data is */
156 lli->reg_cfg = reg_cfg;
158 /* If this scatter list entry is the last one, no next link */
160 lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
162 lli->reg_lnk = next_lli;
164 /* Set/clear interrupt generation on this link item.*/
166 lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
168 lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
171 lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
176 static int d40_seg_size(int size, int data_width1, int data_width2)
178 u32 max_w = max(data_width1, data_width2);
179 u32 min_w = min(data_width1, data_width2);
180 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
182 if (seg_max > STEDMA40_MAX_SEG_SIZE)
183 seg_max -= (1 << max_w);
188 if (size <= 2 * seg_max)
189 return ALIGN(size / 2, 1 << max_w);
194 static struct d40_phy_lli *
195 d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
196 dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
197 struct stedma40_half_channel_info *info,
198 struct stedma40_half_channel_info *otherinfo,
201 bool lastlink = flags & LLI_LAST_LINK;
202 bool addr_inc = flags & LLI_ADDR_INC;
203 bool term_int = flags & LLI_TERM_INT;
204 bool cyclic = flags & LLI_CYCLIC;
206 dma_addr_t next = lli_phys;
207 int size_rest = size;
211 * This piece may be split up based on d40_seg_size(); we only want the
212 * term int on the last part.
215 flags &= ~LLI_TERM_INT;
218 size_seg = d40_seg_size(size_rest, info->data_width,
219 otherinfo->data_width);
220 size_rest -= size_seg;
222 if (size_rest == 0 && term_int)
223 flags |= LLI_TERM_INT;
225 if (size_rest == 0 && lastlink)
226 next = cyclic ? first_phys : 0;
228 next = ALIGN(next + sizeof(struct d40_phy_lli),
231 err = d40_phy_fill_lli(lli, addr, size_seg, next,
232 reg_cfg, info, flags);
248 int d40_phy_sg_to_lli(struct scatterlist *sg,
251 struct d40_phy_lli *lli_sg,
254 struct stedma40_half_channel_info *info,
255 struct stedma40_half_channel_info *otherinfo,
260 struct scatterlist *current_sg = sg;
261 struct d40_phy_lli *lli = lli_sg;
262 dma_addr_t l_phys = lli_phys;
265 flags |= LLI_ADDR_INC;
267 for_each_sg(sg, current_sg, sg_len, i) {
268 dma_addr_t sg_addr = sg_dma_address(current_sg);
269 unsigned int len = sg_dma_len(current_sg);
270 dma_addr_t dst = target ?: sg_addr;
272 total_size += sg_dma_len(current_sg);
275 flags |= LLI_TERM_INT | LLI_LAST_LINK;
277 l_phys = ALIGN(lli_phys + (lli - lli_sg) *
278 sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
280 lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
281 reg_cfg, info, otherinfo, flags);
291 /* DMA logical lli operations */
293 static void d40_log_lli_link(struct d40_log_lli *lli_dst,
294 struct d40_log_lli *lli_src,
295 int next, unsigned int flags)
297 bool interrupt = flags & LLI_TERM_INT;
301 if (next != -EINVAL) {
307 lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
308 lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
311 lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
312 (slos << D40_MEM_LCSP1_SLOS_POS);
314 lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
315 (dlos << D40_MEM_LCSP1_SLOS_POS);
318 void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
319 struct d40_log_lli *lli_dst,
320 struct d40_log_lli *lli_src,
321 int next, unsigned int flags)
323 d40_log_lli_link(lli_dst, lli_src, next, flags);
325 writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
326 writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
327 writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
328 writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
331 void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
332 struct d40_log_lli *lli_dst,
333 struct d40_log_lli *lli_src,
334 int next, unsigned int flags)
336 d40_log_lli_link(lli_dst, lli_src, next, flags);
338 writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
339 writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
340 writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
341 writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
344 static void d40_log_fill_lli(struct d40_log_lli *lli,
345 dma_addr_t data, u32 data_size,
350 bool addr_inc = flags & LLI_ADDR_INC;
352 lli->lcsp13 = reg_cfg;
354 /* The number of elements to transfer */
355 lli->lcsp02 = ((data_size >> data_width) <<
356 D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
358 BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);
360 /* 16 LSBs address of the current element */
361 lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
362 /* 16 MSBs address of the current element */
363 lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
366 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
370 static struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
373 u32 lcsp13, /* src or dst*/
378 bool addr_inc = flags & LLI_ADDR_INC;
379 struct d40_log_lli *lli = lli_sg;
380 int size_rest = size;
384 size_seg = d40_seg_size(size_rest, data_width1, data_width2);
385 size_rest -= size_seg;
387 d40_log_fill_lli(lli,
400 int d40_log_sg_to_lli(struct scatterlist *sg,
403 struct d40_log_lli *lli_sg,
404 u32 lcsp13, /* src or dst*/
405 u32 data_width1, u32 data_width2)
408 struct scatterlist *current_sg = sg;
410 struct d40_log_lli *lli = lli_sg;
411 unsigned long flags = 0;
414 flags |= LLI_ADDR_INC;
416 for_each_sg(sg, current_sg, sg_len, i) {
417 dma_addr_t sg_addr = sg_dma_address(current_sg);
418 unsigned int len = sg_dma_len(current_sg);
419 dma_addr_t addr = dev_addr ?: sg_addr;
421 total_size += sg_dma_len(current_sg);
423 lli = d40_log_buf_to_lli(lli, addr, len,