2 * DMA driver for Nvidia's Tegra20 APB DMA controller.
4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/bitops.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
29 #include <linux/module.h>
31 #include <linux/of_device.h>
32 #include <linux/of_dma.h>
33 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/reset.h>
37 #include <linux/slab.h>
39 #include "dmaengine.h"
41 #define TEGRA_APBDMA_GENERAL 0x0
42 #define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
44 #define TEGRA_APBDMA_CONTROL 0x010
45 #define TEGRA_APBDMA_IRQ_MASK 0x01c
46 #define TEGRA_APBDMA_IRQ_MASK_SET 0x020
49 #define TEGRA_APBDMA_CHAN_CSR 0x00
50 #define TEGRA_APBDMA_CSR_ENB BIT(31)
51 #define TEGRA_APBDMA_CSR_IE_EOC BIT(30)
52 #define TEGRA_APBDMA_CSR_HOLD BIT(29)
53 #define TEGRA_APBDMA_CSR_DIR BIT(28)
54 #define TEGRA_APBDMA_CSR_ONCE BIT(27)
55 #define TEGRA_APBDMA_CSR_FLOW BIT(21)
56 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16
57 #define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC
60 #define TEGRA_APBDMA_CHAN_STATUS 0x004
61 #define TEGRA_APBDMA_STATUS_BUSY BIT(31)
62 #define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)
63 #define TEGRA_APBDMA_STATUS_HALT BIT(29)
64 #define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)
65 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2
66 #define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
68 #define TEGRA_APBDMA_CHAN_CSRE 0x00C
69 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)
71 /* AHB memory address */
72 #define TEGRA_APBDMA_CHAN_AHBPTR 0x010
74 /* AHB sequence register */
75 #define TEGRA_APBDMA_CHAN_AHBSEQ 0x14
76 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)
77 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)
78 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)
79 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)
80 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)
81 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
82 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)
83 #define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)
84 #define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)
85 #define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)
86 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)
87 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16
88 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0
91 #define TEGRA_APBDMA_CHAN_APBPTR 0x018
93 /* APB sequence register */
94 #define TEGRA_APBDMA_CHAN_APBSEQ 0x01c
95 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28)
96 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
97 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
98 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28)
99 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
100 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27)
101 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16)
104 * If any burst is in flight and DMA paused then this is the time to complete
105 * on-flight burst and update DMA status register.
107 #define TEGRA_APBDMA_BURST_COMPLETE_TIME 20
109 /* Channel base address offset from APBDMA base address */
110 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
112 /* DMA channel register space size */
113 #define TEGRA_APBDMA_CHANNEL_REGISTER_SIZE 0x20
118 * tegra_dma_chip_data Tegra chip specific DMA data
119 * @nr_channels: Number of channels available in the controller.
120 * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
121 * @support_channel_pause: Support channel wise pause of dma.
123 struct tegra_dma_chip_data {
126 bool support_channel_pause;
129 /* DMA channel registers */
130 struct tegra_dma_channel_regs {
132 unsigned long ahb_ptr;
133 unsigned long apb_ptr;
134 unsigned long ahb_seq;
135 unsigned long apb_seq;
139 * tegra_dma_sg_req: Dma request details to configure hardware. This
140 * contains the details for one transfer to configure DMA hw.
141 * The client's request for data transfer can be broken into multiple
142 * sub-transfer as per requester details and hw support.
143 * This sub transfer get added in the list of transfer and point to Tegra
144 * DMA descriptor which manages the transfer details.
146 struct tegra_dma_sg_req {
147 struct tegra_dma_channel_regs ch_regs;
152 struct list_head node;
153 struct tegra_dma_desc *dma_desc;
157 * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
158 * This descriptor keep track of transfer status, callbacks and request
161 struct tegra_dma_desc {
162 struct dma_async_tx_descriptor txd;
164 int bytes_transferred;
165 enum dma_status dma_status;
166 struct list_head node;
167 struct list_head tx_list;
168 struct list_head cb_node;
172 struct tegra_dma_channel;
174 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
177 /* tegra_dma_channel: Channel specific information */
178 struct tegra_dma_channel {
179 struct dma_chan dma_chan;
184 unsigned long chan_base_offset;
187 struct tegra_dma *tdma;
190 /* Different lists for managing the requests */
191 struct list_head free_sg_req;
192 struct list_head pending_sg_req;
193 struct list_head free_dma_desc;
194 struct list_head cb_desc;
196 /* ISR handler and tasklet for bottom half of isr handling */
197 dma_isr_handler isr_handler;
198 struct tasklet_struct tasklet;
199 dma_async_tx_callback callback;
200 void *callback_param;
202 /* Channel-slave specific configuration */
203 unsigned int slave_id;
204 struct dma_slave_config dma_sconfig;
205 struct tegra_dma_channel_regs channel_reg;
208 /* tegra_dma: Tegra DMA specific information */
210 struct dma_device dma_dev;
213 struct reset_control *rst;
214 spinlock_t global_lock;
215 void __iomem *base_addr;
216 const struct tegra_dma_chip_data *chip_data;
218 /* Some register need to be cache before suspend */
221 /* Last member of the structure */
222 struct tegra_dma_channel channels[0];
225 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
227 writel(val, tdma->base_addr + reg);
230 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
232 return readl(tdma->base_addr + reg);
235 static inline void tdc_write(struct tegra_dma_channel *tdc,
238 writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
241 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
243 return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
246 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
248 return container_of(dc, struct tegra_dma_channel, dma_chan);
251 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
252 struct dma_async_tx_descriptor *td)
254 return container_of(td, struct tegra_dma_desc, txd);
257 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
259 return &tdc->dma_chan.dev->device;
262 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
263 static int tegra_dma_runtime_suspend(struct device *dev);
264 static int tegra_dma_runtime_resume(struct device *dev);
266 /* Get DMA desc from free list, if not there then allocate it. */
267 static struct tegra_dma_desc *tegra_dma_desc_get(
268 struct tegra_dma_channel *tdc)
270 struct tegra_dma_desc *dma_desc;
273 spin_lock_irqsave(&tdc->lock, flags);
275 /* Do not allocate if desc are waiting for ack */
276 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
277 if (async_tx_test_ack(&dma_desc->txd)) {
278 list_del(&dma_desc->node);
279 spin_unlock_irqrestore(&tdc->lock, flags);
280 dma_desc->txd.flags = 0;
285 spin_unlock_irqrestore(&tdc->lock, flags);
287 /* Allocate DMA desc */
288 dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
290 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
294 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
295 dma_desc->txd.tx_submit = tegra_dma_tx_submit;
296 dma_desc->txd.flags = 0;
300 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
301 struct tegra_dma_desc *dma_desc)
305 spin_lock_irqsave(&tdc->lock, flags);
306 if (!list_empty(&dma_desc->tx_list))
307 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
308 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
309 spin_unlock_irqrestore(&tdc->lock, flags);
312 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
313 struct tegra_dma_channel *tdc)
315 struct tegra_dma_sg_req *sg_req = NULL;
318 spin_lock_irqsave(&tdc->lock, flags);
319 if (!list_empty(&tdc->free_sg_req)) {
320 sg_req = list_first_entry(&tdc->free_sg_req,
321 typeof(*sg_req), node);
322 list_del(&sg_req->node);
323 spin_unlock_irqrestore(&tdc->lock, flags);
326 spin_unlock_irqrestore(&tdc->lock, flags);
328 sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
330 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
334 static int tegra_dma_slave_config(struct dma_chan *dc,
335 struct dma_slave_config *sconfig)
337 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
339 if (!list_empty(&tdc->pending_sg_req)) {
340 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
344 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
346 tdc->slave_id = sconfig->slave_id;
347 tdc->config_init = true;
351 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
352 bool wait_for_burst_complete)
354 struct tegra_dma *tdma = tdc->tdma;
356 spin_lock(&tdma->global_lock);
357 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
358 if (wait_for_burst_complete)
359 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
362 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
364 struct tegra_dma *tdma = tdc->tdma;
366 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
367 spin_unlock(&tdma->global_lock);
370 static void tegra_dma_pause(struct tegra_dma_channel *tdc,
371 bool wait_for_burst_complete)
373 struct tegra_dma *tdma = tdc->tdma;
375 if (tdma->chip_data->support_channel_pause) {
376 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
377 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
378 if (wait_for_burst_complete)
379 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
381 tegra_dma_global_pause(tdc, wait_for_burst_complete);
385 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
387 struct tegra_dma *tdma = tdc->tdma;
389 if (tdma->chip_data->support_channel_pause) {
390 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
392 tegra_dma_global_resume(tdc);
396 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
401 /* Disable interrupts */
402 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
403 csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
404 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
407 csr &= ~TEGRA_APBDMA_CSR_ENB;
408 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
410 /* Clear interrupt status if it is there */
411 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
412 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
413 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
414 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
419 static void tegra_dma_start(struct tegra_dma_channel *tdc,
420 struct tegra_dma_sg_req *sg_req)
422 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
424 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
425 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
426 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
427 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
428 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
431 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
432 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
435 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
436 struct tegra_dma_sg_req *nsg_req)
438 unsigned long status;
441 * The DMA controller reloads the new configuration for next transfer
442 * after last burst of current transfer completes.
443 * If there is no IEC status then this makes sure that last burst
444 * has not be completed. There may be case that last burst is on
445 * flight and so it can complete but because DMA is paused, it
446 * will not generates interrupt as well as not reload the new
448 * If there is already IEC status then interrupt handler need to
449 * load new configuration.
451 tegra_dma_pause(tdc, false);
452 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
455 * If interrupt is pending then do nothing as the ISR will handle
456 * the programing for new request.
458 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
459 dev_err(tdc2dev(tdc),
460 "Skipping new configuration as interrupt is pending\n");
461 tegra_dma_resume(tdc);
465 /* Safe to program new configuration */
466 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
467 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
468 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
469 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
470 nsg_req->configured = true;
472 tegra_dma_resume(tdc);
475 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
477 struct tegra_dma_sg_req *sg_req;
479 if (list_empty(&tdc->pending_sg_req))
482 sg_req = list_first_entry(&tdc->pending_sg_req,
483 typeof(*sg_req), node);
484 tegra_dma_start(tdc, sg_req);
485 sg_req->configured = true;
489 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
491 struct tegra_dma_sg_req *hsgreq;
492 struct tegra_dma_sg_req *hnsgreq;
494 if (list_empty(&tdc->pending_sg_req))
497 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
498 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
499 hnsgreq = list_first_entry(&hsgreq->node,
500 typeof(*hnsgreq), node);
501 tegra_dma_configure_for_next(tdc, hnsgreq);
505 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
506 struct tegra_dma_sg_req *sg_req, unsigned long status)
508 return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
511 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
513 struct tegra_dma_sg_req *sgreq;
514 struct tegra_dma_desc *dma_desc;
516 while (!list_empty(&tdc->pending_sg_req)) {
517 sgreq = list_first_entry(&tdc->pending_sg_req,
518 typeof(*sgreq), node);
519 list_move_tail(&sgreq->node, &tdc->free_sg_req);
520 if (sgreq->last_sg) {
521 dma_desc = sgreq->dma_desc;
522 dma_desc->dma_status = DMA_ERROR;
523 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
525 /* Add in cb list if it is not there. */
526 if (!dma_desc->cb_count)
527 list_add_tail(&dma_desc->cb_node,
529 dma_desc->cb_count++;
532 tdc->isr_handler = NULL;
535 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
536 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
538 struct tegra_dma_sg_req *hsgreq = NULL;
540 if (list_empty(&tdc->pending_sg_req)) {
541 dev_err(tdc2dev(tdc), "Dma is running without req\n");
547 * Check that head req on list should be in flight.
548 * If it is not in flight then abort transfer as
549 * looping of transfer can not continue.
551 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
552 if (!hsgreq->configured) {
554 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
555 tegra_dma_abort_all(tdc);
559 /* Configure next request */
561 tdc_configure_next_head_desc(tdc);
565 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
568 struct tegra_dma_sg_req *sgreq;
569 struct tegra_dma_desc *dma_desc;
572 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
573 dma_desc = sgreq->dma_desc;
574 dma_desc->bytes_transferred += sgreq->req_len;
576 list_del(&sgreq->node);
577 if (sgreq->last_sg) {
578 dma_desc->dma_status = DMA_COMPLETE;
579 dma_cookie_complete(&dma_desc->txd);
580 if (!dma_desc->cb_count)
581 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
582 dma_desc->cb_count++;
583 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
585 list_add_tail(&sgreq->node, &tdc->free_sg_req);
587 /* Do not start DMA if it is going to be terminate */
588 if (to_terminate || list_empty(&tdc->pending_sg_req))
591 tdc_start_head_req(tdc);
595 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
598 struct tegra_dma_sg_req *sgreq;
599 struct tegra_dma_desc *dma_desc;
602 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
603 dma_desc = sgreq->dma_desc;
604 dma_desc->bytes_transferred += sgreq->req_len;
606 /* Callback need to be call */
607 if (!dma_desc->cb_count)
608 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
609 dma_desc->cb_count++;
611 /* If not last req then put at end of pending list */
612 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
613 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
614 sgreq->configured = false;
615 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
617 dma_desc->dma_status = DMA_ERROR;
622 static void tegra_dma_tasklet(unsigned long data)
624 struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
625 dma_async_tx_callback callback = NULL;
626 void *callback_param = NULL;
627 struct tegra_dma_desc *dma_desc;
631 spin_lock_irqsave(&tdc->lock, flags);
632 while (!list_empty(&tdc->cb_desc)) {
633 dma_desc = list_first_entry(&tdc->cb_desc,
634 typeof(*dma_desc), cb_node);
635 list_del(&dma_desc->cb_node);
636 callback = dma_desc->txd.callback;
637 callback_param = dma_desc->txd.callback_param;
638 cb_count = dma_desc->cb_count;
639 dma_desc->cb_count = 0;
640 spin_unlock_irqrestore(&tdc->lock, flags);
641 while (cb_count-- && callback)
642 callback(callback_param);
643 spin_lock_irqsave(&tdc->lock, flags);
645 spin_unlock_irqrestore(&tdc->lock, flags);
648 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
650 struct tegra_dma_channel *tdc = dev_id;
651 unsigned long status;
654 spin_lock_irqsave(&tdc->lock, flags);
656 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
657 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
658 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
659 tdc->isr_handler(tdc, false);
660 tasklet_schedule(&tdc->tasklet);
661 spin_unlock_irqrestore(&tdc->lock, flags);
665 spin_unlock_irqrestore(&tdc->lock, flags);
666 dev_info(tdc2dev(tdc),
667 "Interrupt already served status 0x%08lx\n", status);
671 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
673 struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
674 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
678 spin_lock_irqsave(&tdc->lock, flags);
679 dma_desc->dma_status = DMA_IN_PROGRESS;
680 cookie = dma_cookie_assign(&dma_desc->txd);
681 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
682 spin_unlock_irqrestore(&tdc->lock, flags);
686 static void tegra_dma_issue_pending(struct dma_chan *dc)
688 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
691 spin_lock_irqsave(&tdc->lock, flags);
692 if (list_empty(&tdc->pending_sg_req)) {
693 dev_err(tdc2dev(tdc), "No DMA request\n");
697 tdc_start_head_req(tdc);
699 /* Continuous single mode: Configure next req */
702 * Wait for 1 burst time for configure DMA for
705 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
706 tdc_configure_next_head_desc(tdc);
710 spin_unlock_irqrestore(&tdc->lock, flags);
714 static void tegra_dma_terminate_all(struct dma_chan *dc)
716 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
717 struct tegra_dma_sg_req *sgreq;
718 struct tegra_dma_desc *dma_desc;
720 unsigned long status;
723 spin_lock_irqsave(&tdc->lock, flags);
724 if (list_empty(&tdc->pending_sg_req)) {
725 spin_unlock_irqrestore(&tdc->lock, flags);
732 /* Pause DMA before checking the queue status */
733 tegra_dma_pause(tdc, true);
735 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
736 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
737 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
738 tdc->isr_handler(tdc, true);
739 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
742 was_busy = tdc->busy;
745 if (!list_empty(&tdc->pending_sg_req) && was_busy) {
746 sgreq = list_first_entry(&tdc->pending_sg_req,
747 typeof(*sgreq), node);
748 sgreq->dma_desc->bytes_transferred +=
749 get_current_xferred_count(tdc, sgreq, status);
751 tegra_dma_resume(tdc);
754 tegra_dma_abort_all(tdc);
756 while (!list_empty(&tdc->cb_desc)) {
757 dma_desc = list_first_entry(&tdc->cb_desc,
758 typeof(*dma_desc), cb_node);
759 list_del(&dma_desc->cb_node);
760 dma_desc->cb_count = 0;
762 spin_unlock_irqrestore(&tdc->lock, flags);
765 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
766 dma_cookie_t cookie, struct dma_tx_state *txstate)
768 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
769 struct tegra_dma_desc *dma_desc;
770 struct tegra_dma_sg_req *sg_req;
773 unsigned int residual;
775 ret = dma_cookie_status(dc, cookie, txstate);
776 if (ret == DMA_COMPLETE)
779 spin_lock_irqsave(&tdc->lock, flags);
781 /* Check on wait_ack desc status */
782 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
783 if (dma_desc->txd.cookie == cookie) {
784 residual = dma_desc->bytes_requested -
785 (dma_desc->bytes_transferred %
786 dma_desc->bytes_requested);
787 dma_set_residue(txstate, residual);
788 ret = dma_desc->dma_status;
789 spin_unlock_irqrestore(&tdc->lock, flags);
794 /* Check in pending list */
795 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
796 dma_desc = sg_req->dma_desc;
797 if (dma_desc->txd.cookie == cookie) {
798 residual = dma_desc->bytes_requested -
799 (dma_desc->bytes_transferred %
800 dma_desc->bytes_requested);
801 dma_set_residue(txstate, residual);
802 ret = dma_desc->dma_status;
803 spin_unlock_irqrestore(&tdc->lock, flags);
808 dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
809 spin_unlock_irqrestore(&tdc->lock, flags);
813 static int tegra_dma_device_control(struct dma_chan *dc, enum dma_ctrl_cmd cmd,
817 case DMA_SLAVE_CONFIG:
818 return tegra_dma_slave_config(dc,
819 (struct dma_slave_config *)arg);
821 case DMA_TERMINATE_ALL:
822 tegra_dma_terminate_all(dc);
832 static inline int get_bus_width(struct tegra_dma_channel *tdc,
833 enum dma_slave_buswidth slave_bw)
836 case DMA_SLAVE_BUSWIDTH_1_BYTE:
837 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
838 case DMA_SLAVE_BUSWIDTH_2_BYTES:
839 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
840 case DMA_SLAVE_BUSWIDTH_4_BYTES:
841 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
842 case DMA_SLAVE_BUSWIDTH_8_BYTES:
843 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
845 dev_warn(tdc2dev(tdc),
846 "slave bw is not supported, using 32bits\n");
847 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
851 static inline int get_burst_size(struct tegra_dma_channel *tdc,
852 u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
858 * burst_size from client is in terms of the bus_width.
859 * convert them into AHB memory width which is 4 byte.
861 burst_byte = burst_size * slave_bw;
862 burst_ahb_width = burst_byte / 4;
864 /* If burst size is 0 then calculate the burst size based on length */
865 if (!burst_ahb_width) {
867 return TEGRA_APBDMA_AHBSEQ_BURST_1;
868 else if ((len >> 4) & 0x1)
869 return TEGRA_APBDMA_AHBSEQ_BURST_4;
871 return TEGRA_APBDMA_AHBSEQ_BURST_8;
873 if (burst_ahb_width < 4)
874 return TEGRA_APBDMA_AHBSEQ_BURST_1;
875 else if (burst_ahb_width < 8)
876 return TEGRA_APBDMA_AHBSEQ_BURST_4;
878 return TEGRA_APBDMA_AHBSEQ_BURST_8;
881 static int get_transfer_param(struct tegra_dma_channel *tdc,
882 enum dma_transfer_direction direction, unsigned long *apb_addr,
883 unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
884 enum dma_slave_buswidth *slave_bw)
889 *apb_addr = tdc->dma_sconfig.dst_addr;
890 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
891 *burst_size = tdc->dma_sconfig.dst_maxburst;
892 *slave_bw = tdc->dma_sconfig.dst_addr_width;
893 *csr = TEGRA_APBDMA_CSR_DIR;
897 *apb_addr = tdc->dma_sconfig.src_addr;
898 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
899 *burst_size = tdc->dma_sconfig.src_maxburst;
900 *slave_bw = tdc->dma_sconfig.src_addr_width;
905 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
911 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
912 struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
913 enum dma_transfer_direction direction, unsigned long flags,
916 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
917 struct tegra_dma_desc *dma_desc;
919 struct scatterlist *sg;
920 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
921 struct list_head req_list;
922 struct tegra_dma_sg_req *sg_req = NULL;
924 enum dma_slave_buswidth slave_bw;
927 if (!tdc->config_init) {
928 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
932 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
936 ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
937 &burst_size, &slave_bw);
941 INIT_LIST_HEAD(&req_list);
943 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
944 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
945 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
946 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
948 csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
949 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
950 if (flags & DMA_PREP_INTERRUPT)
951 csr |= TEGRA_APBDMA_CSR_IE_EOC;
953 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
955 dma_desc = tegra_dma_desc_get(tdc);
957 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
960 INIT_LIST_HEAD(&dma_desc->tx_list);
961 INIT_LIST_HEAD(&dma_desc->cb_node);
962 dma_desc->cb_count = 0;
963 dma_desc->bytes_requested = 0;
964 dma_desc->bytes_transferred = 0;
965 dma_desc->dma_status = DMA_IN_PROGRESS;
967 /* Make transfer requests */
968 for_each_sg(sgl, sg, sg_len, i) {
971 mem = sg_dma_address(sg);
972 len = sg_dma_len(sg);
974 if ((len & 3) || (mem & 3) ||
975 (len > tdc->tdma->chip_data->max_dma_count)) {
976 dev_err(tdc2dev(tdc),
977 "Dma length/memory address is not supported\n");
978 tegra_dma_desc_put(tdc, dma_desc);
982 sg_req = tegra_dma_sg_req_get(tdc);
984 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
985 tegra_dma_desc_put(tdc, dma_desc);
989 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
990 dma_desc->bytes_requested += len;
992 sg_req->ch_regs.apb_ptr = apb_ptr;
993 sg_req->ch_regs.ahb_ptr = mem;
994 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
995 sg_req->ch_regs.apb_seq = apb_seq;
996 sg_req->ch_regs.ahb_seq = ahb_seq;
997 sg_req->configured = false;
998 sg_req->last_sg = false;
999 sg_req->dma_desc = dma_desc;
1000 sg_req->req_len = len;
1002 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1004 sg_req->last_sg = true;
1005 if (flags & DMA_CTRL_ACK)
1006 dma_desc->txd.flags = DMA_CTRL_ACK;
1009 * Make sure that mode should not be conflicting with currently
1012 if (!tdc->isr_handler) {
1013 tdc->isr_handler = handle_once_dma_done;
1014 tdc->cyclic = false;
1017 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1018 tegra_dma_desc_put(tdc, dma_desc);
1023 return &dma_desc->txd;
1026 static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1027 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1028 size_t period_len, enum dma_transfer_direction direction,
1029 unsigned long flags, void *context)
1031 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1032 struct tegra_dma_desc *dma_desc = NULL;
1033 struct tegra_dma_sg_req *sg_req = NULL;
1034 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1037 dma_addr_t mem = buf_addr;
1039 enum dma_slave_buswidth slave_bw;
1042 if (!buf_len || !period_len) {
1043 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1047 if (!tdc->config_init) {
1048 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1053 * We allow to take more number of requests till DMA is
1054 * not started. The driver will loop over all requests.
1055 * Once DMA is started then new requests can be queued only after
1056 * terminating the DMA.
1059 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1064 * We only support cycle transfer when buf_len is multiple of
1067 if (buf_len % period_len) {
1068 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1073 if ((len & 3) || (buf_addr & 3) ||
1074 (len > tdc->tdma->chip_data->max_dma_count)) {
1075 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1079 ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1080 &burst_size, &slave_bw);
1085 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1086 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1087 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1088 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1090 csr |= TEGRA_APBDMA_CSR_FLOW;
1091 if (flags & DMA_PREP_INTERRUPT)
1092 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1093 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1095 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1097 dma_desc = tegra_dma_desc_get(tdc);
1099 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1103 INIT_LIST_HEAD(&dma_desc->tx_list);
1104 INIT_LIST_HEAD(&dma_desc->cb_node);
1105 dma_desc->cb_count = 0;
1107 dma_desc->bytes_transferred = 0;
1108 dma_desc->bytes_requested = buf_len;
1109 remain_len = buf_len;
1111 /* Split transfer equal to period size */
1112 while (remain_len) {
1113 sg_req = tegra_dma_sg_req_get(tdc);
1115 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1116 tegra_dma_desc_put(tdc, dma_desc);
1120 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1121 sg_req->ch_regs.apb_ptr = apb_ptr;
1122 sg_req->ch_regs.ahb_ptr = mem;
1123 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
1124 sg_req->ch_regs.apb_seq = apb_seq;
1125 sg_req->ch_regs.ahb_seq = ahb_seq;
1126 sg_req->configured = false;
1127 sg_req->half_done = false;
1128 sg_req->last_sg = false;
1129 sg_req->dma_desc = dma_desc;
1130 sg_req->req_len = len;
1132 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1136 sg_req->last_sg = true;
1137 if (flags & DMA_CTRL_ACK)
1138 dma_desc->txd.flags = DMA_CTRL_ACK;
1141 * Make sure that mode should not be conflicting with currently
1144 if (!tdc->isr_handler) {
1145 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1149 dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1150 tegra_dma_desc_put(tdc, dma_desc);
1155 return &dma_desc->txd;
1158 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1160 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1161 struct tegra_dma *tdma = tdc->tdma;
1164 dma_cookie_init(&tdc->dma_chan);
1165 tdc->config_init = false;
1166 ret = clk_prepare_enable(tdma->dma_clk);
1168 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1172 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1174 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1175 struct tegra_dma *tdma = tdc->tdma;
1177 struct tegra_dma_desc *dma_desc;
1178 struct tegra_dma_sg_req *sg_req;
1179 struct list_head dma_desc_list;
1180 struct list_head sg_req_list;
1181 unsigned long flags;
1183 INIT_LIST_HEAD(&dma_desc_list);
1184 INIT_LIST_HEAD(&sg_req_list);
1186 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1189 tegra_dma_terminate_all(dc);
1191 spin_lock_irqsave(&tdc->lock, flags);
1192 list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1193 list_splice_init(&tdc->free_sg_req, &sg_req_list);
1194 list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1195 INIT_LIST_HEAD(&tdc->cb_desc);
1196 tdc->config_init = false;
1197 tdc->isr_handler = NULL;
1198 spin_unlock_irqrestore(&tdc->lock, flags);
1200 while (!list_empty(&dma_desc_list)) {
1201 dma_desc = list_first_entry(&dma_desc_list,
1202 typeof(*dma_desc), node);
1203 list_del(&dma_desc->node);
1207 while (!list_empty(&sg_req_list)) {
1208 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1209 list_del(&sg_req->node);
1212 clk_disable_unprepare(tdma->dma_clk);
1217 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
1218 struct of_dma *ofdma)
1220 struct tegra_dma *tdma = ofdma->of_dma_data;
1221 struct dma_chan *chan;
1222 struct tegra_dma_channel *tdc;
1224 chan = dma_get_any_slave_channel(&tdma->dma_dev);
1228 tdc = to_tegra_dma_chan(chan);
1229 tdc->slave_id = dma_spec->args[0];
1234 /* Tegra20 specific DMA controller information */
1235 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1237 .max_dma_count = 1024UL * 64,
1238 .support_channel_pause = false,
1241 /* Tegra30 specific DMA controller information */
1242 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1244 .max_dma_count = 1024UL * 64,
1245 .support_channel_pause = false,
1248 /* Tegra114 specific DMA controller information */
1249 static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1251 .max_dma_count = 1024UL * 64,
1252 .support_channel_pause = true,
1256 static const struct of_device_id tegra_dma_of_match[] = {
1258 .compatible = "nvidia,tegra114-apbdma",
1259 .data = &tegra114_dma_chip_data,
1261 .compatible = "nvidia,tegra30-apbdma",
1262 .data = &tegra30_dma_chip_data,
1264 .compatible = "nvidia,tegra20-apbdma",
1265 .data = &tegra20_dma_chip_data,
1269 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1271 static int tegra_dma_probe(struct platform_device *pdev)
1273 struct resource *res;
1274 struct tegra_dma *tdma;
1277 const struct tegra_dma_chip_data *cdata = NULL;
1278 const struct of_device_id *match;
1280 match = of_match_device(tegra_dma_of_match, &pdev->dev);
1282 dev_err(&pdev->dev, "Error: No device match found\n");
1285 cdata = match->data;
1287 tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1288 sizeof(struct tegra_dma_channel), GFP_KERNEL);
1290 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1294 tdma->dev = &pdev->dev;
1295 tdma->chip_data = cdata;
1296 platform_set_drvdata(pdev, tdma);
1298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1299 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1300 if (IS_ERR(tdma->base_addr))
1301 return PTR_ERR(tdma->base_addr);
1303 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1304 if (IS_ERR(tdma->dma_clk)) {
1305 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1306 return PTR_ERR(tdma->dma_clk);
1309 tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1310 if (IS_ERR(tdma->rst)) {
1311 dev_err(&pdev->dev, "Error: Missing reset\n");
1312 return PTR_ERR(tdma->rst);
1315 spin_lock_init(&tdma->global_lock);
1317 pm_runtime_enable(&pdev->dev);
1318 if (!pm_runtime_enabled(&pdev->dev)) {
1319 ret = tegra_dma_runtime_resume(&pdev->dev);
1321 dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
1323 goto err_pm_disable;
1327 /* Enable clock before accessing registers */
1328 ret = clk_prepare_enable(tdma->dma_clk);
1330 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1331 goto err_pm_disable;
1334 /* Reset DMA controller */
1335 reset_control_assert(tdma->rst);
1337 reset_control_deassert(tdma->rst);
1339 /* Enable global DMA registers */
1340 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1341 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1342 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1344 clk_disable_unprepare(tdma->dma_clk);
1346 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1347 for (i = 0; i < cdata->nr_channels; i++) {
1348 struct tegra_dma_channel *tdc = &tdma->channels[i];
1350 tdc->chan_base_offset = TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1351 i * TEGRA_APBDMA_CHANNEL_REGISTER_SIZE;
1353 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1356 dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1359 tdc->irq = res->start;
1360 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1361 ret = devm_request_irq(&pdev->dev, tdc->irq,
1362 tegra_dma_isr, 0, tdc->name, tdc);
1365 "request_irq failed with err %d channel %d\n",
1370 tdc->dma_chan.device = &tdma->dma_dev;
1371 dma_cookie_init(&tdc->dma_chan);
1372 list_add_tail(&tdc->dma_chan.device_node,
1373 &tdma->dma_dev.channels);
1377 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1378 (unsigned long)tdc);
1379 spin_lock_init(&tdc->lock);
1381 INIT_LIST_HEAD(&tdc->pending_sg_req);
1382 INIT_LIST_HEAD(&tdc->free_sg_req);
1383 INIT_LIST_HEAD(&tdc->free_dma_desc);
1384 INIT_LIST_HEAD(&tdc->cb_desc);
1387 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1388 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1389 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1391 tdma->dma_dev.dev = &pdev->dev;
1392 tdma->dma_dev.device_alloc_chan_resources =
1393 tegra_dma_alloc_chan_resources;
1394 tdma->dma_dev.device_free_chan_resources =
1395 tegra_dma_free_chan_resources;
1396 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1397 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1398 tdma->dma_dev.device_control = tegra_dma_device_control;
1399 tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1400 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1402 ret = dma_async_device_register(&tdma->dma_dev);
1405 "Tegra20 APB DMA driver registration failed %d\n", ret);
1409 ret = of_dma_controller_register(pdev->dev.of_node,
1410 tegra_dma_of_xlate, tdma);
1413 "Tegra20 APB DMA OF registration failed %d\n", ret);
1414 goto err_unregister_dma_dev;
1417 dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1418 cdata->nr_channels);
1421 err_unregister_dma_dev:
1422 dma_async_device_unregister(&tdma->dma_dev);
1425 struct tegra_dma_channel *tdc = &tdma->channels[i];
1426 tasklet_kill(&tdc->tasklet);
1430 pm_runtime_disable(&pdev->dev);
1431 if (!pm_runtime_status_suspended(&pdev->dev))
1432 tegra_dma_runtime_suspend(&pdev->dev);
1436 static int tegra_dma_remove(struct platform_device *pdev)
1438 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1440 struct tegra_dma_channel *tdc;
1442 dma_async_device_unregister(&tdma->dma_dev);
1444 for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1445 tdc = &tdma->channels[i];
1446 tasklet_kill(&tdc->tasklet);
1449 pm_runtime_disable(&pdev->dev);
1450 if (!pm_runtime_status_suspended(&pdev->dev))
1451 tegra_dma_runtime_suspend(&pdev->dev);
1456 static int tegra_dma_runtime_suspend(struct device *dev)
1458 struct platform_device *pdev = to_platform_device(dev);
1459 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1461 clk_disable_unprepare(tdma->dma_clk);
1465 static int tegra_dma_runtime_resume(struct device *dev)
1467 struct platform_device *pdev = to_platform_device(dev);
1468 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1471 ret = clk_prepare_enable(tdma->dma_clk);
1473 dev_err(dev, "clk_enable failed: %d\n", ret);
1479 #ifdef CONFIG_PM_SLEEP
1480 static int tegra_dma_pm_suspend(struct device *dev)
1482 struct tegra_dma *tdma = dev_get_drvdata(dev);
1486 /* Enable clock before accessing register */
1487 ret = tegra_dma_runtime_resume(dev);
1491 tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1492 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1493 struct tegra_dma_channel *tdc = &tdma->channels[i];
1494 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1496 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1497 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1498 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1499 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1500 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1504 tegra_dma_runtime_suspend(dev);
1508 static int tegra_dma_pm_resume(struct device *dev)
1510 struct tegra_dma *tdma = dev_get_drvdata(dev);
1514 /* Enable clock before accessing register */
1515 ret = tegra_dma_runtime_resume(dev);
1519 tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1520 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1521 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1523 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1524 struct tegra_dma_channel *tdc = &tdma->channels[i];
1525 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1527 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1528 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1529 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1530 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1531 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1532 (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1536 tegra_dma_runtime_suspend(dev);
1541 static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
1542 #ifdef CONFIG_PM_RUNTIME
1543 .runtime_suspend = tegra_dma_runtime_suspend,
1544 .runtime_resume = tegra_dma_runtime_resume,
1546 SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
1549 static struct platform_driver tegra_dmac_driver = {
1551 .name = "tegra-apbdma",
1552 .owner = THIS_MODULE,
1553 .pm = &tegra_dma_dev_pm_ops,
1554 .of_match_table = tegra_dma_of_match,
1556 .probe = tegra_dma_probe,
1557 .remove = tegra_dma_remove,
1560 module_platform_driver(tegra_dmac_driver);
1562 MODULE_ALIAS("platform:tegra20-apbdma");
1563 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1564 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1565 MODULE_LICENSE("GPL v2");