3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
8 bool "EDAC (Error Detection And Correction) reporting"
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
14 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
18 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
21 <http://bluesmoke.sourceforge.net/>
25 <http://buttersideup.com/edacwiki>
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
32 comment "Reporting subsystems"
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
42 config EDAC_DEBUG_VERBOSE
43 bool "More verbose debugging"
46 This option makes debugging information more verbose.
47 Source file name and line number where debugging message
48 printed will be added to debugging message.
51 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
53 Some systems are able to detect and correct errors in main
54 memory. EDAC can report statistics on memory error
55 detection and correction (EDAC - or commonly referred to ECC
56 errors). EDAC will also try to decode where these errors
57 occurred so that a particular failing memory module can be
58 replaced. If unsure, select 'Y'.
61 tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
62 depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && CPU_SUP_AMD
64 Support for error detection and correction on the AMD 64
65 Families of Memory Controllers (K8, F10h and F11h)
67 config EDAC_AMD64_ERROR_INJECTION
68 bool "Sysfs Error Injection facilities"
71 Recent Opterons (Family 10h and later) provide for Memory Error
72 Injection into the ECC detection circuits. The amd64_edac module
73 allows the operator/user to inject Uncorrectable and Correctable
76 When enabled, in each of the respective memory controller directories
77 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
79 - inject_section (0..3, 16-byte section of 64-byte cacheline),
80 - inject_word (0..8, 16-bit word of 16-byte section),
81 - inject_ecc_vector (hex ecc vector: select bits of inject word)
83 In addition, there are two control files, inject_read and inject_write,
84 which trigger the DRAM ECC Read and Write respectively.
87 tristate "AMD 76x (760, 762, 768)"
88 depends on EDAC_MM_EDAC && PCI && X86_32
90 Support for error detection and correction on the AMD 76x
91 series of chipsets used with the Athlon processor.
94 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
95 depends on EDAC_MM_EDAC && PCI && X86_32
97 Support for error detection and correction on the Intel
98 E7205, E7500, E7501 and E7505 server chipsets.
101 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
102 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
104 Support for error detection and correction on the Intel
105 E7520, E7525, E7320 server chipsets.
107 config EDAC_I82443BXGX
108 tristate "Intel 82443BX/GX (440BX/GX)"
109 depends on EDAC_MM_EDAC && PCI && X86_32
112 Support for error detection and correction on the Intel
113 82443BX/GX memory controllers (440BX/GX chipsets).
116 tristate "Intel 82875p (D82875P, E7210)"
117 depends on EDAC_MM_EDAC && PCI && X86_32
119 Support for error detection and correction on the Intel
120 DP82785P and E7210 server chipsets.
123 tristate "Intel 82975x (D82975x)"
124 depends on EDAC_MM_EDAC && PCI && X86
126 Support for error detection and correction on the Intel
127 DP82975x server chipsets.
130 tristate "Intel 3000/3010"
131 depends on EDAC_MM_EDAC && PCI && X86
133 Support for error detection and correction on the Intel
134 3000 and 3010 server chipsets.
137 tristate "Intel 3200"
138 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
140 Support for error detection and correction on the Intel
141 3200 and 3210 server chipsets.
145 depends on EDAC_MM_EDAC && PCI && X86
147 Support for error detection and correction on the Intel
151 tristate "Intel 5400 (Seaburg) chipsets"
152 depends on EDAC_MM_EDAC && PCI && X86
154 Support for error detection and correction the Intel
155 i5400 MCH chipset (Seaburg).
158 tristate "Intel 82860"
159 depends on EDAC_MM_EDAC && PCI && X86_32
161 Support for error detection and correction on the Intel
165 tristate "Radisys 82600 embedded chipset"
166 depends on EDAC_MM_EDAC && PCI && X86_32
168 Support for error detection and correction on the Radisys
169 82600 embedded chipset.
172 tristate "Intel Greencreek/Blackford chipset"
173 depends on EDAC_MM_EDAC && X86 && PCI
175 Support for error detection and correction the Intel
176 Greekcreek/Blackford chipsets.
179 tristate "Intel San Clemente MCH"
180 depends on EDAC_MM_EDAC && X86 && PCI
182 Support for error detection and correction the Intel
186 tristate "Freescale MPC83xx / MPC85xx"
187 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || MPC85xx)
189 Support for error detection and correction on the Freescale
190 MPC8349, MPC8560, MPC8540, MPC8548
193 tristate "Marvell MV64x60"
194 depends on EDAC_MM_EDAC && MV64X60
196 Support for error detection and correction on the Marvell
197 MV64360 and MV64460 chipsets.
200 tristate "PA Semi PWRficient"
201 depends on EDAC_MM_EDAC && PCI
202 depends on PPC_PASEMI
204 Support for error detection and correction on PA Semi
208 tristate "Cell Broadband Engine memory controller"
209 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
211 Support for error detection and correction on the
212 Cell Broadband Engine internal memory controller
213 on platform without a hypervisor
216 tristate "PPC4xx IBM DDR2 Memory Controller"
217 depends on EDAC_MM_EDAC && 4xx
219 This enables support for EDAC on the ECC memory used
220 with the IBM DDR2 memory controller found in various
221 PowerPC 4xx embedded processors such as the 405EX[r],
222 440SP, 440SPe, 460EX, 460GT and 460SX.
225 tristate "AMD8131 HyperTransport PCI-X Tunnel"
226 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
228 Support for error detection and correction on the
229 AMD8131 HyperTransport PCI-X Tunnel chip.
230 Note, add more Kconfig dependency if it's adopted
231 on some machine other than Maple.
234 tristate "AMD8111 HyperTransport I/O Hub"
235 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
237 Support for error detection and correction on the
238 AMD8111 HyperTransport I/O Hub chip.
239 Note, add more Kconfig dependency if it's adopted
240 on some machine other than Maple.
243 tristate "IBM CPC925 Memory Controller (PPC970FX)"
244 depends on EDAC_MM_EDAC && PPC64
246 Support for error detection and correction on the
247 IBM CPC925 Bridge and Memory Controller, which is
248 a companion chip to the PowerPC 970 family of