3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
11 bool "EDAC (Error Detection And Correction) reporting"
13 depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
15 EDAC is designed to report errors in the core system.
16 These are low-level errors that are reported in the CPU or
17 supporting chipset or other subsystems:
18 memory errors, cache errors, PCI errors, thermal throttling, etc..
19 If unsure, select 'Y'.
21 If this code is reporting problems on your system, please
22 see the EDAC project web pages for more information at:
24 <http://bluesmoke.sourceforge.net/>
28 <http://buttersideup.com/edacwiki>
30 There is also a mailing list for the EDAC project, which can
31 be found via the sourceforge page.
35 config EDAC_LEGACY_SYSFS
36 bool "EDAC legacy sysfs"
39 Enable the compatibility sysfs nodes.
40 Use 'Y' if your edac utilities aren't ported to work with the newer
46 This turns on debugging information for the entire EDAC subsystem.
47 You do so by inserting edac_module with "edac_debug_level=x." Valid
48 levels are 0-4 (from low to high) and by default it is set to 2.
49 Usually you should select 'N' here.
51 config EDAC_DECODE_MCE
52 tristate "Decode MCEs in human-readable form (only on AMD for now)"
53 depends on CPU_SUP_AMD && X86_MCE_AMD
56 Enable this option if you want to decode Machine Check Exceptions
57 occurring on your machine in human-readable form.
59 You should definitely say Y here in case you want to decode MCEs
60 which occur really early upon boot, before the module infrastructure
64 tristate "Simple MCE injection interface over /sysfs"
65 depends on EDAC_DECODE_MCE
68 This is a simple interface to inject MCEs over /sysfs and test
69 the MCE decoding code in EDAC.
71 This is currently AMD-only.
74 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
76 Some systems are able to detect and correct errors in main
77 memory. EDAC can report statistics on memory error
78 detection and correction (EDAC - or commonly referred to ECC
79 errors). EDAC will also try to decode where these errors
80 occurred so that a particular failing memory module can be
81 replaced. If unsure, select 'Y'.
84 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
85 depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
88 Not all machines support hardware-driven error report. Some of those
89 provide a BIOS-driven error report mechanism via ACPI, using the
90 APEI/GHES driver. By enabling this option, the error reports provided
91 by GHES are sent to userspace via the EDAC API.
93 When this option is enabled, it will disable the hardware-driven
94 mechanisms, if a GHES BIOS is detected, entering into the
95 "Firmware First" mode.
97 It should be noticed that keeping both GHES and a hardware-driven
98 error mechanism won't work well, as BIOS will race with OS, while
99 reading the error registers. So, if you want to not use "Firmware
100 first" GHES error mechanism, you should disable GHES either at
101 compilation time or by passing "ghes.disable=1" Kernel parameter
107 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
108 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
110 Support for error detection and correction of DRAM ECC errors on
111 the AMD64 families of memory controllers (K8 and F10h)
113 config EDAC_AMD64_ERROR_INJECTION
114 bool "Sysfs HW Error injection facilities"
115 depends on EDAC_AMD64
117 Recent Opterons (Family 10h and later) provide for Memory Error
118 Injection into the ECC detection circuits. The amd64_edac module
119 allows the operator/user to inject Uncorrectable and Correctable
122 When enabled, in each of the respective memory controller directories
123 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
125 - inject_section (0..3, 16-byte section of 64-byte cacheline),
126 - inject_word (0..8, 16-bit word of 16-byte section),
127 - inject_ecc_vector (hex ecc vector: select bits of inject word)
129 In addition, there are two control files, inject_read and inject_write,
130 which trigger the DRAM ECC Read and Write respectively.
133 tristate "AMD 76x (760, 762, 768)"
134 depends on EDAC_MM_EDAC && PCI && X86_32
136 Support for error detection and correction on the AMD 76x
137 series of chipsets used with the Athlon processor.
140 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
141 depends on EDAC_MM_EDAC && PCI && X86_32
143 Support for error detection and correction on the Intel
144 E7205, E7500, E7501 and E7505 server chipsets.
147 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
148 depends on EDAC_MM_EDAC && PCI && X86
150 Support for error detection and correction on the Intel
151 E7520, E7525, E7320 server chipsets.
153 config EDAC_I82443BXGX
154 tristate "Intel 82443BX/GX (440BX/GX)"
155 depends on EDAC_MM_EDAC && PCI && X86_32
158 Support for error detection and correction on the Intel
159 82443BX/GX memory controllers (440BX/GX chipsets).
162 tristate "Intel 82875p (D82875P, E7210)"
163 depends on EDAC_MM_EDAC && PCI && X86_32
165 Support for error detection and correction on the Intel
166 DP82785P and E7210 server chipsets.
169 tristate "Intel 82975x (D82975x)"
170 depends on EDAC_MM_EDAC && PCI && X86
172 Support for error detection and correction on the Intel
173 DP82975x server chipsets.
176 tristate "Intel 3000/3010"
177 depends on EDAC_MM_EDAC && PCI && X86
179 Support for error detection and correction on the Intel
180 3000 and 3010 server chipsets.
183 tristate "Intel 3200"
184 depends on EDAC_MM_EDAC && PCI && X86
186 Support for error detection and correction on the Intel
187 3200 and 3210 server chipsets.
190 tristate "Intel e312xx"
191 depends on EDAC_MM_EDAC && PCI && X86
193 Support for error detection and correction on the Intel
194 E3-1200 based DRAM controllers.
198 depends on EDAC_MM_EDAC && PCI && X86
200 Support for error detection and correction on the Intel
204 tristate "Intel 5400 (Seaburg) chipsets"
205 depends on EDAC_MM_EDAC && PCI && X86
207 Support for error detection and correction the Intel
208 i5400 MCH chipset (Seaburg).
211 tristate "Intel i7 Core (Nehalem) processors"
212 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
214 Support for error detection and correction the Intel
215 i7 Core (Nehalem) Integrated Memory Controller that exists on
216 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
217 and Xeon 55xx processors.
220 tristate "Intel 82860"
221 depends on EDAC_MM_EDAC && PCI && X86_32
223 Support for error detection and correction on the Intel
227 tristate "Radisys 82600 embedded chipset"
228 depends on EDAC_MM_EDAC && PCI && X86_32
230 Support for error detection and correction on the Radisys
231 82600 embedded chipset.
234 tristate "Intel Greencreek/Blackford chipset"
235 depends on EDAC_MM_EDAC && X86 && PCI
237 Support for error detection and correction the Intel
238 Greekcreek/Blackford chipsets.
241 tristate "Intel San Clemente MCH"
242 depends on EDAC_MM_EDAC && X86 && PCI
244 Support for error detection and correction the Intel
248 tristate "Intel Clarksboro MCH"
249 depends on EDAC_MM_EDAC && X86 && PCI
251 Support for error detection and correction the Intel
252 Clarksboro MCH (Intel 7300 chipset).
255 tristate "Intel Sandy-Bridge Integrated MC"
256 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
257 depends on PCI_MMCONFIG
259 Support for error detection and correction the Intel
260 Sandy Bridge Integrated Memory Controller.
263 tristate "Freescale MPC83xx / MPC85xx"
264 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
266 Support for error detection and correction on the Freescale
267 MPC8349, MPC8560, MPC8540, MPC8548
270 tristate "Marvell MV64x60"
271 depends on EDAC_MM_EDAC && MV64X60
273 Support for error detection and correction on the Marvell
274 MV64360 and MV64460 chipsets.
277 tristate "PA Semi PWRficient"
278 depends on EDAC_MM_EDAC && PCI
279 depends on PPC_PASEMI
281 Support for error detection and correction on PA Semi
285 tristate "Cell Broadband Engine memory controller"
286 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
288 Support for error detection and correction on the
289 Cell Broadband Engine internal memory controller
290 on platform without a hypervisor
293 tristate "PPC4xx IBM DDR2 Memory Controller"
294 depends on EDAC_MM_EDAC && 4xx
296 This enables support for EDAC on the ECC memory used
297 with the IBM DDR2 memory controller found in various
298 PowerPC 4xx embedded processors such as the 405EX[r],
299 440SP, 440SPe, 460EX, 460GT and 460SX.
302 tristate "AMD8131 HyperTransport PCI-X Tunnel"
303 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
305 Support for error detection and correction on the
306 AMD8131 HyperTransport PCI-X Tunnel chip.
307 Note, add more Kconfig dependency if it's adopted
308 on some machine other than Maple.
311 tristate "AMD8111 HyperTransport I/O Hub"
312 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
314 Support for error detection and correction on the
315 AMD8111 HyperTransport I/O Hub chip.
316 Note, add more Kconfig dependency if it's adopted
317 on some machine other than Maple.
320 tristate "IBM CPC925 Memory Controller (PPC970FX)"
321 depends on EDAC_MM_EDAC && PPC64
323 Support for error detection and correction on the
324 IBM CPC925 Bridge and Memory Controller, which is
325 a companion chip to the PowerPC 970 family of
329 tristate "Tilera Memory Controller"
330 depends on EDAC_MM_EDAC && TILE
333 Support for error detection and correction on the
334 Tilera memory controller.
336 config EDAC_HIGHBANK_MC
337 tristate "Highbank Memory Controller"
338 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
340 Support for error detection and correction on the
341 Calxeda Highbank memory controller.
343 config EDAC_HIGHBANK_L2
344 tristate "Highbank L2 Cache"
345 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
347 Support for error detection and correction on the
348 Calxeda Highbank memory controller.
350 config EDAC_OCTEON_PC
351 tristate "Cavium Octeon Primary Caches"
352 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
354 Support for error detection and correction on the primary caches of
355 the cnMIPS cores of Cavium Octeon family SOCs.
357 config EDAC_OCTEON_L2C
358 tristate "Cavium Octeon Secondary Caches (L2C)"
359 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
361 Support for error detection and correction on the
362 Cavium Octeon family of SOCs.
364 config EDAC_OCTEON_LMC
365 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
366 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
368 Support for error detection and correction on the
369 Cavium Octeon family of SOCs.
371 config EDAC_OCTEON_PCI
372 tristate "Cavium Octeon PCI Controller"
373 depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
375 Support for error detection and correction on the
376 Cavium Octeon family of SOCs.