1 #include "amd64_edac.h"
2 #include <asm/amd_nb.h>
4 static struct edac_pci_ctl_info *amd64_ctl_pci;
6 static int report_gart_errors;
7 module_param(report_gart_errors, int, 0644);
10 * Set by command line parameter. If BIOS has enabled the ECC, this override is
11 * cleared to prevent re-enabling the hardware by this driver.
13 static int ecc_enable_override;
14 module_param(ecc_enable_override, int, 0644);
16 static struct msr __percpu *msrs;
19 * count successfully initialized driver instances for setup_pci_device()
21 static atomic_t drv_instances = ATOMIC_INIT(0);
23 /* Per-node driver instances */
24 static struct mem_ctl_info **mcis;
25 static struct ecc_settings **ecc_stngs;
28 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
29 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
32 *FIXME: Produce a better mapping/linearisation.
35 u32 scrubval; /* bit pattern for scrub rate */
36 u32 bandwidth; /* bandwidth consumed (bytes/sec) */
38 { 0x01, 1600000000UL},
60 { 0x00, 0UL}, /* scrubbing off */
63 static int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
64 u32 *val, const char *func)
68 err = pci_read_config_dword(pdev, offset, val);
70 amd64_warn("%s: error reading F%dx%03x.\n",
71 func, PCI_FUNC(pdev->devfn), offset);
76 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
77 u32 val, const char *func)
81 err = pci_write_config_dword(pdev, offset, val);
83 amd64_warn("%s: error writing to F%dx%03x.\n",
84 func, PCI_FUNC(pdev->devfn), offset);
91 * Depending on the family, F2 DCT reads need special handling:
93 * K8: has a single DCT only
95 * F10h: each DCT has its own set of regs
99 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
102 static int k8_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
108 return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
111 static int f10_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
114 return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
118 * Select DCT to which PCI cfg accesses are routed
120 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
124 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®);
127 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
130 static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
135 if (addr >= 0x140 && addr <= 0x1a0) {
140 f15h_select_dct(pvt, dct);
142 return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
146 * Memory scrubber control interface. For K8, memory scrubbing is handled by
147 * hardware and can involve L2 cache, dcache as well as the main memory. With
148 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
151 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
152 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
153 * bytes/sec for the setting.
155 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
156 * other archs, we might not have access to the caches directly.
160 * scan the scrub rate mapping table for a close or matching bandwidth value to
161 * issue. If requested is too big, then use last maximum value found.
163 static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
169 * map the configured rate (new_bw) to a value specific to the AMD64
170 * memory controller and apply to register. Search for the first
171 * bandwidth entry that is greater or equal than the setting requested
172 * and program that. If at last entry, turn off DRAM scrubbing.
174 for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
176 * skip scrub rates which aren't recommended
177 * (see F10 BKDG, F3x58)
179 if (scrubrates[i].scrubval < min_rate)
182 if (scrubrates[i].bandwidth <= new_bw)
186 * if no suitable bandwidth found, turn off DRAM scrubbing
187 * entirely by falling back to the last element in the
192 scrubval = scrubrates[i].scrubval;
194 pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F);
197 return scrubrates[i].bandwidth;
202 static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
204 struct amd64_pvt *pvt = mci->pvt_info;
205 u32 min_scrubrate = 0x5;
207 if (boot_cpu_data.x86 == 0xf)
210 /* F15h Erratum #505 */
211 if (boot_cpu_data.x86 == 0x15)
212 f15h_select_dct(pvt, 0);
214 return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate);
217 static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
219 struct amd64_pvt *pvt = mci->pvt_info;
221 int i, retval = -EINVAL;
223 /* F15h Erratum #505 */
224 if (boot_cpu_data.x86 == 0x15)
225 f15h_select_dct(pvt, 0);
227 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
229 scrubval = scrubval & 0x001F;
231 for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
232 if (scrubrates[i].scrubval == scrubval) {
233 retval = scrubrates[i].bandwidth;
241 * returns true if the SysAddr given by sys_addr matches the
242 * DRAM base/limit associated with node_id
244 static bool amd64_base_limit_match(struct amd64_pvt *pvt, u64 sys_addr,
249 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be
250 * all ones if the most significant implemented address bit is 1.
251 * Here we discard bits 63-40. See section 3.4.2 of AMD publication
252 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
253 * Application Programming.
255 addr = sys_addr & 0x000000ffffffffffull;
257 return ((addr >= get_dram_base(pvt, nid)) &&
258 (addr <= get_dram_limit(pvt, nid)));
262 * Attempt to map a SysAddr to a node. On success, return a pointer to the
263 * mem_ctl_info structure for the node that the SysAddr maps to.
265 * On failure, return NULL.
267 static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
270 struct amd64_pvt *pvt;
275 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
276 * 3.4.4.2) registers to map the SysAddr to a node ID.
281 * The value of this field should be the same for all DRAM Base
282 * registers. Therefore we arbitrarily choose to read it from the
283 * register for node 0.
285 intlv_en = dram_intlv_en(pvt, 0);
288 for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
289 if (amd64_base_limit_match(pvt, sys_addr, node_id))
295 if (unlikely((intlv_en != 0x01) &&
296 (intlv_en != 0x03) &&
297 (intlv_en != 0x07))) {
298 amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
302 bits = (((u32) sys_addr) >> 12) & intlv_en;
304 for (node_id = 0; ; ) {
305 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
306 break; /* intlv_sel field matches */
308 if (++node_id >= DRAM_RANGES)
312 /* sanity test for sys_addr */
313 if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) {
314 amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
315 "range for node %d with node interleaving enabled.\n",
316 __func__, sys_addr, node_id);
321 return edac_mc_find((int)node_id);
324 edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
325 (unsigned long)sys_addr);
331 * compute the CS base address of the @csrow on the DRAM controller @dct.
332 * For details see F2x[5C:40] in the processor's BKDG
334 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
335 u64 *base, u64 *mask)
337 u64 csbase, csmask, base_bits, mask_bits;
340 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) {
341 csbase = pvt->csels[dct].csbases[csrow];
342 csmask = pvt->csels[dct].csmasks[csrow];
343 base_bits = GENMASK(21, 31) | GENMASK(9, 15);
344 mask_bits = GENMASK(21, 29) | GENMASK(9, 15);
347 csbase = pvt->csels[dct].csbases[csrow];
348 csmask = pvt->csels[dct].csmasks[csrow >> 1];
351 if (boot_cpu_data.x86 == 0x15)
352 base_bits = mask_bits = GENMASK(19,30) | GENMASK(5,13);
354 base_bits = mask_bits = GENMASK(19,28) | GENMASK(5,13);
357 *base = (csbase & base_bits) << addr_shift;
360 /* poke holes for the csmask */
361 *mask &= ~(mask_bits << addr_shift);
363 *mask |= (csmask & mask_bits) << addr_shift;
366 #define for_each_chip_select(i, dct, pvt) \
367 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
369 #define chip_select_base(i, dct, pvt) \
370 pvt->csels[dct].csbases[i]
372 #define for_each_chip_select_mask(i, dct, pvt) \
373 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
376 * @input_addr is an InputAddr associated with the node given by mci. Return the
377 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
379 static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
381 struct amd64_pvt *pvt;
387 for_each_chip_select(csrow, 0, pvt) {
388 if (!csrow_enabled(csrow, 0, pvt))
391 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);
395 if ((input_addr & mask) == (base & mask)) {
396 edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
397 (unsigned long)input_addr, csrow,
403 edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
404 (unsigned long)input_addr, pvt->mc_node_id);
410 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
411 * for the node represented by mci. Info is passed back in *hole_base,
412 * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if
413 * info is invalid. Info may be invalid for either of the following reasons:
415 * - The revision of the node is not E or greater. In this case, the DRAM Hole
416 * Address Register does not exist.
418 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
419 * indicating that its contents are not valid.
421 * The values passed back in *hole_base, *hole_offset, and *hole_size are
422 * complete 32-bit values despite the fact that the bitfields in the DHAR
423 * only represent bits 31-24 of the base and offset values.
425 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
426 u64 *hole_offset, u64 *hole_size)
428 struct amd64_pvt *pvt = mci->pvt_info;
431 /* only revE and later have the DRAM Hole Address Register */
432 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) {
433 edac_dbg(1, " revision %d for node %d does not support DHAR\n",
434 pvt->ext_model, pvt->mc_node_id);
438 /* valid for Fam10h and above */
439 if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
440 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n");
444 if (!dhar_valid(pvt)) {
445 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n",
450 /* This node has Memory Hoisting */
452 /* +------------------+--------------------+--------------------+-----
453 * | memory | DRAM hole | relocated |
454 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
456 * | | | [0x100000000, |
457 * | | | (0x100000000+ |
458 * | | | (0xffffffff-x))] |
459 * +------------------+--------------------+--------------------+-----
461 * Above is a diagram of physical memory showing the DRAM hole and the
462 * relocated addresses from the DRAM hole. As shown, the DRAM hole
463 * starts at address x (the base address) and extends through address
464 * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
465 * addresses in the hole so that they start at 0x100000000.
468 base = dhar_base(pvt);
471 *hole_size = (0x1ull << 32) - base;
473 if (boot_cpu_data.x86 > 0xf)
474 *hole_offset = f10_dhar_offset(pvt);
476 *hole_offset = k8_dhar_offset(pvt);
478 edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
479 pvt->mc_node_id, (unsigned long)*hole_base,
480 (unsigned long)*hole_offset, (unsigned long)*hole_size);
484 EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info);
487 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
488 * assumed that sys_addr maps to the node given by mci.
490 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
491 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
492 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
493 * then it is also involved in translating a SysAddr to a DramAddr. Sections
494 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
495 * These parts of the documentation are unclear. I interpret them as follows:
497 * When node n receives a SysAddr, it processes the SysAddr as follows:
499 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
500 * Limit registers for node n. If the SysAddr is not within the range
501 * specified by the base and limit values, then node n ignores the Sysaddr
502 * (since it does not map to node n). Otherwise continue to step 2 below.
504 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
505 * disabled so skip to step 3 below. Otherwise see if the SysAddr is within
506 * the range of relocated addresses (starting at 0x100000000) from the DRAM
507 * hole. If not, skip to step 3 below. Else get the value of the
508 * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
509 * offset defined by this value from the SysAddr.
511 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
512 * Base register for node n. To obtain the DramAddr, subtract the base
513 * address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
515 static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
517 struct amd64_pvt *pvt = mci->pvt_info;
518 u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
521 dram_base = get_dram_base(pvt, pvt->mc_node_id);
523 ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
526 if ((sys_addr >= (1ull << 32)) &&
527 (sys_addr < ((1ull << 32) + hole_size))) {
528 /* use DHAR to translate SysAddr to DramAddr */
529 dram_addr = sys_addr - hole_offset;
531 edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
532 (unsigned long)sys_addr,
533 (unsigned long)dram_addr);
540 * Translate the SysAddr to a DramAddr as shown near the start of
541 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
542 * only deals with 40-bit values. Therefore we discard bits 63-40 of
543 * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
544 * discard are all 1s. Otherwise the bits we discard are all 0s. See
545 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
546 * Programmer's Manual Volume 1 Application Programming.
548 dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base;
550 edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
551 (unsigned long)sys_addr, (unsigned long)dram_addr);
556 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
557 * (section 3.4.4.1). Return the number of bits from a SysAddr that are used
558 * for node interleaving.
560 static int num_node_interleave_bits(unsigned intlv_en)
562 static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
565 BUG_ON(intlv_en > 7);
566 n = intlv_shift_table[intlv_en];
570 /* Translate the DramAddr given by @dram_addr to an InputAddr. */
571 static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
573 struct amd64_pvt *pvt;
580 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
581 * concerning translating a DramAddr to an InputAddr.
583 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
584 input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) +
587 edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
588 intlv_shift, (unsigned long)dram_addr,
589 (unsigned long)input_addr);
595 * Translate the SysAddr represented by @sys_addr to an InputAddr. It is
596 * assumed that @sys_addr maps to the node given by mci.
598 static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
603 dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));
605 edac_dbg(2, "SysAdddr 0x%lx translates to InputAddr 0x%lx\n",
606 (unsigned long)sys_addr, (unsigned long)input_addr);
613 * @input_addr is an InputAddr associated with the node represented by mci.
614 * Translate @input_addr to a DramAddr and return the result.
616 static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
618 struct amd64_pvt *pvt;
619 unsigned node_id, intlv_shift;
624 * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
625 * shows how to translate a DramAddr to an InputAddr. Here we reverse
626 * this procedure. When translating from a DramAddr to an InputAddr, the
627 * bits used for node interleaving are discarded. Here we recover these
628 * bits from the IntlvSel field of the DRAM Limit register (section
629 * 3.4.4.2) for the node that input_addr is associated with.
632 node_id = pvt->mc_node_id;
636 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
637 if (intlv_shift == 0) {
638 edac_dbg(1, " InputAddr 0x%lx translates to DramAddr of same value\n",
639 (unsigned long)input_addr);
644 bits = ((input_addr & GENMASK(12, 35)) << intlv_shift) +
645 (input_addr & 0xfff);
647 intlv_sel = dram_intlv_sel(pvt, node_id) & ((1 << intlv_shift) - 1);
648 dram_addr = bits + (intlv_sel << 12);
650 edac_dbg(1, "InputAddr 0x%lx translates to DramAddr 0x%lx (%d node interleave bits)\n",
651 (unsigned long)input_addr,
652 (unsigned long)dram_addr, intlv_shift);
658 * @dram_addr is a DramAddr that maps to the node represented by mci. Convert
659 * @dram_addr to a SysAddr.
661 static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr)
663 struct amd64_pvt *pvt = mci->pvt_info;
664 u64 hole_base, hole_offset, hole_size, base, sys_addr;
667 ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
670 if ((dram_addr >= hole_base) &&
671 (dram_addr < (hole_base + hole_size))) {
672 sys_addr = dram_addr + hole_offset;
674 edac_dbg(1, "using DHAR to translate DramAddr 0x%lx to SysAddr 0x%lx\n",
675 (unsigned long)dram_addr,
676 (unsigned long)sys_addr);
682 base = get_dram_base(pvt, pvt->mc_node_id);
683 sys_addr = dram_addr + base;
686 * The sys_addr we have computed up to this point is a 40-bit value
687 * because the k8 deals with 40-bit values. However, the value we are
688 * supposed to return is a full 64-bit physical address. The AMD
689 * x86-64 architecture specifies that the most significant implemented
690 * address bit through bit 63 of a physical address must be either all
691 * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a
692 * 64-bit value below. See section 3.4.2 of AMD publication 24592:
693 * AMD x86-64 Architecture Programmer's Manual Volume 1 Application
696 sys_addr |= ~((sys_addr & (1ull << 39)) - 1);
698 edac_dbg(1, " Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n",
699 pvt->mc_node_id, (unsigned long)dram_addr,
700 (unsigned long)sys_addr);
706 * @input_addr is an InputAddr associated with the node given by mci. Translate
707 * @input_addr to a SysAddr.
709 static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci,
712 return dram_addr_to_sys_addr(mci,
713 input_addr_to_dram_addr(mci, input_addr));
716 /* Map the Error address to a PAGE and PAGE OFFSET. */
717 static inline void error_address_to_page_and_offset(u64 error_address,
718 u32 *page, u32 *offset)
720 *page = (u32) (error_address >> PAGE_SHIFT);
721 *offset = ((u32) error_address) & ~PAGE_MASK;
725 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
726 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
727 * of a node that detected an ECC memory error. mci represents the node that
728 * the error address maps to (possibly different from the node that detected
729 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
732 static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
736 csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));
739 amd64_mc_err(mci, "Failed to translate InputAddr to csrow for "
740 "address 0x%lx\n", (unsigned long)sys_addr);
744 static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
747 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
750 static unsigned long amd64_determine_edac_cap(struct amd64_pvt *pvt)
753 unsigned long edac_cap = EDAC_FLAG_NONE;
755 bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F)
759 if (pvt->dclr0 & BIT(bit))
760 edac_cap = EDAC_FLAG_SECDED;
765 static void amd64_debug_display_dimm_sizes(struct amd64_pvt *, u8);
767 static void amd64_dump_dramcfg_low(u32 dclr, int chan)
769 edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
771 edac_dbg(1, " DIMM type: %sbuffered; all DIMMs support ECC: %s\n",
772 (dclr & BIT(16)) ? "un" : "",
773 (dclr & BIT(19)) ? "yes" : "no");
775 edac_dbg(1, " PAR/ERR parity: %s\n",
776 (dclr & BIT(8)) ? "enabled" : "disabled");
778 if (boot_cpu_data.x86 == 0x10)
779 edac_dbg(1, " DCT 128bit mode width: %s\n",
780 (dclr & BIT(11)) ? "128b" : "64b");
782 edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
783 (dclr & BIT(12)) ? "yes" : "no",
784 (dclr & BIT(13)) ? "yes" : "no",
785 (dclr & BIT(14)) ? "yes" : "no",
786 (dclr & BIT(15)) ? "yes" : "no");
789 /* Display and decode various NB registers for debug purposes. */
790 static void dump_misc_regs(struct amd64_pvt *pvt)
792 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
794 edac_dbg(1, " NB two channel DRAM capable: %s\n",
795 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
797 edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n",
798 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
799 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
801 amd64_dump_dramcfg_low(pvt->dclr0, 0);
803 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
805 edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
806 pvt->dhar, dhar_base(pvt),
807 (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt)
808 : f10_dhar_offset(pvt));
810 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
812 amd64_debug_display_dimm_sizes(pvt, 0);
814 /* everything below this point is Fam10h and above */
815 if (boot_cpu_data.x86 == 0xf)
818 amd64_debug_display_dimm_sizes(pvt, 1);
820 amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4"));
822 /* Only if NOT ganged does dclr1 have valid info */
823 if (!dct_ganging_enabled(pvt))
824 amd64_dump_dramcfg_low(pvt->dclr1, 1);
828 * see BKDG, F2x[1,0][5C:40], F2[1,0][6C:60]
830 static void prep_chip_selects(struct amd64_pvt *pvt)
832 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) {
833 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
834 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
836 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
837 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
842 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
844 static void read_dct_base_mask(struct amd64_pvt *pvt)
848 prep_chip_selects(pvt);
850 for_each_chip_select(cs, 0, pvt) {
851 int reg0 = DCSB0 + (cs * 4);
852 int reg1 = DCSB1 + (cs * 4);
853 u32 *base0 = &pvt->csels[0].csbases[cs];
854 u32 *base1 = &pvt->csels[1].csbases[cs];
856 if (!amd64_read_dct_pci_cfg(pvt, reg0, base0))
857 edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n",
860 if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt))
863 if (!amd64_read_dct_pci_cfg(pvt, reg1, base1))
864 edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n",
868 for_each_chip_select_mask(cs, 0, pvt) {
869 int reg0 = DCSM0 + (cs * 4);
870 int reg1 = DCSM1 + (cs * 4);
871 u32 *mask0 = &pvt->csels[0].csmasks[cs];
872 u32 *mask1 = &pvt->csels[1].csmasks[cs];
874 if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0))
875 edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n",
878 if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt))
881 if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1))
882 edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n",
887 static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt, int cs)
891 /* F15h supports only DDR3 */
892 if (boot_cpu_data.x86 >= 0x15)
893 type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
894 else if (boot_cpu_data.x86 == 0x10 || pvt->ext_model >= K8_REV_F) {
895 if (pvt->dchr0 & DDR3_MODE)
896 type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
898 type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
900 type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
903 amd64_info("CS%d: %s\n", cs, edac_mem_types[type]);
908 /* Get the number of DCT channels the memory controller is using. */
909 static int k8_early_channel_count(struct amd64_pvt *pvt)
913 if (pvt->ext_model >= K8_REV_F)
914 /* RevF (NPT) and later */
915 flag = pvt->dclr0 & WIDTH_128;
917 /* RevE and earlier */
918 flag = pvt->dclr0 & REVE_WIDTH_128;
923 return (flag) ? 2 : 1;
926 /* On F10h and later ErrAddr is MC4_ADDR[47:1] */
927 static u64 get_error_address(struct mce *m)
929 struct cpuinfo_x86 *c = &boot_cpu_data;
939 addr = m->addr & GENMASK(start_bit, end_bit);
942 * Erratum 637 workaround
944 if (c->x86 == 0x15) {
945 struct amd64_pvt *pvt;
946 u64 cc6_base, tmp_addr;
948 u8 mce_nid, intlv_en;
950 if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7)
953 mce_nid = amd_get_nb_id(m->extcpu);
954 pvt = mcis[mce_nid]->pvt_info;
956 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
957 intlv_en = tmp >> 21 & 0x7;
959 /* add [47:27] + 3 trailing bits */
960 cc6_base = (tmp & GENMASK(0, 20)) << 3;
962 /* reverse and add DramIntlvEn */
963 cc6_base |= intlv_en ^ 0x7;
969 return cc6_base | (addr & GENMASK(0, 23));
971 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);
974 tmp_addr = (addr & GENMASK(12, 23)) << __fls(intlv_en + 1);
976 /* OR DramIntlvSel into bits [14:12] */
977 tmp_addr |= (tmp & GENMASK(21, 23)) >> 9;
979 /* add remaining [11:0] bits from original MC4_ADDR */
980 tmp_addr |= addr & GENMASK(0, 11);
982 return cc6_base | tmp_addr;
988 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
990 struct cpuinfo_x86 *c = &boot_cpu_data;
991 int off = range << 3;
993 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo);
994 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
999 if (!dram_rw(pvt, range))
1002 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi);
1003 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
1005 /* Factor in CC6 save area by reading dst node's limit reg */
1006 if (c->x86 == 0x15) {
1007 struct pci_dev *f1 = NULL;
1008 u8 nid = dram_dst_node(pvt, range);
1011 f1 = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0x18 + nid, 1));
1015 amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
1017 pvt->ranges[range].lim.lo &= GENMASK(0, 15);
1019 /* {[39:27],111b} */
1020 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
1022 pvt->ranges[range].lim.hi &= GENMASK(0, 7);
1025 pvt->ranges[range].lim.hi |= llim >> 13;
1031 static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
1034 struct mem_ctl_info *src_mci;
1035 struct amd64_pvt *pvt = mci->pvt_info;
1039 error_address_to_page_and_offset(sys_addr, &page, &offset);
1042 * Find out which node the error address belongs to. This may be
1043 * different from the node that detected the error.
1045 src_mci = find_mc_by_sys_addr(mci, sys_addr);
1047 amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n",
1048 (unsigned long)sys_addr);
1049 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
1050 page, offset, syndrome,
1052 "failed to map error addr to a node",
1057 /* Now map the sys_addr to a CSROW */
1058 csrow = sys_addr_to_csrow(src_mci, sys_addr);
1060 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
1061 page, offset, syndrome,
1063 "failed to map error addr to a csrow",
1068 /* CHIPKILL enabled */
1069 if (pvt->nbcfg & NBCFG_CHIPKILL) {
1070 channel = get_channel_from_ecc_syndrome(mci, syndrome);
1073 * Syndrome didn't map, so we don't know which of the
1074 * 2 DIMMs is in error. So we need to ID 'both' of them
1077 amd64_mc_warn(src_mci, "unknown syndrome 0x%04x - "
1078 "possible error reporting race\n",
1080 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
1081 page, offset, syndrome,
1083 "unknown syndrome - possible error reporting race",
1089 * non-chipkill ecc mode
1091 * The k8 documentation is unclear about how to determine the
1092 * channel number when using non-chipkill memory. This method
1093 * was obtained from email communication with someone at AMD.
1094 * (Wish the email was placed in this comment - norsk)
1096 channel = ((sys_addr & BIT(3)) != 0);
1099 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, src_mci,
1100 page, offset, syndrome,
1105 static int ddr2_cs_size(unsigned i, bool dct_width)
1111 else if (!(i & 0x1))
1114 shift = (i + 1) >> 1;
1116 return 128 << (shift + !!dct_width);
1119 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1122 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
1124 if (pvt->ext_model >= K8_REV_F) {
1125 WARN_ON(cs_mode > 11);
1126 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
1128 else if (pvt->ext_model >= K8_REV_D) {
1130 WARN_ON(cs_mode > 10);
1133 * the below calculation, besides trying to win an obfuscated C
1134 * contest, maps cs_mode values to DIMM chip select sizes. The
1137 * cs_mode CS size (mb)
1138 * ======= ============
1151 * Basically, it calculates a value with which to shift the
1152 * smallest CS size of 32MB.
1154 * ddr[23]_cs_size have a similar purpose.
1156 diff = cs_mode/3 + (unsigned)(cs_mode > 5);
1158 return 32 << (cs_mode - diff);
1161 WARN_ON(cs_mode > 6);
1162 return 32 << cs_mode;
1167 * Get the number of DCT channels in use.
1170 * number of Memory Channels in operation
1172 * contents of the DCL0_LOW register
1174 static int f1x_early_channel_count(struct amd64_pvt *pvt)
1176 int i, j, channels = 0;
1178 /* On F10h, if we are in 128 bit mode, then we are using 2 channels */
1179 if (boot_cpu_data.x86 == 0x10 && (pvt->dclr0 & WIDTH_128))
1183 * Need to check if in unganged mode: In such, there are 2 channels,
1184 * but they are not in 128 bit mode and thus the above 'dclr0' status
1187 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
1188 * their CSEnable bit on. If so, then SINGLE DIMM case.
1190 edac_dbg(0, "Data width is not 128 bits - need more decoding\n");
1193 * Check DRAM Bank Address Mapping values for each DIMM to see if there
1194 * is more than just one DIMM present in unganged mode. Need to check
1195 * both controllers since DIMMs can be placed in either one.
1197 for (i = 0; i < 2; i++) {
1198 u32 dbam = (i ? pvt->dbam1 : pvt->dbam0);
1200 for (j = 0; j < 4; j++) {
1201 if (DBAM_DIMM(j, dbam) > 0) {
1211 amd64_info("MCT channel count: %d\n", channels);
1216 static int ddr3_cs_size(unsigned i, bool dct_width)
1221 if (i == 0 || i == 3 || i == 4)
1227 else if (!(i & 0x1))
1230 shift = (i + 1) >> 1;
1233 cs_size = (128 * (1 << !!dct_width)) << shift;
1238 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1241 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
1243 WARN_ON(cs_mode > 11);
1245 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
1246 return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
1248 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
1252 * F15h supports only 64bit DCT interfaces
1254 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1257 WARN_ON(cs_mode > 12);
1259 return ddr3_cs_size(cs_mode, false);
1262 static void read_dram_ctl_register(struct amd64_pvt *pvt)
1265 if (boot_cpu_data.x86 == 0xf)
1268 if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) {
1269 edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
1270 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
1272 edac_dbg(0, " DCTs operate in %s mode\n",
1273 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
1275 if (!dct_ganging_enabled(pvt))
1276 edac_dbg(0, " Address range split per DCT: %s\n",
1277 (dct_high_range_enabled(pvt) ? "yes" : "no"));
1279 edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
1280 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
1281 (dct_memory_cleared(pvt) ? "yes" : "no"));
1283 edac_dbg(0, " channel interleave: %s, "
1284 "interleave bits selector: 0x%x\n",
1285 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
1286 dct_sel_interleave_addr(pvt));
1289 amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi);
1293 * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
1294 * Interleaving Modes.
1296 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
1297 bool hi_range_sel, u8 intlv_en)
1299 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
1301 if (dct_ganging_enabled(pvt))
1305 return dct_sel_high;
1308 * see F2x110[DctSelIntLvAddr] - channel interleave mode
1310 if (dct_interleave_enabled(pvt)) {
1311 u8 intlv_addr = dct_sel_interleave_addr(pvt);
1313 /* return DCT select function: 0=DCT0, 1=DCT1 */
1315 return sys_addr >> 6 & 1;
1317 if (intlv_addr & 0x2) {
1318 u8 shift = intlv_addr & 0x1 ? 9 : 6;
1319 u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2;
1321 return ((sys_addr >> shift) & 1) ^ temp;
1324 return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
1327 if (dct_high_range_enabled(pvt))
1328 return ~dct_sel_high & 1;
1333 /* Convert the sys_addr to the normalized DCT address */
1334 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, unsigned range,
1335 u64 sys_addr, bool hi_rng,
1336 u32 dct_sel_base_addr)
1339 u64 dram_base = get_dram_base(pvt, range);
1340 u64 hole_off = f10_dhar_offset(pvt);
1341 u64 dct_sel_base_off = (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
1346 * base address of high range is below 4Gb
1347 * (bits [47:27] at [31:11])
1348 * DRAM address space on this DCT is hoisted above 4Gb &&
1351 * remove hole offset from sys_addr
1353 * remove high range offset from sys_addr
1355 if ((!(dct_sel_base_addr >> 16) ||
1356 dct_sel_base_addr < dhar_base(pvt)) &&
1358 (sys_addr >= BIT_64(32)))
1359 chan_off = hole_off;
1361 chan_off = dct_sel_base_off;
1365 * we have a valid hole &&
1370 * remove dram base to normalize to DCT address
1372 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
1373 chan_off = hole_off;
1375 chan_off = dram_base;
1378 return (sys_addr & GENMASK(6,47)) - (chan_off & GENMASK(23,47));
1382 * checks if the csrow passed in is marked as SPARED, if so returns the new
1385 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
1389 if (online_spare_swap_done(pvt, dct) &&
1390 csrow == online_spare_bad_dramcs(pvt, dct)) {
1392 for_each_chip_select(tmp_cs, dct, pvt) {
1393 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
1403 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
1404 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
1407 * -EINVAL: NOT FOUND
1408 * 0..csrow = Chip-Select Row
1410 static int f1x_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct)
1412 struct mem_ctl_info *mci;
1413 struct amd64_pvt *pvt;
1414 u64 cs_base, cs_mask;
1415 int cs_found = -EINVAL;
1422 pvt = mci->pvt_info;
1424 edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
1426 for_each_chip_select(csrow, dct, pvt) {
1427 if (!csrow_enabled(csrow, dct, pvt))
1430 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
1432 edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
1433 csrow, cs_base, cs_mask);
1437 edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
1438 (in_addr & cs_mask), (cs_base & cs_mask));
1440 if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
1441 cs_found = f10_process_possible_spare(pvt, dct, csrow);
1443 edac_dbg(1, " MATCH csrow=%d\n", cs_found);
1451 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
1452 * swapped with a region located at the bottom of memory so that the GPU can use
1453 * the interleaved region and thus two channels.
1455 static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
1457 u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr;
1459 if (boot_cpu_data.x86 == 0x10) {
1460 /* only revC3 and revE have that feature */
1461 if (boot_cpu_data.x86_model < 4 ||
1462 (boot_cpu_data.x86_model < 0xa &&
1463 boot_cpu_data.x86_mask < 3))
1467 amd64_read_dct_pci_cfg(pvt, SWAP_INTLV_REG, &swap_reg);
1469 if (!(swap_reg & 0x1))
1472 swap_base = (swap_reg >> 3) & 0x7f;
1473 swap_limit = (swap_reg >> 11) & 0x7f;
1474 rgn_size = (swap_reg >> 20) & 0x7f;
1475 tmp_addr = sys_addr >> 27;
1477 if (!(sys_addr >> 34) &&
1478 (((tmp_addr >= swap_base) &&
1479 (tmp_addr <= swap_limit)) ||
1480 (tmp_addr < rgn_size)))
1481 return sys_addr ^ (u64)swap_base << 27;
1486 /* For a given @dram_range, check if @sys_addr falls within it. */
1487 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
1488 u64 sys_addr, int *nid, int *chan_sel)
1490 int cs_found = -EINVAL;
1494 bool high_range = false;
1496 u8 node_id = dram_dst_node(pvt, range);
1497 u8 intlv_en = dram_intlv_en(pvt, range);
1498 u32 intlv_sel = dram_intlv_sel(pvt, range);
1500 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
1501 range, sys_addr, get_dram_limit(pvt, range));
1503 if (dhar_valid(pvt) &&
1504 dhar_base(pvt) <= sys_addr &&
1505 sys_addr < BIT_64(32)) {
1506 amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
1511 if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
1514 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
1516 dct_sel_base = dct_sel_baseaddr(pvt);
1519 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
1520 * select between DCT0 and DCT1.
1522 if (dct_high_range_enabled(pvt) &&
1523 !dct_ganging_enabled(pvt) &&
1524 ((sys_addr >> 27) >= (dct_sel_base >> 11)))
1527 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
1529 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
1530 high_range, dct_sel_base);
1532 /* Remove node interleaving, see F1x120 */
1534 chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) |
1535 (chan_addr & 0xfff);
1537 /* remove channel interleave */
1538 if (dct_interleave_enabled(pvt) &&
1539 !dct_high_range_enabled(pvt) &&
1540 !dct_ganging_enabled(pvt)) {
1542 if (dct_sel_interleave_addr(pvt) != 1) {
1543 if (dct_sel_interleave_addr(pvt) == 0x3)
1545 chan_addr = ((chan_addr >> 10) << 9) |
1546 (chan_addr & 0x1ff);
1548 /* A[6] or hash 6 */
1549 chan_addr = ((chan_addr >> 7) << 6) |
1553 chan_addr = ((chan_addr >> 13) << 12) |
1554 (chan_addr & 0xfff);
1557 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
1559 cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);
1561 if (cs_found >= 0) {
1563 *chan_sel = channel;
1568 static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr,
1569 int *node, int *chan_sel)
1571 int cs_found = -EINVAL;
1574 for (range = 0; range < DRAM_RANGES; range++) {
1576 if (!dram_rw(pvt, range))
1579 if ((get_dram_base(pvt, range) <= sys_addr) &&
1580 (get_dram_limit(pvt, range) >= sys_addr)) {
1582 cs_found = f1x_match_to_this_node(pvt, range,
1593 * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps
1594 * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
1596 * The @sys_addr is usually an error address received from the hardware
1599 static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
1602 struct amd64_pvt *pvt = mci->pvt_info;
1604 int nid, csrow, chan = 0;
1606 error_address_to_page_and_offset(sys_addr, &page, &offset);
1608 csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan);
1611 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
1612 page, offset, syndrome,
1614 "failed to map error addr to a csrow",
1620 * We need the syndromes for channel detection only when we're
1621 * ganged. Otherwise @chan should already contain the channel at
1624 if (dct_ganging_enabled(pvt))
1625 chan = get_channel_from_ecc_syndrome(mci, syndrome);
1627 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
1628 page, offset, syndrome,
1634 * debug routine to display the memory sizes of all logical DIMMs and its
1637 static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
1639 int dimm, size0, size1, factor = 0;
1640 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
1641 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
1643 if (boot_cpu_data.x86 == 0xf) {
1644 if (pvt->dclr0 & WIDTH_128)
1647 /* K8 families < revF not supported yet */
1648 if (pvt->ext_model < K8_REV_F)
1654 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 : pvt->dbam0;
1655 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases
1656 : pvt->csels[0].csbases;
1658 edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
1661 edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
1663 /* Dump memory sizes for DIMM and its CSROWs */
1664 for (dimm = 0; dimm < 4; dimm++) {
1667 if (dcsb[dimm*2] & DCSB_CS_ENABLE)
1668 size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
1669 DBAM_DIMM(dimm, dbam));
1672 if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE)
1673 size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
1674 DBAM_DIMM(dimm, dbam));
1676 amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
1677 dimm * 2, size0 << factor,
1678 dimm * 2 + 1, size1 << factor);
1682 static struct amd64_family_type amd64_family_types[] = {
1685 .f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
1686 .f3_id = PCI_DEVICE_ID_AMD_K8_NB_MISC,
1688 .early_channel_count = k8_early_channel_count,
1689 .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow,
1690 .dbam_to_cs = k8_dbam_to_chip_select,
1691 .read_dct_pci_cfg = k8_read_dct_pci_cfg,
1696 .f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP,
1697 .f3_id = PCI_DEVICE_ID_AMD_10H_NB_MISC,
1699 .early_channel_count = f1x_early_channel_count,
1700 .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
1701 .dbam_to_cs = f10_dbam_to_chip_select,
1702 .read_dct_pci_cfg = f10_read_dct_pci_cfg,
1707 .f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1,
1708 .f3_id = PCI_DEVICE_ID_AMD_15H_NB_F3,
1710 .early_channel_count = f1x_early_channel_count,
1711 .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
1712 .dbam_to_cs = f15_dbam_to_chip_select,
1713 .read_dct_pci_cfg = f15_read_dct_pci_cfg,
1718 static struct pci_dev *pci_get_related_function(unsigned int vendor,
1719 unsigned int device,
1720 struct pci_dev *related)
1722 struct pci_dev *dev = NULL;
1724 dev = pci_get_device(vendor, device, dev);
1726 if ((dev->bus->number == related->bus->number) &&
1727 (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
1729 dev = pci_get_device(vendor, device, dev);
1736 * These are tables of eigenvectors (one per line) which can be used for the
1737 * construction of the syndrome tables. The modified syndrome search algorithm
1738 * uses those to find the symbol in error and thus the DIMM.
1740 * Algorithm courtesy of Ross LaFetra from AMD.
1742 static u16 x4_vectors[] = {
1743 0x2f57, 0x1afe, 0x66cc, 0xdd88,
1744 0x11eb, 0x3396, 0x7f4c, 0xeac8,
1745 0x0001, 0x0002, 0x0004, 0x0008,
1746 0x1013, 0x3032, 0x4044, 0x8088,
1747 0x106b, 0x30d6, 0x70fc, 0xe0a8,
1748 0x4857, 0xc4fe, 0x13cc, 0x3288,
1749 0x1ac5, 0x2f4a, 0x5394, 0xa1e8,
1750 0x1f39, 0x251e, 0xbd6c, 0x6bd8,
1751 0x15c1, 0x2a42, 0x89ac, 0x4758,
1752 0x2b03, 0x1602, 0x4f0c, 0xca08,
1753 0x1f07, 0x3a0e, 0x6b04, 0xbd08,
1754 0x8ba7, 0x465e, 0x244c, 0x1cc8,
1755 0x2b87, 0x164e, 0x642c, 0xdc18,
1756 0x40b9, 0x80de, 0x1094, 0x20e8,
1757 0x27db, 0x1eb6, 0x9dac, 0x7b58,
1758 0x11c1, 0x2242, 0x84ac, 0x4c58,
1759 0x1be5, 0x2d7a, 0x5e34, 0xa718,
1760 0x4b39, 0x8d1e, 0x14b4, 0x28d8,
1761 0x4c97, 0xc87e, 0x11fc, 0x33a8,
1762 0x8e97, 0x497e, 0x2ffc, 0x1aa8,
1763 0x16b3, 0x3d62, 0x4f34, 0x8518,
1764 0x1e2f, 0x391a, 0x5cac, 0xf858,
1765 0x1d9f, 0x3b7a, 0x572c, 0xfe18,
1766 0x15f5, 0x2a5a, 0x5264, 0xa3b8,
1767 0x1dbb, 0x3b66, 0x715c, 0xe3f8,
1768 0x4397, 0xc27e, 0x17fc, 0x3ea8,
1769 0x1617, 0x3d3e, 0x6464, 0xb8b8,
1770 0x23ff, 0x12aa, 0xab6c, 0x56d8,
1771 0x2dfb, 0x1ba6, 0x913c, 0x7328,
1772 0x185d, 0x2ca6, 0x7914, 0x9e28,
1773 0x171b, 0x3e36, 0x7d7c, 0xebe8,
1774 0x4199, 0x82ee, 0x19f4, 0x2e58,
1775 0x4807, 0xc40e, 0x130c, 0x3208,
1776 0x1905, 0x2e0a, 0x5804, 0xac08,
1777 0x213f, 0x132a, 0xadfc, 0x5ba8,
1778 0x19a9, 0x2efe, 0xb5cc, 0x6f88,
1781 static u16 x8_vectors[] = {
1782 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480,
1783 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80,
1784 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80,
1785 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80,
1786 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780,
1787 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080,
1788 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080,
1789 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080,
1790 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80,
1791 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580,
1792 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880,
1793 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280,
1794 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180,
1795 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580,
1796 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280,
1797 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180,
1798 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080,
1799 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
1800 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
1803 static int decode_syndrome(u16 syndrome, u16 *vectors, unsigned num_vecs,
1806 unsigned int i, err_sym;
1808 for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) {
1810 unsigned v_idx = err_sym * v_dim;
1811 unsigned v_end = (err_sym + 1) * v_dim;
1813 /* walk over all 16 bits of the syndrome */
1814 for (i = 1; i < (1U << 16); i <<= 1) {
1816 /* if bit is set in that eigenvector... */
1817 if (v_idx < v_end && vectors[v_idx] & i) {
1818 u16 ev_comp = vectors[v_idx++];
1820 /* ... and bit set in the modified syndrome, */
1830 /* can't get to zero, move to next symbol */
1835 edac_dbg(0, "syndrome(%x) not found\n", syndrome);
1839 static int map_err_sym_to_channel(int err_sym, int sym_size)
1852 return err_sym >> 4;
1858 /* imaginary bits not in a DIMM */
1860 WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n",
1872 return err_sym >> 3;
1878 static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
1880 struct amd64_pvt *pvt = mci->pvt_info;
1883 if (pvt->ecc_sym_sz == 8)
1884 err_sym = decode_syndrome(syndrome, x8_vectors,
1885 ARRAY_SIZE(x8_vectors),
1887 else if (pvt->ecc_sym_sz == 4)
1888 err_sym = decode_syndrome(syndrome, x4_vectors,
1889 ARRAY_SIZE(x4_vectors),
1892 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz);
1896 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz);
1900 * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR
1901 * ADDRESS and process.
1903 static void amd64_handle_ce(struct mem_ctl_info *mci, struct mce *m)
1905 struct amd64_pvt *pvt = mci->pvt_info;
1909 /* Ensure that the Error Address is VALID */
1910 if (!(m->status & MCI_STATUS_ADDRV)) {
1911 amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n");
1912 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
1915 "HW has no ERROR_ADDRESS available",
1920 sys_addr = get_error_address(m);
1921 syndrome = extract_syndrome(m->status);
1923 amd64_mc_err(mci, "CE ERROR_ADDRESS= 0x%llx\n", sys_addr);
1925 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, syndrome);
1928 /* Handle any Un-correctable Errors (UEs) */
1929 static void amd64_handle_ue(struct mem_ctl_info *mci, struct mce *m)
1931 struct mem_ctl_info *log_mci, *src_mci = NULL;
1938 if (!(m->status & MCI_STATUS_ADDRV)) {
1939 amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n");
1940 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
1943 "HW has no ERROR_ADDRESS available",
1948 sys_addr = get_error_address(m);
1949 error_address_to_page_and_offset(sys_addr, &page, &offset);
1952 * Find out which node the error address belongs to. This may be
1953 * different from the node that detected the error.
1955 src_mci = find_mc_by_sys_addr(mci, sys_addr);
1957 amd64_mc_err(mci, "ERROR ADDRESS (0x%lx) NOT mapped to a MC\n",
1958 (unsigned long)sys_addr);
1959 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
1962 "ERROR ADDRESS NOT mapped to a MC",
1969 csrow = sys_addr_to_csrow(log_mci, sys_addr);
1971 amd64_mc_err(mci, "ERROR_ADDRESS (0x%lx) NOT mapped to CS\n",
1972 (unsigned long)sys_addr);
1973 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
1976 "ERROR ADDRESS NOT mapped to CS",
1979 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
1986 static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
1989 u16 ec = EC(m->status);
1990 u8 xec = XEC(m->status, 0x1f);
1991 u8 ecc_type = (m->status >> 45) & 0x3;
1993 /* Bail early out if this was an 'observed' error */
1994 if (PP(ec) == NBSL_PP_OBS)
1997 /* Do only ECC errors */
1998 if (xec && xec != F10_NBSL_EXT_ERR_ECC)
2002 amd64_handle_ce(mci, m);
2003 else if (ecc_type == 1)
2004 amd64_handle_ue(mci, m);
2007 void amd64_decode_bus_error(int node_id, struct mce *m)
2009 __amd64_decode_bus_error(mcis[node_id], m);
2013 * Use pvt->F2 which contains the F2 CPU PCI device to get the related
2014 * F1 (AddrMap) and F3 (Misc) devices. Return negative value on error.
2016 static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id)
2018 /* Reserve the ADDRESS MAP Device */
2019 pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2);
2021 amd64_err("error address map device not found: "
2022 "vendor %x device 0x%x (broken BIOS?)\n",
2023 PCI_VENDOR_ID_AMD, f1_id);
2027 /* Reserve the MISC Device */
2028 pvt->F3 = pci_get_related_function(pvt->F2->vendor, f3_id, pvt->F2);
2030 pci_dev_put(pvt->F1);
2033 amd64_err("error F3 device not found: "
2034 "vendor %x device 0x%x (broken BIOS?)\n",
2035 PCI_VENDOR_ID_AMD, f3_id);
2039 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
2040 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
2041 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
2046 static void free_mc_sibling_devs(struct amd64_pvt *pvt)
2048 pci_dev_put(pvt->F1);
2049 pci_dev_put(pvt->F3);
2053 * Retrieve the hardware registers of the memory controller (this includes the
2054 * 'Address Map' and 'Misc' device regs)
2056 static void read_mc_regs(struct amd64_pvt *pvt)
2058 struct cpuinfo_x86 *c = &boot_cpu_data;
2064 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
2065 * those are Read-As-Zero
2067 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
2068 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
2070 /* check first whether TOP_MEM2 is enabled */
2071 rdmsrl(MSR_K8_SYSCFG, msr_val);
2072 if (msr_val & (1U << 21)) {
2073 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
2074 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
2076 edac_dbg(0, " TOP_MEM2 disabled\n");
2078 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
2080 read_dram_ctl_register(pvt);
2082 for (range = 0; range < DRAM_RANGES; range++) {
2085 /* read settings for this DRAM range */
2086 read_dram_base_limit_regs(pvt, range);
2088 rw = dram_rw(pvt, range);
2092 edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
2094 get_dram_base(pvt, range),
2095 get_dram_limit(pvt, range));
2097 edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
2098 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
2099 (rw & 0x1) ? "R" : "-",
2100 (rw & 0x2) ? "W" : "-",
2101 dram_intlv_sel(pvt, range),
2102 dram_dst_node(pvt, range));
2105 read_dct_base_mask(pvt);
2107 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
2108 amd64_read_dct_pci_cfg(pvt, DBAM0, &pvt->dbam0);
2110 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
2112 amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0);
2113 amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0);
2115 if (!dct_ganging_enabled(pvt)) {
2116 amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1);
2117 amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1);
2120 pvt->ecc_sym_sz = 4;
2122 if (c->x86 >= 0x10) {
2123 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
2124 amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
2126 /* F10h, revD and later can do x8 ECC too */
2127 if ((c->x86 > 0x10 || c->x86_model > 7) && tmp & BIT(25))
2128 pvt->ecc_sym_sz = 8;
2130 dump_misc_regs(pvt);
2134 * NOTE: CPU Revision Dependent code
2137 * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
2138 * k8 private pointer to -->
2139 * DRAM Bank Address mapping register
2141 * DCL register where dual_channel_active is
2143 * The DBAM register consists of 4 sets of 4 bits each definitions:
2146 * 0-3 CSROWs 0 and 1
2147 * 4-7 CSROWs 2 and 3
2148 * 8-11 CSROWs 4 and 5
2149 * 12-15 CSROWs 6 and 7
2151 * Values range from: 0 to 15
2152 * The meaning of the values depends on CPU revision and dual-channel state,
2153 * see relevant BKDG more info.
2155 * The memory controller provides for total of only 8 CSROWs in its current
2156 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
2157 * single channel or two (2) DIMMs in dual channel mode.
2159 * The following code logic collapses the various tables for CSROW based on CPU
2163 * The number of PAGE_SIZE pages on the specified CSROW number it
2167 static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
2169 u32 cs_mode, nr_pages;
2170 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
2173 * The math on this doesn't look right on the surface because x/2*4 can
2174 * be simplified to x*2 but this expression makes use of the fact that
2175 * it is integral math where 1/2=0. This intermediate value becomes the
2176 * number of bits to shift the DBAM register to extract the proper CSROW
2179 cs_mode = (dbam >> ((csrow_nr / 2) * 4)) & 0xF;
2181 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
2183 edac_dbg(0, " (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);
2184 edac_dbg(0, " nr_pages/channel= %u channel-count = %d\n",
2185 nr_pages, pvt->channel_count);
2191 * Initialize the array of csrow attribute instances, based on the values
2192 * from pci config hardware registers.
2194 static int init_csrows(struct mem_ctl_info *mci)
2196 struct csrow_info *csrow;
2197 struct dimm_info *dimm;
2198 struct amd64_pvt *pvt = mci->pvt_info;
2201 int i, j, empty = 1;
2202 enum mem_type mtype;
2203 enum edac_type edac_mode;
2206 amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
2210 edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
2211 pvt->mc_node_id, val,
2212 !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
2214 for_each_chip_select(i, 0, pvt) {
2215 csrow = mci->csrows[i];
2217 if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) {
2218 edac_dbg(1, "----CSROW %d VALID for MC node %d\n",
2219 i, pvt->mc_node_id);
2224 if (csrow_enabled(i, 0, pvt))
2225 nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
2226 if (csrow_enabled(i, 1, pvt))
2227 nr_pages += amd64_csrow_nr_pages(pvt, 1, i);
2229 get_cs_base_and_mask(pvt, i, 0, &base, &mask);
2230 /* 8 bytes of resolution */
2232 mtype = amd64_determine_memory_type(pvt, i);
2234 edac_dbg(1, " for MC node %d csrow %d:\n", pvt->mc_node_id, i);
2235 edac_dbg(1, " nr_pages: %u\n",
2236 nr_pages * pvt->channel_count);
2239 * determine whether CHIPKILL or JUST ECC or NO ECC is operating
2241 if (pvt->nbcfg & NBCFG_ECC_ENABLE)
2242 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) ?
2243 EDAC_S4ECD4ED : EDAC_SECDED;
2245 edac_mode = EDAC_NONE;
2247 for (j = 0; j < pvt->channel_count; j++) {
2248 dimm = csrow->channels[j]->dimm;
2249 dimm->mtype = mtype;
2250 dimm->edac_mode = edac_mode;
2251 dimm->nr_pages = nr_pages;
2258 /* get all cores on this DCT */
2259 static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, unsigned nid)
2263 for_each_online_cpu(cpu)
2264 if (amd_get_nb_id(cpu) == nid)
2265 cpumask_set_cpu(cpu, mask);
2268 /* check MCG_CTL on all the cpus on this node */
2269 static bool amd64_nb_mce_bank_enabled_on_node(unsigned nid)
2275 if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
2276 amd64_warn("%s: Error allocating mask\n", __func__);
2280 get_cpus_on_this_dct_cpumask(mask, nid);
2282 rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs);
2284 for_each_cpu(cpu, mask) {
2285 struct msr *reg = per_cpu_ptr(msrs, cpu);
2286 nbe = reg->l & MSR_MCGCTL_NBE;
2288 edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
2290 (nbe ? "enabled" : "disabled"));
2298 free_cpumask_var(mask);
2302 static int toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on)
2304 cpumask_var_t cmask;
2307 if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
2308 amd64_warn("%s: error allocating mask\n", __func__);
2312 get_cpus_on_this_dct_cpumask(cmask, nid);
2314 rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
2316 for_each_cpu(cpu, cmask) {
2318 struct msr *reg = per_cpu_ptr(msrs, cpu);
2321 if (reg->l & MSR_MCGCTL_NBE)
2322 s->flags.nb_mce_enable = 1;
2324 reg->l |= MSR_MCGCTL_NBE;
2327 * Turn off NB MCE reporting only when it was off before
2329 if (!s->flags.nb_mce_enable)
2330 reg->l &= ~MSR_MCGCTL_NBE;
2333 wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
2335 free_cpumask_var(cmask);
2340 static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
2344 u32 value, mask = 0x3; /* UECC/CECC enable */
2346 if (toggle_ecc_err_reporting(s, nid, ON)) {
2347 amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
2351 amd64_read_pci_cfg(F3, NBCTL, &value);
2353 s->old_nbctl = value & mask;
2354 s->nbctl_valid = true;
2357 amd64_write_pci_cfg(F3, NBCTL, value);
2359 amd64_read_pci_cfg(F3, NBCFG, &value);
2361 edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
2362 nid, value, !!(value & NBCFG_ECC_ENABLE));
2364 if (!(value & NBCFG_ECC_ENABLE)) {
2365 amd64_warn("DRAM ECC disabled on this node, enabling...\n");
2367 s->flags.nb_ecc_prev = 0;
2369 /* Attempt to turn on DRAM ECC Enable */
2370 value |= NBCFG_ECC_ENABLE;
2371 amd64_write_pci_cfg(F3, NBCFG, value);
2373 amd64_read_pci_cfg(F3, NBCFG, &value);
2375 if (!(value & NBCFG_ECC_ENABLE)) {
2376 amd64_warn("Hardware rejected DRAM ECC enable,"
2377 "check memory DIMM configuration.\n");
2380 amd64_info("Hardware accepted DRAM ECC Enable\n");
2383 s->flags.nb_ecc_prev = 1;
2386 edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
2387 nid, value, !!(value & NBCFG_ECC_ENABLE));
2392 static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid,
2395 u32 value, mask = 0x3; /* UECC/CECC enable */
2398 if (!s->nbctl_valid)
2401 amd64_read_pci_cfg(F3, NBCTL, &value);
2403 value |= s->old_nbctl;
2405 amd64_write_pci_cfg(F3, NBCTL, value);
2407 /* restore previous BIOS DRAM ECC "off" setting we force-enabled */
2408 if (!s->flags.nb_ecc_prev) {
2409 amd64_read_pci_cfg(F3, NBCFG, &value);
2410 value &= ~NBCFG_ECC_ENABLE;
2411 amd64_write_pci_cfg(F3, NBCFG, value);
2414 /* restore the NB Enable MCGCTL bit */
2415 if (toggle_ecc_err_reporting(s, nid, OFF))
2416 amd64_warn("Error restoring NB MCGCTL settings!\n");
2420 * EDAC requires that the BIOS have ECC enabled before
2421 * taking over the processing of ECC errors. A command line
2422 * option allows to force-enable hardware ECC later in
2423 * enable_ecc_error_reporting().
2425 static const char *ecc_msg =
2426 "ECC disabled in the BIOS or no ECC capability, module will not load.\n"
2427 " Either enable ECC checking or force module loading by setting "
2428 "'ecc_enable_override'.\n"
2429 " (Note that use of the override may cause unknown side effects.)\n";
2431 static bool ecc_enabled(struct pci_dev *F3, u8 nid)
2435 bool nb_mce_en = false;
2437 amd64_read_pci_cfg(F3, NBCFG, &value);
2439 ecc_en = !!(value & NBCFG_ECC_ENABLE);
2440 amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled"));
2442 nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid);
2444 amd64_notice("NB MCE bank disabled, set MSR "
2445 "0x%08x[4] on node %d to enable.\n",
2446 MSR_IA32_MCG_CTL, nid);
2448 if (!ecc_en || !nb_mce_en) {
2449 amd64_notice("%s", ecc_msg);
2455 static int set_mc_sysfs_attrs(struct mem_ctl_info *mci)
2459 rc = amd64_create_sysfs_dbg_files(mci);
2463 if (boot_cpu_data.x86 >= 0x10) {
2464 rc = amd64_create_sysfs_inject_files(mci);
2472 static void del_mc_sysfs_attrs(struct mem_ctl_info *mci)
2474 amd64_remove_sysfs_dbg_files(mci);
2476 if (boot_cpu_data.x86 >= 0x10)
2477 amd64_remove_sysfs_inject_files(mci);
2480 static void setup_mci_misc_attrs(struct mem_ctl_info *mci,
2481 struct amd64_family_type *fam)
2483 struct amd64_pvt *pvt = mci->pvt_info;
2485 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
2486 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2488 if (pvt->nbcap & NBCAP_SECDED)
2489 mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
2491 if (pvt->nbcap & NBCAP_CHIPKILL)
2492 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
2494 mci->edac_cap = amd64_determine_edac_cap(pvt);
2495 mci->mod_name = EDAC_MOD_STR;
2496 mci->mod_ver = EDAC_AMD64_VERSION;
2497 mci->ctl_name = fam->ctl_name;
2498 mci->dev_name = pci_name(pvt->F2);
2499 mci->ctl_page_to_phys = NULL;
2501 /* memory scrubber interface */
2502 mci->set_sdram_scrub_rate = amd64_set_scrub_rate;
2503 mci->get_sdram_scrub_rate = amd64_get_scrub_rate;
2507 * returns a pointer to the family descriptor on success, NULL otherwise.
2509 static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt)
2511 u8 fam = boot_cpu_data.x86;
2512 struct amd64_family_type *fam_type = NULL;
2516 fam_type = &amd64_family_types[K8_CPUS];
2517 pvt->ops = &amd64_family_types[K8_CPUS].ops;
2521 fam_type = &amd64_family_types[F10_CPUS];
2522 pvt->ops = &amd64_family_types[F10_CPUS].ops;
2526 fam_type = &amd64_family_types[F15_CPUS];
2527 pvt->ops = &amd64_family_types[F15_CPUS].ops;
2531 amd64_err("Unsupported family!\n");
2535 pvt->ext_model = boot_cpu_data.x86_model >> 4;
2537 amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name,
2539 (pvt->ext_model >= K8_REV_F ? "revF or later "
2540 : "revE or earlier ")
2541 : ""), pvt->mc_node_id);
2545 static int amd64_init_one_instance(struct pci_dev *F2)
2547 struct amd64_pvt *pvt = NULL;
2548 struct amd64_family_type *fam_type = NULL;
2549 struct mem_ctl_info *mci = NULL;
2550 struct edac_mc_layer layers[2];
2552 u8 nid = get_node_id(F2);
2555 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
2559 pvt->mc_node_id = nid;
2563 fam_type = amd64_per_family_init(pvt);
2568 err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id);
2575 * We need to determine how many memory channels there are. Then use
2576 * that information for calculating the size of the dynamic instance
2577 * tables in the 'mci' structure.
2580 pvt->channel_count = pvt->ops->early_channel_count(pvt);
2581 if (pvt->channel_count < 0)
2585 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
2586 layers[0].size = pvt->csels[0].b_cnt;
2587 layers[0].is_virt_csrow = true;
2588 layers[1].type = EDAC_MC_LAYER_CHANNEL;
2589 layers[1].size = pvt->channel_count;
2590 layers[1].is_virt_csrow = false;
2591 mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0);
2595 mci->pvt_info = pvt;
2596 mci->pdev = &pvt->F2->dev;
2598 setup_mci_misc_attrs(mci, fam_type);
2600 if (init_csrows(mci))
2601 mci->edac_cap = EDAC_FLAG_NONE;
2604 if (edac_mc_add_mc(mci)) {
2605 edac_dbg(1, "failed edac_mc_add_mc()\n");
2608 if (set_mc_sysfs_attrs(mci)) {
2609 edac_dbg(1, "failed edac_mc_add_mc()\n");
2613 /* register stuff with EDAC MCE */
2614 if (report_gart_errors)
2615 amd_report_gart_errors(true);
2617 amd_register_ecc_decoder(amd64_decode_bus_error);
2621 atomic_inc(&drv_instances);
2626 edac_mc_del_mc(mci->pdev);
2631 free_mc_sibling_devs(pvt);
2640 static int __devinit amd64_probe_one_instance(struct pci_dev *pdev,
2641 const struct pci_device_id *mc_type)
2643 u8 nid = get_node_id(pdev);
2644 struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
2645 struct ecc_settings *s;
2648 ret = pci_enable_device(pdev);
2650 edac_dbg(0, "ret=%d\n", ret);
2655 s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
2661 if (!ecc_enabled(F3, nid)) {
2664 if (!ecc_enable_override)
2667 amd64_warn("Forcing ECC on!\n");
2669 if (!enable_ecc_error_reporting(s, nid, F3))
2673 ret = amd64_init_one_instance(pdev);
2675 amd64_err("Error probing instance: %d\n", nid);
2676 restore_ecc_error_reporting(s, nid, F3);
2683 ecc_stngs[nid] = NULL;
2689 static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
2691 struct mem_ctl_info *mci;
2692 struct amd64_pvt *pvt;
2693 u8 nid = get_node_id(pdev);
2694 struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
2695 struct ecc_settings *s = ecc_stngs[nid];
2697 mci = find_mci_by_dev(&pdev->dev);
2698 del_mc_sysfs_attrs(mci);
2699 /* Remove from EDAC CORE tracking list */
2700 mci = edac_mc_del_mc(&pdev->dev);
2704 pvt = mci->pvt_info;
2706 restore_ecc_error_reporting(s, nid, F3);
2708 free_mc_sibling_devs(pvt);
2710 /* unregister from EDAC MCE */
2711 amd_report_gart_errors(false);
2712 amd_unregister_ecc_decoder(amd64_decode_bus_error);
2714 kfree(ecc_stngs[nid]);
2715 ecc_stngs[nid] = NULL;
2717 /* Free the EDAC CORE resources */
2718 mci->pvt_info = NULL;
2726 * This table is part of the interface for loading drivers for PCI devices. The
2727 * PCI core identifies what devices are on a system during boot, and then
2728 * inquiry this table to see if this driver is for a given device found.
2730 static DEFINE_PCI_DEVICE_TABLE(amd64_pci_table) = {
2732 .vendor = PCI_VENDOR_ID_AMD,
2733 .device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
2734 .subvendor = PCI_ANY_ID,
2735 .subdevice = PCI_ANY_ID,
2740 .vendor = PCI_VENDOR_ID_AMD,
2741 .device = PCI_DEVICE_ID_AMD_10H_NB_DRAM,
2742 .subvendor = PCI_ANY_ID,
2743 .subdevice = PCI_ANY_ID,
2748 .vendor = PCI_VENDOR_ID_AMD,
2749 .device = PCI_DEVICE_ID_AMD_15H_NB_F2,
2750 .subvendor = PCI_ANY_ID,
2751 .subdevice = PCI_ANY_ID,
2758 MODULE_DEVICE_TABLE(pci, amd64_pci_table);
2760 static struct pci_driver amd64_pci_driver = {
2761 .name = EDAC_MOD_STR,
2762 .probe = amd64_probe_one_instance,
2763 .remove = __devexit_p(amd64_remove_one_instance),
2764 .id_table = amd64_pci_table,
2767 static void setup_pci_device(void)
2769 struct mem_ctl_info *mci;
2770 struct amd64_pvt *pvt;
2778 pvt = mci->pvt_info;
2780 edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
2782 if (!amd64_ctl_pci) {
2783 pr_warning("%s(): Unable to create PCI control\n",
2786 pr_warning("%s(): PCI error report via EDAC not set\n",
2792 static int __init amd64_edac_init(void)
2796 printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION);
2800 if (amd_cache_northbridges() < 0)
2804 mcis = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL);
2805 ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL);
2806 if (!(mcis && ecc_stngs))
2809 msrs = msrs_alloc();
2813 err = pci_register_driver(&amd64_pci_driver);
2818 if (!atomic_read(&drv_instances))
2819 goto err_no_instances;
2825 pci_unregister_driver(&amd64_pci_driver);
2842 static void __exit amd64_edac_exit(void)
2845 edac_pci_release_generic_ctl(amd64_ctl_pci);
2847 pci_unregister_driver(&amd64_pci_driver);
2859 module_init(amd64_edac_init);
2860 module_exit(amd64_edac_exit);
2862 MODULE_LICENSE("GPL");
2863 MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
2864 "Dave Peterson, Thayne Harbaugh");
2865 MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
2866 EDAC_AMD64_VERSION);
2868 module_param(edac_op_state, int, 0444);
2869 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");