2 * AMD 76x Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
11 * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
16 #include <linux/config.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <linux/pci_ids.h>
23 #include <linux/slab.h>
28 #define amd76x_printk(level, fmt, arg...) \
29 edac_printk(level, "amd76x", fmt, ##arg)
32 #define amd76x_mc_printk(mci, level, fmt, arg...) \
33 edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
36 #define AMD76X_NR_CSROWS 8
37 #define AMD76X_NR_CHANS 1
38 #define AMD76X_NR_DIMMS 4
41 /* AMD 76x register addresses - device 0 function 0 - PCI bridge */
42 #define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
45 * 15:14 SERR enabled: x1=ue 1x=ce
47 * 12 diag: disabled, enabled
48 * 11:10 mode: dis, EC, ECC, ECC+scrub
49 * 9:8 status: x1=ue 1x=ce
53 #define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
55 * 31:26 clock disable 5 - 0
58 * 23 mode register service
59 * 22:21 suspend to RAM
60 * 20 burst refresh enable
63 * 17:16 cycles-per-refresh
65 * 7:0 x4 mode enable 7 - 0
67 #define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
69 * 31:23 chip-select base
71 * 15:7 chip-select mask
74 * 0 chip-select enable
78 struct amd76x_error_info {
89 struct amd76x_dev_info {
94 static const struct amd76x_dev_info amd76x_devs[] = {
95 [AMD761] = {.ctl_name = "AMD761"},
96 [AMD762] = {.ctl_name = "AMD762"},
101 * amd76x_get_error_info - fetch error information
102 * @mci: Memory controller
103 * @info: Info to fill in
105 * Fetch and store the AMD76x ECC status. Clear pending status
106 * on the chip so that further errors will be reported
109 static void amd76x_get_error_info (struct mem_ctl_info *mci,
110 struct amd76x_error_info *info)
112 pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS,
113 &info->ecc_mode_status);
115 if (info->ecc_mode_status & BIT(8))
116 pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
117 (u32) BIT(8), (u32) BIT(8));
119 if (info->ecc_mode_status & BIT(9))
120 pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
121 (u32) BIT(9), (u32) BIT(9));
126 * amd76x_process_error_info - Error check
127 * @mci: Memory controller
128 * @info: Previously fetched information from chip
129 * @handle_errors: 1 if we should do recovery
131 * Process the chip state and decide if an error has occurred.
132 * A return of 1 indicates an error. Also if handle_errors is true
133 * then attempt to handle and clean up after the error
136 static int amd76x_process_error_info (struct mem_ctl_info *mci,
137 struct amd76x_error_info *info, int handle_errors)
145 * Check for an uncorrectable error
147 if (info->ecc_mode_status & BIT(8)) {
151 row = (info->ecc_mode_status >> 4) & 0xf;
152 edac_mc_handle_ue(mci,
153 mci->csrows[row].first_page, 0, row,
159 * Check for a correctable error
161 if (info->ecc_mode_status & BIT(9)) {
165 row = info->ecc_mode_status & 0xf;
166 edac_mc_handle_ce(mci,
167 mci->csrows[row].first_page, 0, 0, row, 0,
175 * amd76x_check - Poll the controller
176 * @mci: Memory controller
178 * Called by the poll handlers this function reads the status
179 * from the controller and checks for errors.
182 static void amd76x_check(struct mem_ctl_info *mci)
184 struct amd76x_error_info info;
185 debugf3("%s()\n", __func__);
186 amd76x_get_error_info(mci, &info);
187 amd76x_process_error_info(mci, &info, 1);
192 * amd76x_probe1 - Perform set up for detected device
193 * @pdev; PCI device detected
194 * @dev_idx: Device type index
196 * We have found an AMD76x and now need to set up the memory
197 * controller status reporting. We configure and set up the
198 * memory controller reporting and claim the device.
201 static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
205 struct mem_ctl_info *mci = NULL;
206 enum edac_type ems_modes[] = {
214 struct amd76x_error_info discard;
216 debugf0("%s()\n", __func__);
218 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
219 ems_mode = (ems >> 10) & 0x3;
221 mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS);
228 debugf0("%s(): mci = %p\n", __func__, mci);
231 mci->mtype_cap = MEM_FLAG_RDDR;
233 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
234 mci->edac_cap = ems_mode ?
235 (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
237 mci->mod_name = EDAC_MOD_STR;
238 mci->mod_ver = "$Revision: 1.4.2.5 $";
239 mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
240 mci->edac_check = amd76x_check;
241 mci->ctl_page_to_phys = NULL;
243 for (index = 0; index < mci->nr_csrows; index++) {
244 struct csrow_info *csrow = &mci->csrows[index];
250 /* find the DRAM Chip Select Base address and mask */
251 pci_read_config_dword(mci->pdev,
252 AMD76X_MEM_BASE_ADDR + (index * 4),
258 mba_base = mba & 0xff800000UL;
259 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
261 pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS,
264 csrow->first_page = mba_base >> PAGE_SHIFT;
265 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
266 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
267 csrow->page_mask = mba_mask >> PAGE_SHIFT;
268 csrow->grain = csrow->nr_pages << PAGE_SHIFT;
269 csrow->mtype = MEM_RDDR;
270 csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
271 csrow->edac_mode = ems_modes[ems_mode];
274 amd76x_get_error_info(mci, &discard); /* clear counters */
276 if (edac_mc_add_mc(mci)) {
277 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
281 /* get this far and it's successful */
282 debugf3("%s(): success\n", __func__);
291 /* returns count (>= 0), or negative on error */
292 static int __devinit amd76x_init_one(struct pci_dev *pdev,
293 const struct pci_device_id *ent)
295 debugf0("%s()\n", __func__);
297 /* don't need to call pci_device_enable() */
298 return amd76x_probe1(pdev, ent->driver_data);
303 * amd76x_remove_one - driver shutdown
304 * @pdev: PCI device being handed back
306 * Called when the driver is unloaded. Find the matching mci
307 * structure for the device then delete the mci and free the
311 static void __devexit amd76x_remove_one(struct pci_dev *pdev)
313 struct mem_ctl_info *mci;
315 debugf0("%s()\n", __func__);
317 if ((mci = edac_mc_del_mc(pdev)) == NULL)
324 static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
325 {PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
327 {PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
329 {0,} /* 0 terminated list. */
332 MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
335 static struct pci_driver amd76x_driver = {
336 .name = EDAC_MOD_STR,
337 .probe = amd76x_init_one,
338 .remove = __devexit_p(amd76x_remove_one),
339 .id_table = amd76x_pci_tbl,
342 static int __init amd76x_init(void)
344 return pci_register_driver(&amd76x_driver);
347 static void __exit amd76x_exit(void)
349 pci_unregister_driver(&amd76x_driver);
352 module_init(amd76x_init);
353 module_exit(amd76x_exit);
355 MODULE_LICENSE("GPL");
356 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
357 MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");