2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Implement support for the e7520, E7525, e7320 and i3100 memory controllers.
10 * http://www.intel.in/content/www/in/en/chipsets/e7525-memory-controller-hub-datasheet.html
11 * ftp://download.intel.com/design/intarch/datashts/31345803.pdf
13 * Written by Tom Zimmerman
16 * Thayne Harbaugh at realmsys.com (?)
17 * Wang Zhenyu at intel.com
18 * Dave Jiang at mvista.com
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/pci.h>
25 #include <linux/pci_ids.h>
26 #include <linux/edac.h>
27 #include "edac_core.h"
29 #define E752X_REVISION " Ver: 2.0.2"
30 #define EDAC_MOD_STR "e752x_edac"
32 static int report_non_memory_errors;
33 static int force_function_unhide;
34 static int sysbus_parity = -1;
36 static struct edac_pci_ctl_info *e752x_pci;
38 #define e752x_printk(level, fmt, arg...) \
39 edac_printk(level, "e752x", fmt, ##arg)
41 #define e752x_mc_printk(mci, level, fmt, arg...) \
42 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
44 #ifndef PCI_DEVICE_ID_INTEL_7520_0
45 #define PCI_DEVICE_ID_INTEL_7520_0 0x3590
46 #endif /* PCI_DEVICE_ID_INTEL_7520_0 */
48 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
49 #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
50 #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
52 #ifndef PCI_DEVICE_ID_INTEL_7525_0
53 #define PCI_DEVICE_ID_INTEL_7525_0 0x359E
54 #endif /* PCI_DEVICE_ID_INTEL_7525_0 */
56 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
57 #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
58 #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
60 #ifndef PCI_DEVICE_ID_INTEL_7320_0
61 #define PCI_DEVICE_ID_INTEL_7320_0 0x3592
62 #endif /* PCI_DEVICE_ID_INTEL_7320_0 */
64 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
65 #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
66 #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
68 #ifndef PCI_DEVICE_ID_INTEL_3100_0
69 #define PCI_DEVICE_ID_INTEL_3100_0 0x35B0
70 #endif /* PCI_DEVICE_ID_INTEL_3100_0 */
72 #ifndef PCI_DEVICE_ID_INTEL_3100_1_ERR
73 #define PCI_DEVICE_ID_INTEL_3100_1_ERR 0x35B1
74 #endif /* PCI_DEVICE_ID_INTEL_3100_1_ERR */
76 #define E752X_NR_CSROWS 8 /* number of csrows */
78 /* E752X register addresses - device 0 function 0 */
79 #define E752X_MCHSCRB 0x52 /* Memory Scrub register (16b) */
81 * 6:5 Scrub Completion Count
82 * 3:2 Scrub Rate (i3100 only)
84 * 1:0 Scrub Mode enable
87 #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
88 #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
90 * 31:30 Device width row 7
91 * 01=x8 10=x4 11=x8 DDR2
92 * 27:26 Device width row 6
93 * 23:22 Device width row 5
94 * 19:20 Device width row 4
95 * 15:14 Device width row 3
96 * 11:10 Device width row 2
97 * 7:6 Device width row 1
98 * 3:2 Device width row 0
100 #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
101 /* FIXME:IS THIS RIGHT? */
103 * 22 Number channels 0=1,1=2
104 * 19:18 DRB Granularity 32/64MB
106 #define E752X_DRM 0x80 /* Dimm mapping register */
107 #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
109 * 14:12 1 single A, 2 single B, 3 dual
111 #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
112 #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
113 #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
114 #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
116 /* E752X register addresses - device 0 function 1 */
117 #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
118 #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
119 #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
120 #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
121 #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
122 #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
123 #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
124 #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
125 #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
126 #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
127 #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
128 #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
129 #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
130 #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI cmd reg (8b) */
131 #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
132 #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
133 #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
134 #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
135 #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
136 #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
137 /* error address register (32b) */
140 * 30:2 CE address (64 byte block 34:6
144 #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
145 /* error address register (32b) */
148 * 30:2 CE address (64 byte block 34:6)
152 #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
153 /* error address register (32b) */
156 * 30:2 CE address (64 byte block 34:6)
160 #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM 1st uncorrectable scrub mem */
161 /* error address register (32b) */
164 * 30:2 CE address (64 byte block 34:6
168 #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
169 /* error syndrome register (16b) */
170 #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
171 /* error syndrome register (16b) */
172 #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
174 /* 3100 IMCH specific register addresses - device 0 function 1 */
175 #define I3100_NSI_FERR 0x48 /* NSI first error reg (32b) */
176 #define I3100_NSI_NERR 0x4C /* NSI next error reg (32b) */
177 #define I3100_NSI_SMICMD 0x54 /* NSI SMI command register (32b) */
178 #define I3100_NSI_EMASK 0x90 /* NSI error mask register (32b) */
180 /* ICH5R register addresses - device 30 function 0 */
181 #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
182 #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
183 #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
193 * Those chips Support single-rank and dual-rank memories only.
195 * On e752x chips, the odd rows are present only on dual-rank memories.
196 * Dividing the rank by two will provide the dimm#
198 * i3100 MC has a different mapping: it supports only 4 ranks.
200 * The mapping is (from 1 to n):
201 * slot single-ranked double-ranked
202 * dimm #1 -> rank #4 NA
203 * dimm #2 -> rank #3 NA
204 * dimm #3 -> rank #2 Ranks 2 and 3
205 * dimm #4 -> rank $1 Ranks 1 and 4
207 * FIXME: The current mapping for i3100 considers that it supports up to 8
208 * ranks/chanel, but datasheet says that the MC supports only 4 ranks.
212 struct pci_dev *bridge_ck;
213 struct pci_dev *dev_d0f0;
214 struct pci_dev *dev_d0f1;
221 const struct e752x_dev_info *dev_info;
224 struct e752x_dev_info {
227 const char *ctl_name;
230 struct e752x_error_info {
233 u32 nsi_ferr; /* 3100 only */
234 u32 nsi_nerr; /* 3100 only */
235 u8 hi_ferr; /* all but 3100 */
236 u8 hi_nerr; /* all but 3100 */
245 u16 dram_sec1_syndrome;
246 u16 dram_sec2_syndrome;
252 static const struct e752x_dev_info e752x_devs[] = {
254 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
255 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
256 .ctl_name = "E7520"},
258 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
259 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
260 .ctl_name = "E7525"},
262 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
263 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
264 .ctl_name = "E7320"},
266 .err_dev = PCI_DEVICE_ID_INTEL_3100_1_ERR,
267 .ctl_dev = PCI_DEVICE_ID_INTEL_3100_0,
271 /* Valid scrub rates for the e752x/3100 hardware memory scrubber. We
272 * map the scrubbing bandwidth to a hardware register value. The 'set'
273 * operation finds the 'matching or higher value'. Note that scrubbing
274 * on the e752x can only be enabled/disabled. The 3100 supports
275 * a normal and fast mode.
278 #define SDRATE_EOT 0xFFFFFFFF
281 u32 bandwidth; /* bandwidth consumed by scrubbing in bytes/sec */
282 u16 scrubval; /* register value for scrub rate */
285 /* Rate below assumes same performance as i3100 using PC3200 DDR2 in
286 * normal mode. e752x bridges don't support choosing normal or fast mode,
287 * so the scrubbing bandwidth value isn't all that important - scrubbing is
290 static const struct scrubrate scrubrates_e752x[] = {
291 {0, 0x00}, /* Scrubbing Off */
292 {500000, 0x02}, /* Scrubbing On */
293 {SDRATE_EOT, 0x00} /* End of Table */
296 /* Fast mode: 2 GByte PC3200 DDR2 scrubbed in 33s = 63161283 bytes/s
297 * Normal mode: 125 (32000 / 256) times slower than fast mode.
299 static const struct scrubrate scrubrates_i3100[] = {
300 {0, 0x00}, /* Scrubbing Off */
301 {500000, 0x0a}, /* Normal mode - 32k clocks */
302 {62500000, 0x06}, /* Fast mode - 256 clocks */
303 {SDRATE_EOT, 0x00} /* End of Table */
306 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
310 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
312 debugf3("%s()\n", __func__);
314 if (page < pvt->tolm)
317 if ((page >= 0x100000) && (page < pvt->remapbase))
320 remap = (page - pvt->tolm) + pvt->remapbase;
322 if (remap < pvt->remaplimit)
325 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
326 return pvt->tolm - 1;
329 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
330 u32 sec1_add, u16 sec1_syndrome)
336 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
338 debugf3("%s()\n", __func__);
340 /* convert the addr to 4k page */
341 page = sec1_add >> (PAGE_SHIFT - 4);
343 /* FIXME - check for -1 */
344 if (pvt->mc_symmetric) {
345 /* chip select are bits 14 & 13 */
346 row = ((page >> 1) & 3);
347 e752x_printk(KERN_WARNING,
348 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
349 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
350 pvt->map[4], pvt->map[5], pvt->map[6],
353 /* test for channel remapping */
354 for (i = 0; i < 8; i++) {
355 if (pvt->map[i] == row)
359 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
364 e752x_mc_printk(mci, KERN_WARNING,
365 "row %d not found in remap table\n",
368 row = edac_mc_find_csrow_by_page(mci, page);
370 /* 0 = channel A, 1 = channel B */
371 channel = !(error_one & 1);
373 /* e752x mc reads 34:6 of the DRAM linear address */
374 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
375 page, offset_in_page(sec1_add << 4), sec1_syndrome,
377 "e752x CE", "", NULL);
380 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
381 u32 sec1_add, u16 sec1_syndrome, int *error_found,
387 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
390 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
391 u32 ded_add, u32 scrb_add)
393 u32 error_2b, block_page;
395 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
397 debugf3("%s()\n", __func__);
399 if (error_one & 0x0202) {
402 /* convert to 4k address */
403 block_page = error_2b >> (PAGE_SHIFT - 4);
405 row = pvt->mc_symmetric ?
406 /* chip select are bits 14 & 13 */
407 ((block_page >> 1) & 3) :
408 edac_mc_find_csrow_by_page(mci, block_page);
410 /* e752x mc reads 34:6 of the DRAM linear address */
411 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
413 offset_in_page(error_2b << 4), 0,
415 "e752x UE from Read", "", NULL);
418 if (error_one & 0x0404) {
421 /* convert to 4k address */
422 block_page = error_2b >> (PAGE_SHIFT - 4);
424 row = pvt->mc_symmetric ?
425 /* chip select are bits 14 & 13 */
426 ((block_page >> 1) & 3) :
427 edac_mc_find_csrow_by_page(mci, block_page);
429 /* e752x mc reads 34:6 of the DRAM linear address */
430 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
432 offset_in_page(error_2b << 4), 0,
434 "e752x UE from Scruber", "", NULL);
438 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
439 u32 ded_add, u32 scrb_add, int *error_found,
445 do_process_ue(mci, error_one, ded_add, scrb_add);
448 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
449 int *error_found, int handle_error)
456 debugf3("%s()\n", __func__);
457 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
459 "e752x UE log memory write", "", NULL);
462 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
467 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
469 error_1b = retry_add;
470 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
472 /* chip select are bits 14 & 13 */
473 row = pvt->mc_symmetric ? ((page >> 1) & 3) :
474 edac_mc_find_csrow_by_page(mci, page);
476 e752x_mc_printk(mci, KERN_WARNING,
477 "CE page 0x%lx, row %d : Memory read retry\n",
478 (long unsigned int)page, row);
481 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
482 u32 retry_add, int *error_found,
488 do_process_ded_retry(mci, error, retry_add);
491 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
492 int *error_found, int handle_error)
497 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
500 static char *global_message[11] = {
508 "HUB or NS Interface",
510 "DRAM Controller", /* 9th entry */
516 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
518 static void do_global_error(int fatal, u32 errors)
522 for (i = 0; i < 11; i++) {
523 if (errors & (1 << i)) {
524 /* If the error is from DRAM Controller OR
525 * we are to report ALL errors, then
528 if ((i == DRAM_ENTRY) || report_non_memory_errors)
529 e752x_printk(KERN_WARNING, "%sError %s\n",
530 fatal_message[fatal],
536 static inline void global_error(int fatal, u32 errors, int *error_found,
542 do_global_error(fatal, errors);
545 static char *hub_message[7] = {
546 "HI Address or Command Parity", "HI Illegal Access",
547 "HI Internal Parity", "Out of Range Access",
548 "HI Data Parity", "Enhanced Config Access",
549 "Hub Interface Target Abort"
552 static void do_hub_error(int fatal, u8 errors)
556 for (i = 0; i < 7; i++) {
557 if (errors & (1 << i))
558 e752x_printk(KERN_WARNING, "%sError %s\n",
559 fatal_message[fatal], hub_message[i]);
563 static inline void hub_error(int fatal, u8 errors, int *error_found,
569 do_hub_error(fatal, errors);
572 #define NSI_FATAL_MASK 0x0c080081
573 #define NSI_NON_FATAL_MASK 0x23a0ba64
574 #define NSI_ERR_MASK (NSI_FATAL_MASK | NSI_NON_FATAL_MASK)
576 static char *nsi_message[30] = {
577 "NSI Link Down", /* NSI_FERR/NSI_NERR bit 0, fatal error */
579 "NSI Parity Error", /* bit 2, non-fatal */
582 "Correctable Error Message", /* bit 5, non-fatal */
583 "Non-Fatal Error Message", /* bit 6, non-fatal */
584 "Fatal Error Message", /* bit 7, fatal */
586 "Receiver Error", /* bit 9, non-fatal */
588 "Bad TLP", /* bit 11, non-fatal */
589 "Bad DLLP", /* bit 12, non-fatal */
590 "REPLAY_NUM Rollover", /* bit 13, non-fatal */
592 "Replay Timer Timeout", /* bit 15, non-fatal */
596 "Data Link Protocol Error", /* bit 19, fatal */
598 "Poisoned TLP", /* bit 21, non-fatal */
600 "Completion Timeout", /* bit 23, non-fatal */
601 "Completer Abort", /* bit 24, non-fatal */
602 "Unexpected Completion", /* bit 25, non-fatal */
603 "Receiver Overflow", /* bit 26, fatal */
604 "Malformed TLP", /* bit 27, fatal */
606 "Unsupported Request" /* bit 29, non-fatal */
609 static void do_nsi_error(int fatal, u32 errors)
613 for (i = 0; i < 30; i++) {
614 if (errors & (1 << i))
615 printk(KERN_WARNING "%sError %s\n",
616 fatal_message[fatal], nsi_message[i]);
620 static inline void nsi_error(int fatal, u32 errors, int *error_found,
626 do_nsi_error(fatal, errors);
629 static char *membuf_message[4] = {
630 "Internal PMWB to DRAM parity",
631 "Internal PMWB to System Bus Parity",
632 "Internal System Bus or IO to PMWB Parity",
633 "Internal DRAM to PMWB Parity"
636 static void do_membuf_error(u8 errors)
640 for (i = 0; i < 4; i++) {
641 if (errors & (1 << i))
642 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
647 static inline void membuf_error(u8 errors, int *error_found, int handle_error)
652 do_membuf_error(errors);
655 static char *sysbus_message[10] = {
656 "Addr or Request Parity",
657 "Data Strobe Glitch",
658 "Addr Strobe Glitch",
661 "Non DRAM Lock Error",
664 "IO Subsystem Parity"
667 static void do_sysbus_error(int fatal, u32 errors)
671 for (i = 0; i < 10; i++) {
672 if (errors & (1 << i))
673 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
674 fatal_message[fatal], sysbus_message[i]);
678 static inline void sysbus_error(int fatal, u32 errors, int *error_found,
684 do_sysbus_error(fatal, errors);
687 static void e752x_check_hub_interface(struct e752x_error_info *info,
688 int *error_found, int handle_error)
692 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
694 stat8 = info->hi_ferr;
696 if (stat8 & 0x7f) { /* Error, so process */
700 hub_error(1, stat8 & 0x2b, error_found, handle_error);
703 hub_error(0, stat8 & 0x54, error_found, handle_error);
705 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
707 stat8 = info->hi_nerr;
709 if (stat8 & 0x7f) { /* Error, so process */
713 hub_error(1, stat8 & 0x2b, error_found, handle_error);
716 hub_error(0, stat8 & 0x54, error_found, handle_error);
720 static void e752x_check_ns_interface(struct e752x_error_info *info,
721 int *error_found, int handle_error)
725 stat32 = info->nsi_ferr;
726 if (stat32 & NSI_ERR_MASK) { /* Error, so process */
727 if (stat32 & NSI_FATAL_MASK) /* check for fatal errors */
728 nsi_error(1, stat32 & NSI_FATAL_MASK, error_found,
730 if (stat32 & NSI_NON_FATAL_MASK) /* check for non-fatal ones */
731 nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found,
734 stat32 = info->nsi_nerr;
735 if (stat32 & NSI_ERR_MASK) {
736 if (stat32 & NSI_FATAL_MASK)
737 nsi_error(1, stat32 & NSI_FATAL_MASK, error_found,
739 if (stat32 & NSI_NON_FATAL_MASK)
740 nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found,
745 static void e752x_check_sysbus(struct e752x_error_info *info,
746 int *error_found, int handle_error)
750 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
751 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
754 return; /* no errors */
756 error32 = (stat32 >> 16) & 0x3ff;
757 stat32 = stat32 & 0x3ff;
760 sysbus_error(1, stat32 & 0x087, error_found, handle_error);
763 sysbus_error(0, stat32 & 0x378, error_found, handle_error);
766 sysbus_error(1, error32 & 0x087, error_found, handle_error);
769 sysbus_error(0, error32 & 0x378, error_found, handle_error);
772 static void e752x_check_membuf(struct e752x_error_info *info,
773 int *error_found, int handle_error)
777 stat8 = info->buf_ferr;
779 if (stat8 & 0x0f) { /* Error, so process */
781 membuf_error(stat8, error_found, handle_error);
784 stat8 = info->buf_nerr;
786 if (stat8 & 0x0f) { /* Error, so process */
788 membuf_error(stat8, error_found, handle_error);
792 static void e752x_check_dram(struct mem_ctl_info *mci,
793 struct e752x_error_info *info, int *error_found,
796 u16 error_one, error_next;
798 error_one = info->dram_ferr;
799 error_next = info->dram_nerr;
801 /* decode and report errors */
802 if (error_one & 0x0101) /* check first error correctable */
803 process_ce(mci, error_one, info->dram_sec1_add,
804 info->dram_sec1_syndrome, error_found, handle_error);
806 if (error_next & 0x0101) /* check next error correctable */
807 process_ce(mci, error_next, info->dram_sec2_add,
808 info->dram_sec2_syndrome, error_found, handle_error);
810 if (error_one & 0x4040)
811 process_ue_no_info_wr(mci, error_found, handle_error);
813 if (error_next & 0x4040)
814 process_ue_no_info_wr(mci, error_found, handle_error);
816 if (error_one & 0x2020)
817 process_ded_retry(mci, error_one, info->dram_retr_add,
818 error_found, handle_error);
820 if (error_next & 0x2020)
821 process_ded_retry(mci, error_next, info->dram_retr_add,
822 error_found, handle_error);
824 if (error_one & 0x0808)
825 process_threshold_ce(mci, error_one, error_found, handle_error);
827 if (error_next & 0x0808)
828 process_threshold_ce(mci, error_next, error_found,
831 if (error_one & 0x0606)
832 process_ue(mci, error_one, info->dram_ded_add,
833 info->dram_scrb_add, error_found, handle_error);
835 if (error_next & 0x0606)
836 process_ue(mci, error_next, info->dram_ded_add,
837 info->dram_scrb_add, error_found, handle_error);
840 static void e752x_get_error_info(struct mem_ctl_info *mci,
841 struct e752x_error_info *info)
844 struct e752x_pvt *pvt;
846 memset(info, 0, sizeof(*info));
847 pvt = (struct e752x_pvt *)mci->pvt_info;
849 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
851 if (info->ferr_global) {
852 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
853 pci_read_config_dword(dev, I3100_NSI_FERR,
857 pci_read_config_byte(dev, E752X_HI_FERR,
861 pci_read_config_word(dev, E752X_SYSBUS_FERR,
863 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
864 pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr);
865 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
866 &info->dram_sec1_add);
867 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
868 &info->dram_sec1_syndrome);
869 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
870 &info->dram_ded_add);
871 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
872 &info->dram_scrb_add);
873 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
874 &info->dram_retr_add);
876 /* ignore the reserved bits just in case */
877 if (info->hi_ferr & 0x7f)
878 pci_write_config_byte(dev, E752X_HI_FERR,
881 if (info->nsi_ferr & NSI_ERR_MASK)
882 pci_write_config_dword(dev, I3100_NSI_FERR,
885 if (info->sysbus_ferr)
886 pci_write_config_word(dev, E752X_SYSBUS_FERR,
889 if (info->buf_ferr & 0x0f)
890 pci_write_config_byte(dev, E752X_BUF_FERR,
894 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
895 info->dram_ferr, info->dram_ferr);
897 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
901 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
903 if (info->nerr_global) {
904 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
905 pci_read_config_dword(dev, I3100_NSI_NERR,
909 pci_read_config_byte(dev, E752X_HI_NERR,
913 pci_read_config_word(dev, E752X_SYSBUS_NERR,
915 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
916 pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr);
917 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
918 &info->dram_sec2_add);
919 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
920 &info->dram_sec2_syndrome);
922 if (info->hi_nerr & 0x7f)
923 pci_write_config_byte(dev, E752X_HI_NERR,
926 if (info->nsi_nerr & NSI_ERR_MASK)
927 pci_write_config_dword(dev, I3100_NSI_NERR,
930 if (info->sysbus_nerr)
931 pci_write_config_word(dev, E752X_SYSBUS_NERR,
934 if (info->buf_nerr & 0x0f)
935 pci_write_config_byte(dev, E752X_BUF_NERR,
939 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
940 info->dram_nerr, info->dram_nerr);
942 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
947 static int e752x_process_error_info(struct mem_ctl_info *mci,
948 struct e752x_error_info *info,
955 error32 = (info->ferr_global >> 18) & 0x3ff;
956 stat32 = (info->ferr_global >> 4) & 0x7ff;
959 global_error(1, error32, &error_found, handle_errors);
962 global_error(0, stat32, &error_found, handle_errors);
964 error32 = (info->nerr_global >> 18) & 0x3ff;
965 stat32 = (info->nerr_global >> 4) & 0x7ff;
968 global_error(1, error32, &error_found, handle_errors);
971 global_error(0, stat32, &error_found, handle_errors);
973 e752x_check_hub_interface(info, &error_found, handle_errors);
974 e752x_check_ns_interface(info, &error_found, handle_errors);
975 e752x_check_sysbus(info, &error_found, handle_errors);
976 e752x_check_membuf(info, &error_found, handle_errors);
977 e752x_check_dram(mci, info, &error_found, handle_errors);
981 static void e752x_check(struct mem_ctl_info *mci)
983 struct e752x_error_info info;
985 debugf3("%s()\n", __func__);
986 e752x_get_error_info(mci, &info);
987 e752x_process_error_info(mci, &info, 1);
990 /* Program byte/sec bandwidth scrub rate to hardware */
991 static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
993 const struct scrubrate *scrubrates;
994 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
995 struct pci_dev *pdev = pvt->dev_d0f0;
998 if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0)
999 scrubrates = scrubrates_i3100;
1001 scrubrates = scrubrates_e752x;
1003 /* Translate the desired scrub rate to a e752x/3100 register value.
1004 * Search for the bandwidth that is equal or greater than the
1005 * desired rate and program the cooresponding register value.
1007 for (i = 0; scrubrates[i].bandwidth != SDRATE_EOT; i++)
1008 if (scrubrates[i].bandwidth >= new_bw)
1011 if (scrubrates[i].bandwidth == SDRATE_EOT)
1014 pci_write_config_word(pdev, E752X_MCHSCRB, scrubrates[i].scrubval);
1016 return scrubrates[i].bandwidth;
1019 /* Convert current scrub rate value into byte/sec bandwidth */
1020 static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
1022 const struct scrubrate *scrubrates;
1023 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
1024 struct pci_dev *pdev = pvt->dev_d0f0;
1028 if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0)
1029 scrubrates = scrubrates_i3100;
1031 scrubrates = scrubrates_e752x;
1033 /* Find the bandwidth matching the memory scrubber configuration */
1034 pci_read_config_word(pdev, E752X_MCHSCRB, &scrubval);
1035 scrubval = scrubval & 0x0f;
1037 for (i = 0; scrubrates[i].bandwidth != SDRATE_EOT; i++)
1038 if (scrubrates[i].scrubval == scrubval)
1041 if (scrubrates[i].bandwidth == SDRATE_EOT) {
1042 e752x_printk(KERN_WARNING,
1043 "Invalid sdram scrub control value: 0x%x\n", scrubval);
1046 return scrubrates[i].bandwidth;
1050 /* Return 1 if dual channel mode is active. Else return 0. */
1051 static inline int dual_channel_active(u16 ddrcsr)
1053 return (((ddrcsr >> 12) & 3) == 3);
1056 /* Remap csrow index numbers if map_type is "reverse"
1058 static inline int remap_csrow_index(struct mem_ctl_info *mci, int index)
1060 struct e752x_pvt *pvt = mci->pvt_info;
1068 static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
1071 struct csrow_info *csrow;
1072 enum edac_type edac_mode;
1073 unsigned long last_cumul_size;
1074 int index, mem_dev, drc_chan;
1075 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
1076 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
1078 u32 dra, drc, cumul_size, i, nr_pages;
1081 for (index = 0; index < 4; index++) {
1083 pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg);
1084 dra |= dra_reg << (index * 8);
1086 pci_read_config_dword(pdev, E752X_DRC, &drc);
1087 drc_chan = dual_channel_active(ddrcsr) ? 1 : 0;
1088 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
1089 drc_ddim = (drc >> 20) & 0x3;
1091 /* The dram row boundary (DRB) reg values are boundary address for
1092 * each DRAM row with a granularity of 64 or 128MB (single/dual
1093 * channel operation). DRB regs are cumulative; therefore DRB7 will
1094 * contain the total memory contained in all eight rows.
1096 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
1097 /* mem_dev 0=x8, 1=x4 */
1098 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
1099 csrow = mci->csrows[remap_csrow_index(mci, index)];
1101 mem_dev = (mem_dev == 2);
1102 pci_read_config_byte(pdev, E752X_DRB + index, &value);
1103 /* convert a 128 or 64 MiB DRB to a page size. */
1104 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
1105 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
1107 if (cumul_size == last_cumul_size)
1108 continue; /* not populated */
1110 csrow->first_page = last_cumul_size;
1111 csrow->last_page = cumul_size - 1;
1112 nr_pages = cumul_size - last_cumul_size;
1113 last_cumul_size = cumul_size;
1116 * if single channel or x8 devices then SECDED
1117 * if dual channel and x4 then S4ECD4ED
1120 if (drc_chan && mem_dev) {
1121 edac_mode = EDAC_S4ECD4ED;
1122 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
1124 edac_mode = EDAC_SECDED;
1125 mci->edac_cap |= EDAC_FLAG_SECDED;
1128 edac_mode = EDAC_NONE;
1129 for (i = 0; i < csrow->nr_channels; i++) {
1130 struct dimm_info *dimm = csrow->channels[i]->dimm;
1132 debugf3("Initializing rank at (%i,%i)\n", index, i);
1133 dimm->nr_pages = nr_pages / csrow->nr_channels;
1134 dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
1135 dimm->mtype = MEM_RDDR; /* only one type supported */
1136 dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
1137 dimm->edac_mode = edac_mode;
1142 static void e752x_init_mem_map_table(struct pci_dev *pdev,
1143 struct e752x_pvt *pvt)
1146 u8 value, last, row;
1151 for (index = 0; index < 8; index += 2) {
1152 pci_read_config_byte(pdev, E752X_DRB + index, &value);
1153 /* test if there is a dimm in this slot */
1154 if (value == last) {
1155 /* no dimm in the slot, so flag it as empty */
1156 pvt->map[index] = 0xff;
1157 pvt->map[index + 1] = 0xff;
1158 } else { /* there is a dimm in the slot */
1159 pvt->map[index] = row;
1162 /* test the next value to see if the dimm is double
1165 pci_read_config_byte(pdev, E752X_DRB + index + 1,
1168 /* the dimm is single sided, so flag as empty */
1169 /* this is a double sided dimm to save the next row #*/
1170 pvt->map[index + 1] = (value == last) ? 0xff : row;
1177 /* Return 0 on success or 1 on failure. */
1178 static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
1179 struct e752x_pvt *pvt)
1181 struct pci_dev *dev;
1183 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
1184 pvt->dev_info->err_dev, pvt->bridge_ck);
1186 if (pvt->bridge_ck == NULL)
1187 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
1190 if (pvt->bridge_ck == NULL) {
1191 e752x_printk(KERN_ERR, "error reporting device not found:"
1192 "vendor %x device 0x%x (broken BIOS?)\n",
1193 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
1197 dev = pci_get_device(PCI_VENDOR_ID_INTEL,
1198 e752x_devs[dev_idx].ctl_dev,
1204 pvt->dev_d0f0 = dev;
1205 pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
1210 pci_dev_put(pvt->bridge_ck);
1214 /* Setup system bus parity mask register.
1215 * Sysbus parity supported on:
1216 * e7320/e7520/e7525 + Xeon
1218 static void e752x_init_sysbus_parity_mask(struct e752x_pvt *pvt)
1220 char *cpu_id = cpu_data(0).x86_model_id;
1221 struct pci_dev *dev = pvt->dev_d0f1;
1224 /* Allow module parameter override, else see if CPU supports parity */
1225 if (sysbus_parity != -1) {
1226 enable = sysbus_parity;
1227 } else if (cpu_id[0] && !strstr(cpu_id, "Xeon")) {
1228 e752x_printk(KERN_INFO, "System Bus Parity not "
1229 "supported by CPU, disabling\n");
1234 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0000);
1236 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0309);
1239 static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
1241 struct pci_dev *dev;
1243 dev = pvt->dev_d0f1;
1244 /* Turn off error disable & SMI in case the BIOS turned it on */
1245 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
1246 pci_write_config_dword(dev, I3100_NSI_EMASK, 0);
1247 pci_write_config_dword(dev, I3100_NSI_SMICMD, 0);
1249 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
1250 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
1253 e752x_init_sysbus_parity_mask(pvt);
1255 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
1256 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
1257 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
1258 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
1259 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
1262 static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1266 struct mem_ctl_info *mci;
1267 struct edac_mc_layer layers[2];
1268 struct e752x_pvt *pvt;
1270 int drc_chan; /* Number of channels 0=1chan,1=2chan */
1271 struct e752x_error_info discard;
1273 debugf0("%s(): mci\n", __func__);
1274 debugf0("Starting Probe1\n");
1276 /* check to see if device 0 function 1 is enabled; if it isn't, we
1277 * assume the BIOS has reserved it for a reason and is expecting
1278 * exclusive access, we take care not to violate that assumption and
1279 * fail the probe. */
1280 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
1281 if (!force_function_unhide && !(stat8 & (1 << 5))) {
1282 printk(KERN_INFO "Contact your BIOS vendor to see if the "
1283 "E752x error registers can be safely un-hidden\n");
1287 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
1289 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
1290 /* FIXME: should check >>12 or 0xf, true for all? */
1291 /* Dual channel = 1, Single channel = 0 */
1292 drc_chan = dual_channel_active(ddrcsr);
1294 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1295 layers[0].size = E752X_NR_CSROWS;
1296 layers[0].is_virt_csrow = true;
1297 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1298 layers[1].size = drc_chan + 1;
1299 layers[1].is_virt_csrow = false;
1300 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1304 debugf3("%s(): init mci\n", __func__);
1305 mci->mtype_cap = MEM_FLAG_RDDR;
1306 /* 3100 IMCH supports SECDEC only */
1307 mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED :
1308 (EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED);
1309 /* FIXME - what if different memory types are in different csrows? */
1310 mci->mod_name = EDAC_MOD_STR;
1311 mci->mod_ver = E752X_REVISION;
1312 mci->pdev = &pdev->dev;
1314 debugf3("%s(): init pvt\n", __func__);
1315 pvt = (struct e752x_pvt *)mci->pvt_info;
1316 pvt->dev_info = &e752x_devs[dev_idx];
1317 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
1319 if (e752x_get_devs(pdev, dev_idx, pvt)) {
1324 debugf3("%s(): more mci init\n", __func__);
1325 mci->ctl_name = pvt->dev_info->ctl_name;
1326 mci->dev_name = pci_name(pdev);
1327 mci->edac_check = e752x_check;
1328 mci->ctl_page_to_phys = ctl_page_to_phys;
1329 mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
1330 mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
1332 /* set the map type. 1 = normal, 0 = reversed
1333 * Must be set before e752x_init_csrows in case csrow mapping
1336 pci_read_config_byte(pdev, E752X_DRM, &stat8);
1337 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1339 e752x_init_csrows(mci, pdev, ddrcsr);
1340 e752x_init_mem_map_table(pdev, pvt);
1342 if (dev_idx == I3100)
1343 mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */
1345 mci->edac_cap |= EDAC_FLAG_NONE;
1346 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
1348 /* load the top of low memory, remap base, and remap limit vars */
1349 pci_read_config_word(pdev, E752X_TOLM, &pci_data);
1350 pvt->tolm = ((u32) pci_data) << 4;
1351 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
1352 pvt->remapbase = ((u32) pci_data) << 14;
1353 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
1354 pvt->remaplimit = ((u32) pci_data) << 14;
1355 e752x_printk(KERN_INFO,
1356 "tolm = %x, remapbase = %x, remaplimit = %x\n",
1357 pvt->tolm, pvt->remapbase, pvt->remaplimit);
1359 /* Here we assume that we will never see multiple instances of this
1360 * type of memory controller. The ID is therefore hardcoded to 0.
1362 if (edac_mc_add_mc(mci)) {
1363 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
1367 e752x_init_error_reporting_regs(pvt);
1368 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
1370 /* allocating generic PCI control info */
1371 e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1374 "%s(): Unable to create PCI control\n", __func__);
1376 "%s(): PCI error report via EDAC not setup\n",
1380 /* get this far and it's successful */
1381 debugf3("%s(): success\n", __func__);
1385 pci_dev_put(pvt->dev_d0f0);
1386 pci_dev_put(pvt->dev_d0f1);
1387 pci_dev_put(pvt->bridge_ck);
1393 /* returns count (>= 0), or negative on error */
1394 static int __devinit e752x_init_one(struct pci_dev *pdev,
1395 const struct pci_device_id *ent)
1397 debugf0("%s()\n", __func__);
1399 /* wake up and enable device */
1400 if (pci_enable_device(pdev) < 0)
1403 return e752x_probe1(pdev, ent->driver_data);
1406 static void __devexit e752x_remove_one(struct pci_dev *pdev)
1408 struct mem_ctl_info *mci;
1409 struct e752x_pvt *pvt;
1411 debugf0("%s()\n", __func__);
1414 edac_pci_release_generic_ctl(e752x_pci);
1416 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1419 pvt = (struct e752x_pvt *)mci->pvt_info;
1420 pci_dev_put(pvt->dev_d0f0);
1421 pci_dev_put(pvt->dev_d0f1);
1422 pci_dev_put(pvt->bridge_ck);
1426 static DEFINE_PCI_DEVICE_TABLE(e752x_pci_tbl) = {
1428 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1431 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1434 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1437 PCI_VEND_DEV(INTEL, 3100_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1441 } /* 0 terminated list. */
1444 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1446 static struct pci_driver e752x_driver = {
1447 .name = EDAC_MOD_STR,
1448 .probe = e752x_init_one,
1449 .remove = __devexit_p(e752x_remove_one),
1450 .id_table = e752x_pci_tbl,
1453 static int __init e752x_init(void)
1457 debugf3("%s()\n", __func__);
1459 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1462 pci_rc = pci_register_driver(&e752x_driver);
1463 return (pci_rc < 0) ? pci_rc : 0;
1466 static void __exit e752x_exit(void)
1468 debugf3("%s()\n", __func__);
1469 pci_unregister_driver(&e752x_driver);
1472 module_init(e752x_init);
1473 module_exit(e752x_exit);
1475 MODULE_LICENSE("GPL");
1476 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1477 MODULE_DESCRIPTION("MC support for Intel e752x/3100 memory controllers");
1479 module_param(force_function_unhide, int, 0444);
1480 MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1481 " 1=force unhide and hope BIOS doesn't fight driver for "
1482 "Dev0:Fun1 access");
1484 module_param(edac_op_state, int, 0444);
1485 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1487 module_param(sysbus_parity, int, 0444);
1488 MODULE_PARM_DESC(sysbus_parity, "0=disable system bus parity checking,"
1489 " 1=enable system bus parity checking, default=auto-detect");
1490 module_param(report_non_memory_errors, int, 0644);
1491 MODULE_PARM_DESC(report_non_memory_errors, "0=disable non-memory error "
1492 "reporting, 1=enable non-memory error reporting");