2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * See "enum e752x_chips" below for supported chipsets
9 * Written by Tom Zimmerman
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/pci_ids.h>
24 #include <linux/slab.h>
25 #include <linux/edac.h>
26 #include "edac_core.h"
28 #define E752X_REVISION " Ver: 2.0.2 " __DATE__
29 #define EDAC_MOD_STR "e752x_edac"
31 static int force_function_unhide;
33 static struct edac_pci_ctl_info *e752x_pci;
35 #define e752x_printk(level, fmt, arg...) \
36 edac_printk(level, "e752x", fmt, ##arg)
38 #define e752x_mc_printk(mci, level, fmt, arg...) \
39 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
41 #ifndef PCI_DEVICE_ID_INTEL_7520_0
42 #define PCI_DEVICE_ID_INTEL_7520_0 0x3590
43 #endif /* PCI_DEVICE_ID_INTEL_7520_0 */
45 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
46 #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
47 #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
49 #ifndef PCI_DEVICE_ID_INTEL_7525_0
50 #define PCI_DEVICE_ID_INTEL_7525_0 0x359E
51 #endif /* PCI_DEVICE_ID_INTEL_7525_0 */
53 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
54 #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
55 #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
57 #ifndef PCI_DEVICE_ID_INTEL_7320_0
58 #define PCI_DEVICE_ID_INTEL_7320_0 0x3592
59 #endif /* PCI_DEVICE_ID_INTEL_7320_0 */
61 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
62 #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
63 #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
65 #ifndef PCI_DEVICE_ID_INTEL_3100_0
66 #define PCI_DEVICE_ID_INTEL_3100_0 0x35B0
67 #endif /* PCI_DEVICE_ID_INTEL_3100_0 */
69 #ifndef PCI_DEVICE_ID_INTEL_3100_1_ERR
70 #define PCI_DEVICE_ID_INTEL_3100_1_ERR 0x35B1
71 #endif /* PCI_DEVICE_ID_INTEL_3100_1_ERR */
73 #define E752X_NR_CSROWS 8 /* number of csrows */
75 /* E752X register addresses - device 0 function 0 */
76 #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
77 #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
79 * 31:30 Device width row 7
80 * 01=x8 10=x4 11=x8 DDR2
81 * 27:26 Device width row 6
82 * 23:22 Device width row 5
83 * 19:20 Device width row 4
84 * 15:14 Device width row 3
85 * 11:10 Device width row 2
86 * 7:6 Device width row 1
87 * 3:2 Device width row 0
89 #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
90 /* FIXME:IS THIS RIGHT? */
92 * 22 Number channels 0=1,1=2
93 * 19:18 DRB Granularity 32/64MB
95 #define E752X_DRM 0x80 /* Dimm mapping register */
96 #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
98 * 14:12 1 single A, 2 single B, 3 dual
100 #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
101 #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
102 #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
103 #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
105 /* E752X register addresses - device 0 function 1 */
106 #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
107 #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
108 #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
109 #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
110 #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
111 #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
112 #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
113 #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
114 #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
115 #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
116 #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
117 #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
118 #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
119 #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
120 #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
121 #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
122 #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
123 #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
124 #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
125 #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
126 /* error address register (32b) */
129 * 30:2 CE address (64 byte block 34:6)
133 #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
134 /* error address register (32b) */
137 * 30:2 CE address (64 byte block 34:6)
141 #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
142 /* error address register (32b) */
145 * 30:2 CE address (64 byte block 34:6)
149 #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
150 /* error address register (32b) */
153 * 30:2 CE address (64 byte block 34:6)
157 #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
158 /* error syndrome register (16b) */
159 #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
160 /* error syndrome register (16b) */
161 #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
163 /* 3100 IMCH specific register addresses - device 0 function 1 */
164 #define I3100_NSI_FERR 0x48 /* NSI first error reg (32b) */
165 #define I3100_NSI_NERR 0x4C /* NSI next error reg (32b) */
166 #define I3100_NSI_SMICMD 0x54 /* NSI SMI command register (32b) */
167 #define I3100_NSI_EMASK 0x90 /* NSI error mask register (32b) */
169 /* ICH5R register addresses - device 30 function 0 */
170 #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
171 #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
172 #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
182 struct pci_dev *bridge_ck;
183 struct pci_dev *dev_d0f0;
184 struct pci_dev *dev_d0f1;
191 const struct e752x_dev_info *dev_info;
194 struct e752x_dev_info {
197 const char *ctl_name;
200 struct e752x_error_info {
203 u32 nsi_ferr; /* 3100 only */
204 u32 nsi_nerr; /* 3100 only */
205 u8 hi_ferr; /* all but 3100 */
206 u8 hi_nerr; /* all but 3100 */
215 u16 dram_sec1_syndrome;
216 u16 dram_sec2_syndrome;
222 static const struct e752x_dev_info e752x_devs[] = {
224 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
225 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
226 .ctl_name = "E7520"},
228 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
229 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
230 .ctl_name = "E7525"},
232 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
233 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
234 .ctl_name = "E7320"},
236 .err_dev = PCI_DEVICE_ID_INTEL_3100_1_ERR,
237 .ctl_dev = PCI_DEVICE_ID_INTEL_3100_0,
241 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
245 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
247 debugf3("%s()\n", __func__);
249 if (page < pvt->tolm)
252 if ((page >= 0x100000) && (page < pvt->remapbase))
255 remap = (page - pvt->tolm) + pvt->remapbase;
257 if (remap < pvt->remaplimit)
260 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
261 return pvt->tolm - 1;
264 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
265 u32 sec1_add, u16 sec1_syndrome)
271 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
273 debugf3("%s()\n", __func__);
275 /* convert the addr to 4k page */
276 page = sec1_add >> (PAGE_SHIFT - 4);
278 /* FIXME - check for -1 */
279 if (pvt->mc_symmetric) {
280 /* chip select are bits 14 & 13 */
281 row = ((page >> 1) & 3);
282 e752x_printk(KERN_WARNING,
283 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
284 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
285 pvt->map[4], pvt->map[5], pvt->map[6],
288 /* test for channel remapping */
289 for (i = 0; i < 8; i++) {
290 if (pvt->map[i] == row)
294 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
299 e752x_mc_printk(mci, KERN_WARNING,
300 "row %d not found in remap table\n",
303 row = edac_mc_find_csrow_by_page(mci, page);
305 /* 0 = channel A, 1 = channel B */
306 channel = !(error_one & 1);
308 /* e752x mc reads 34:6 of the DRAM linear address */
309 edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4),
310 sec1_syndrome, row, channel, "e752x CE");
313 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
314 u32 sec1_add, u16 sec1_syndrome, int *error_found,
320 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
323 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
324 u32 ded_add, u32 scrb_add)
326 u32 error_2b, block_page;
328 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
330 debugf3("%s()\n", __func__);
332 if (error_one & 0x0202) {
335 /* convert to 4k address */
336 block_page = error_2b >> (PAGE_SHIFT - 4);
338 row = pvt->mc_symmetric ?
339 /* chip select are bits 14 & 13 */
340 ((block_page >> 1) & 3) :
341 edac_mc_find_csrow_by_page(mci, block_page);
343 /* e752x mc reads 34:6 of the DRAM linear address */
344 edac_mc_handle_ue(mci, block_page,
345 offset_in_page(error_2b << 4),
346 row, "e752x UE from Read");
348 if (error_one & 0x0404) {
351 /* convert to 4k address */
352 block_page = error_2b >> (PAGE_SHIFT - 4);
354 row = pvt->mc_symmetric ?
355 /* chip select are bits 14 & 13 */
356 ((block_page >> 1) & 3) :
357 edac_mc_find_csrow_by_page(mci, block_page);
359 /* e752x mc reads 34:6 of the DRAM linear address */
360 edac_mc_handle_ue(mci, block_page,
361 offset_in_page(error_2b << 4),
362 row, "e752x UE from Scruber");
366 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
367 u32 ded_add, u32 scrb_add, int *error_found,
373 do_process_ue(mci, error_one, ded_add, scrb_add);
376 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
377 int *error_found, int handle_error)
384 debugf3("%s()\n", __func__);
385 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
388 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
393 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
395 error_1b = retry_add;
396 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
397 row = pvt->mc_symmetric ? ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
398 edac_mc_find_csrow_by_page(mci, page);
399 e752x_mc_printk(mci, KERN_WARNING,
400 "CE page 0x%lx, row %d : Memory read retry\n",
401 (long unsigned int)page, row);
404 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
405 u32 retry_add, int *error_found,
411 do_process_ded_retry(mci, error, retry_add);
414 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
415 int *error_found, int handle_error)
420 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
423 static char *global_message[11] = {
424 "PCI Express C1", "PCI Express C", "PCI Express B1",
425 "PCI Express B", "PCI Express A1", "PCI Express A",
426 "DMA Controler", "HUB or NS Interface", "System Bus",
427 "DRAM Controler", "Internal Buffer"
430 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
432 static void do_global_error(int fatal, u32 errors)
436 for (i = 0; i < 11; i++) {
437 if (errors & (1 << i))
438 e752x_printk(KERN_WARNING, "%sError %s\n",
439 fatal_message[fatal], global_message[i]);
443 static inline void global_error(int fatal, u32 errors, int *error_found,
449 do_global_error(fatal, errors);
452 static char *hub_message[7] = {
453 "HI Address or Command Parity", "HI Illegal Access",
454 "HI Internal Parity", "Out of Range Access",
455 "HI Data Parity", "Enhanced Config Access",
456 "Hub Interface Target Abort"
459 static void do_hub_error(int fatal, u8 errors)
463 for (i = 0; i < 7; i++) {
464 if (errors & (1 << i))
465 e752x_printk(KERN_WARNING, "%sError %s\n",
466 fatal_message[fatal], hub_message[i]);
470 static inline void hub_error(int fatal, u8 errors, int *error_found,
476 do_hub_error(fatal, errors);
479 #define NSI_FATAL_MASK 0x0c080081
480 #define NSI_NON_FATAL_MASK 0x23a0ba64
481 #define NSI_ERR_MASK (NSI_FATAL_MASK | NSI_NON_FATAL_MASK)
483 static char *nsi_message[30] = {
484 "NSI Link Down", /* NSI_FERR/NSI_NERR bit 0, fatal error */
486 "NSI Parity Error", /* bit 2, non-fatal */
489 "Correctable Error Message", /* bit 5, non-fatal */
490 "Non-Fatal Error Message", /* bit 6, non-fatal */
491 "Fatal Error Message", /* bit 7, fatal */
493 "Receiver Error", /* bit 9, non-fatal */
495 "Bad TLP", /* bit 11, non-fatal */
496 "Bad DLLP", /* bit 12, non-fatal */
497 "REPLAY_NUM Rollover", /* bit 13, non-fatal */
499 "Replay Timer Timeout", /* bit 15, non-fatal */
503 "Data Link Protocol Error", /* bit 19, fatal */
505 "Poisoned TLP", /* bit 21, non-fatal */
507 "Completion Timeout", /* bit 23, non-fatal */
508 "Completer Abort", /* bit 24, non-fatal */
509 "Unexpected Completion", /* bit 25, non-fatal */
510 "Receiver Overflow", /* bit 26, fatal */
511 "Malformed TLP", /* bit 27, fatal */
513 "Unsupported Request" /* bit 29, non-fatal */
516 static void do_nsi_error(int fatal, u32 errors)
520 for (i = 0; i < 30; i++) {
521 if (errors & (1 << i))
522 printk(KERN_WARNING "%sError %s\n",
523 fatal_message[fatal], nsi_message[i]);
527 static inline void nsi_error(int fatal, u32 errors, int *error_found,
533 do_nsi_error(fatal, errors);
536 static char *membuf_message[4] = {
537 "Internal PMWB to DRAM parity",
538 "Internal PMWB to System Bus Parity",
539 "Internal System Bus or IO to PMWB Parity",
540 "Internal DRAM to PMWB Parity"
543 static void do_membuf_error(u8 errors)
547 for (i = 0; i < 4; i++) {
548 if (errors & (1 << i))
549 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
554 static inline void membuf_error(u8 errors, int *error_found, int handle_error)
559 do_membuf_error(errors);
562 static char *sysbus_message[10] = {
563 "Addr or Request Parity",
564 "Data Strobe Glitch",
565 "Addr Strobe Glitch",
568 "Non DRAM Lock Error",
571 "IO Subsystem Parity"
574 static void do_sysbus_error(int fatal, u32 errors)
578 for (i = 0; i < 10; i++) {
579 if (errors & (1 << i))
580 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
581 fatal_message[fatal], sysbus_message[i]);
585 static inline void sysbus_error(int fatal, u32 errors, int *error_found,
591 do_sysbus_error(fatal, errors);
594 static void e752x_check_hub_interface(struct e752x_error_info *info,
595 int *error_found, int handle_error)
599 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
601 stat8 = info->hi_ferr;
603 if (stat8 & 0x7f) { /* Error, so process */
607 hub_error(1, stat8 & 0x2b, error_found, handle_error);
610 hub_error(0, stat8 & 0x54, error_found, handle_error);
612 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
614 stat8 = info->hi_nerr;
616 if (stat8 & 0x7f) { /* Error, so process */
620 hub_error(1, stat8 & 0x2b, error_found, handle_error);
623 hub_error(0, stat8 & 0x54, error_found, handle_error);
627 static void e752x_check_ns_interface(struct e752x_error_info *info,
628 int *error_found, int handle_error)
632 stat32 = info->nsi_ferr;
633 if (stat32 & NSI_ERR_MASK) { /* Error, so process */
634 if (stat32 & NSI_FATAL_MASK) /* check for fatal errors */
635 nsi_error(1, stat32 & NSI_FATAL_MASK, error_found,
637 if (stat32 & NSI_NON_FATAL_MASK) /* check for non-fatal ones */
638 nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found,
641 stat32 = info->nsi_nerr;
642 if (stat32 & NSI_ERR_MASK) {
643 if (stat32 & NSI_FATAL_MASK)
644 nsi_error(1, stat32 & NSI_FATAL_MASK, error_found,
646 if (stat32 & NSI_NON_FATAL_MASK)
647 nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found,
652 static void e752x_check_sysbus(struct e752x_error_info *info,
653 int *error_found, int handle_error)
657 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
658 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
661 return; /* no errors */
663 error32 = (stat32 >> 16) & 0x3ff;
664 stat32 = stat32 & 0x3ff;
667 sysbus_error(1, stat32 & 0x087, error_found, handle_error);
670 sysbus_error(0, stat32 & 0x378, error_found, handle_error);
673 sysbus_error(1, error32 & 0x087, error_found, handle_error);
676 sysbus_error(0, error32 & 0x378, error_found, handle_error);
679 static void e752x_check_membuf(struct e752x_error_info *info,
680 int *error_found, int handle_error)
684 stat8 = info->buf_ferr;
686 if (stat8 & 0x0f) { /* Error, so process */
688 membuf_error(stat8, error_found, handle_error);
691 stat8 = info->buf_nerr;
693 if (stat8 & 0x0f) { /* Error, so process */
695 membuf_error(stat8, error_found, handle_error);
699 static void e752x_check_dram(struct mem_ctl_info *mci,
700 struct e752x_error_info *info, int *error_found,
703 u16 error_one, error_next;
705 error_one = info->dram_ferr;
706 error_next = info->dram_nerr;
708 /* decode and report errors */
709 if (error_one & 0x0101) /* check first error correctable */
710 process_ce(mci, error_one, info->dram_sec1_add,
711 info->dram_sec1_syndrome, error_found, handle_error);
713 if (error_next & 0x0101) /* check next error correctable */
714 process_ce(mci, error_next, info->dram_sec2_add,
715 info->dram_sec2_syndrome, error_found, handle_error);
717 if (error_one & 0x4040)
718 process_ue_no_info_wr(mci, error_found, handle_error);
720 if (error_next & 0x4040)
721 process_ue_no_info_wr(mci, error_found, handle_error);
723 if (error_one & 0x2020)
724 process_ded_retry(mci, error_one, info->dram_retr_add,
725 error_found, handle_error);
727 if (error_next & 0x2020)
728 process_ded_retry(mci, error_next, info->dram_retr_add,
729 error_found, handle_error);
731 if (error_one & 0x0808)
732 process_threshold_ce(mci, error_one, error_found, handle_error);
734 if (error_next & 0x0808)
735 process_threshold_ce(mci, error_next, error_found,
738 if (error_one & 0x0606)
739 process_ue(mci, error_one, info->dram_ded_add,
740 info->dram_scrb_add, error_found, handle_error);
742 if (error_next & 0x0606)
743 process_ue(mci, error_next, info->dram_ded_add,
744 info->dram_scrb_add, error_found, handle_error);
747 static void e752x_get_error_info(struct mem_ctl_info *mci,
748 struct e752x_error_info *info)
751 struct e752x_pvt *pvt;
753 memset(info, 0, sizeof(*info));
754 pvt = (struct e752x_pvt *)mci->pvt_info;
756 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
758 if (info->ferr_global) {
759 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
760 pci_read_config_dword(dev, I3100_NSI_FERR,
764 pci_read_config_byte(dev, E752X_HI_FERR,
768 pci_read_config_word(dev, E752X_SYSBUS_FERR,
770 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
771 pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr);
772 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
773 &info->dram_sec1_add);
774 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
775 &info->dram_sec1_syndrome);
776 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
777 &info->dram_ded_add);
778 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
779 &info->dram_scrb_add);
780 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
781 &info->dram_retr_add);
783 /* ignore the reserved bits just in case */
784 if (info->hi_ferr & 0x7f)
785 pci_write_config_byte(dev, E752X_HI_FERR,
788 if (info->nsi_ferr & NSI_ERR_MASK)
789 pci_write_config_dword(dev, I3100_NSI_FERR,
792 if (info->sysbus_ferr)
793 pci_write_config_word(dev, E752X_SYSBUS_FERR,
796 if (info->buf_ferr & 0x0f)
797 pci_write_config_byte(dev, E752X_BUF_FERR,
801 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
802 info->dram_ferr, info->dram_ferr);
804 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
808 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
810 if (info->nerr_global) {
811 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
812 pci_read_config_dword(dev, I3100_NSI_NERR,
816 pci_read_config_byte(dev, E752X_HI_NERR,
820 pci_read_config_word(dev, E752X_SYSBUS_NERR,
822 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
823 pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr);
824 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
825 &info->dram_sec2_add);
826 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
827 &info->dram_sec2_syndrome);
829 if (info->hi_nerr & 0x7f)
830 pci_write_config_byte(dev, E752X_HI_NERR,
833 if (info->nsi_nerr & NSI_ERR_MASK)
834 pci_write_config_dword(dev, I3100_NSI_NERR,
837 if (info->sysbus_nerr)
838 pci_write_config_word(dev, E752X_SYSBUS_NERR,
841 if (info->buf_nerr & 0x0f)
842 pci_write_config_byte(dev, E752X_BUF_NERR,
846 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
847 info->dram_nerr, info->dram_nerr);
849 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
854 static int e752x_process_error_info(struct mem_ctl_info *mci,
855 struct e752x_error_info *info,
862 error32 = (info->ferr_global >> 18) & 0x3ff;
863 stat32 = (info->ferr_global >> 4) & 0x7ff;
866 global_error(1, error32, &error_found, handle_errors);
869 global_error(0, stat32, &error_found, handle_errors);
871 error32 = (info->nerr_global >> 18) & 0x3ff;
872 stat32 = (info->nerr_global >> 4) & 0x7ff;
875 global_error(1, error32, &error_found, handle_errors);
878 global_error(0, stat32, &error_found, handle_errors);
880 e752x_check_hub_interface(info, &error_found, handle_errors);
881 e752x_check_ns_interface(info, &error_found, handle_errors);
882 e752x_check_sysbus(info, &error_found, handle_errors);
883 e752x_check_membuf(info, &error_found, handle_errors);
884 e752x_check_dram(mci, info, &error_found, handle_errors);
888 static void e752x_check(struct mem_ctl_info *mci)
890 struct e752x_error_info info;
892 debugf3("%s()\n", __func__);
893 e752x_get_error_info(mci, &info);
894 e752x_process_error_info(mci, &info, 1);
897 /* Return 1 if dual channel mode is active. Else return 0. */
898 static inline int dual_channel_active(u16 ddrcsr)
900 return (((ddrcsr >> 12) & 3) == 3);
903 /* Remap csrow index numbers if map_type is "reverse"
905 static inline int remap_csrow_index(struct mem_ctl_info *mci, int index)
907 struct e752x_pvt *pvt = mci->pvt_info;
915 static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
918 struct csrow_info *csrow;
919 unsigned long last_cumul_size;
920 int index, mem_dev, drc_chan;
921 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
922 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
924 u32 dra, drc, cumul_size;
927 for (index = 0; index < 4; index++) {
929 pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg);
930 dra |= dra_reg << (index * 8);
932 pci_read_config_dword(pdev, E752X_DRC, &drc);
933 drc_chan = dual_channel_active(ddrcsr);
934 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
935 drc_ddim = (drc >> 20) & 0x3;
937 /* The dram row boundary (DRB) reg values are boundary address for
938 * each DRAM row with a granularity of 64 or 128MB (single/dual
939 * channel operation). DRB regs are cumulative; therefore DRB7 will
940 * contain the total memory contained in all eight rows.
942 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
943 /* mem_dev 0=x8, 1=x4 */
944 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
945 csrow = &mci->csrows[remap_csrow_index(mci, index)];
947 mem_dev = (mem_dev == 2);
948 pci_read_config_byte(pdev, E752X_DRB + index, &value);
949 /* convert a 128 or 64 MiB DRB to a page size. */
950 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
951 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
953 if (cumul_size == last_cumul_size)
954 continue; /* not populated */
956 csrow->first_page = last_cumul_size;
957 csrow->last_page = cumul_size - 1;
958 csrow->nr_pages = cumul_size - last_cumul_size;
959 last_cumul_size = cumul_size;
960 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
961 csrow->mtype = MEM_RDDR; /* only one type supported */
962 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
965 * if single channel or x8 devices then SECDED
966 * if dual channel and x4 then S4ECD4ED
969 if (drc_chan && mem_dev) {
970 csrow->edac_mode = EDAC_S4ECD4ED;
971 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
973 csrow->edac_mode = EDAC_SECDED;
974 mci->edac_cap |= EDAC_FLAG_SECDED;
977 csrow->edac_mode = EDAC_NONE;
981 static void e752x_init_mem_map_table(struct pci_dev *pdev,
982 struct e752x_pvt *pvt)
990 for (index = 0; index < 8; index += 2) {
991 pci_read_config_byte(pdev, E752X_DRB + index, &value);
992 /* test if there is a dimm in this slot */
994 /* no dimm in the slot, so flag it as empty */
995 pvt->map[index] = 0xff;
996 pvt->map[index + 1] = 0xff;
997 } else { /* there is a dimm in the slot */
998 pvt->map[index] = row;
1001 /* test the next value to see if the dimm is double
1004 pci_read_config_byte(pdev, E752X_DRB + index + 1,
1007 /* the dimm is single sided, so flag as empty */
1008 /* this is a double sided dimm to save the next row #*/
1009 pvt->map[index + 1] = (value == last) ? 0xff : row;
1016 /* Return 0 on success or 1 on failure. */
1017 static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
1018 struct e752x_pvt *pvt)
1020 struct pci_dev *dev;
1022 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
1023 pvt->dev_info->err_dev, pvt->bridge_ck);
1025 if (pvt->bridge_ck == NULL)
1026 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
1029 if (pvt->bridge_ck == NULL) {
1030 e752x_printk(KERN_ERR, "error reporting device not found:"
1031 "vendor %x device 0x%x (broken BIOS?)\n",
1032 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
1036 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
1042 pvt->dev_d0f0 = dev;
1043 pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
1048 pci_dev_put(pvt->bridge_ck);
1052 static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
1054 struct pci_dev *dev;
1056 dev = pvt->dev_d0f1;
1057 /* Turn off error disable & SMI in case the BIOS turned it on */
1058 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
1059 pci_write_config_dword(dev, I3100_NSI_EMASK, 0);
1060 pci_write_config_dword(dev, I3100_NSI_SMICMD, 0);
1062 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
1063 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
1065 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
1066 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
1067 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
1068 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
1069 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
1070 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
1073 static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1077 struct mem_ctl_info *mci;
1078 struct e752x_pvt *pvt;
1080 int drc_chan; /* Number of channels 0=1chan,1=2chan */
1081 struct e752x_error_info discard;
1083 debugf0("%s(): mci\n", __func__);
1084 debugf0("Starting Probe1\n");
1086 /* make sure error reporting method is sane */
1087 switch (edac_op_state) {
1088 case EDAC_OPSTATE_POLL:
1089 case EDAC_OPSTATE_NMI:
1092 edac_op_state = EDAC_OPSTATE_POLL;
1096 /* check to see if device 0 function 1 is enabled; if it isn't, we
1097 * assume the BIOS has reserved it for a reason and is expecting
1098 * exclusive access, we take care not to violate that assumption and
1099 * fail the probe. */
1100 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
1101 if (!force_function_unhide && !(stat8 & (1 << 5))) {
1102 printk(KERN_INFO "Contact your BIOS vendor to see if the "
1103 "E752x error registers can be safely un-hidden\n");
1107 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
1109 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
1110 /* FIXME: should check >>12 or 0xf, true for all? */
1111 /* Dual channel = 1, Single channel = 0 */
1112 drc_chan = dual_channel_active(ddrcsr);
1114 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1, 0);
1120 debugf3("%s(): init mci\n", __func__);
1121 mci->mtype_cap = MEM_FLAG_RDDR;
1122 /* 3100 IMCH supports SECDEC only */
1123 mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED :
1124 (EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED);
1125 /* FIXME - what if different memory types are in different csrows? */
1126 mci->mod_name = EDAC_MOD_STR;
1127 mci->mod_ver = E752X_REVISION;
1128 mci->dev = &pdev->dev;
1130 debugf3("%s(): init pvt\n", __func__);
1131 pvt = (struct e752x_pvt *)mci->pvt_info;
1132 pvt->dev_info = &e752x_devs[dev_idx];
1133 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
1135 if (e752x_get_devs(pdev, dev_idx, pvt)) {
1140 debugf3("%s(): more mci init\n", __func__);
1141 mci->ctl_name = pvt->dev_info->ctl_name;
1142 mci->dev_name = pci_name(pdev);
1143 mci->edac_check = e752x_check;
1144 mci->ctl_page_to_phys = ctl_page_to_phys;
1146 /* set the map type. 1 = normal, 0 = reversed
1147 * Must be set before e752x_init_csrows in case csrow mapping
1150 pci_read_config_byte(pdev, E752X_DRM, &stat8);
1151 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1153 e752x_init_csrows(mci, pdev, ddrcsr);
1154 e752x_init_mem_map_table(pdev, pvt);
1156 if (dev_idx == I3100)
1157 mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */
1159 mci->edac_cap |= EDAC_FLAG_NONE;
1160 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
1162 /* load the top of low memory, remap base, and remap limit vars */
1163 pci_read_config_word(pdev, E752X_TOLM, &pci_data);
1164 pvt->tolm = ((u32) pci_data) << 4;
1165 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
1166 pvt->remapbase = ((u32) pci_data) << 14;
1167 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
1168 pvt->remaplimit = ((u32) pci_data) << 14;
1169 e752x_printk(KERN_INFO,
1170 "tolm = %x, remapbase = %x, remaplimit = %x\n",
1171 pvt->tolm, pvt->remapbase, pvt->remaplimit);
1173 /* Here we assume that we will never see multiple instances of this
1174 * type of memory controller. The ID is therefore hardcoded to 0.
1176 if (edac_mc_add_mc(mci)) {
1177 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
1181 e752x_init_error_reporting_regs(pvt);
1182 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
1184 /* allocating generic PCI control info */
1185 e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1188 "%s(): Unable to create PCI control\n", __func__);
1190 "%s(): PCI error report via EDAC not setup\n",
1194 /* get this far and it's successful */
1195 debugf3("%s(): success\n", __func__);
1199 pci_dev_put(pvt->dev_d0f0);
1200 pci_dev_put(pvt->dev_d0f1);
1201 pci_dev_put(pvt->bridge_ck);
1207 /* returns count (>= 0), or negative on error */
1208 static int __devinit e752x_init_one(struct pci_dev *pdev,
1209 const struct pci_device_id *ent)
1211 debugf0("%s()\n", __func__);
1213 /* wake up and enable device */
1214 if (pci_enable_device(pdev) < 0)
1217 return e752x_probe1(pdev, ent->driver_data);
1220 static void __devexit e752x_remove_one(struct pci_dev *pdev)
1222 struct mem_ctl_info *mci;
1223 struct e752x_pvt *pvt;
1225 debugf0("%s()\n", __func__);
1228 edac_pci_release_generic_ctl(e752x_pci);
1230 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1233 pvt = (struct e752x_pvt *)mci->pvt_info;
1234 pci_dev_put(pvt->dev_d0f0);
1235 pci_dev_put(pvt->dev_d0f1);
1236 pci_dev_put(pvt->bridge_ck);
1240 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
1242 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1245 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1248 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1251 PCI_VEND_DEV(INTEL, 3100_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1255 } /* 0 terminated list. */
1258 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1260 static struct pci_driver e752x_driver = {
1261 .name = EDAC_MOD_STR,
1262 .probe = e752x_init_one,
1263 .remove = __devexit_p(e752x_remove_one),
1264 .id_table = e752x_pci_tbl,
1267 static int __init e752x_init(void)
1271 debugf3("%s()\n", __func__);
1272 pci_rc = pci_register_driver(&e752x_driver);
1273 return (pci_rc < 0) ? pci_rc : 0;
1276 static void __exit e752x_exit(void)
1278 debugf3("%s()\n", __func__);
1279 pci_unregister_driver(&e752x_driver);
1282 module_init(e752x_init);
1283 module_exit(e752x_exit);
1285 MODULE_LICENSE("GPL");
1286 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1287 MODULE_DESCRIPTION("MC support for Intel e752x/3100 memory controllers");
1289 module_param(force_function_unhide, int, 0444);
1290 MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1291 " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
1292 module_param(edac_op_state, int, 0444);
1293 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");