drivers/edac/edac_mc.c

   1 /*
   2  * edac_mc kernel module
   3  * (C) 2005, 2006 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Thayne Harbaugh
   8  * Based on work by Dan Hollis <goemon at anime dot net> and others.
   9  *      http://www.anime.net/~goemon/linux-ecc/
  10  *
  11  * Modified by Dave Peterson and Doug Thompson
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/proc_fs.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/smp.h>
  20 #include <linux/init.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/highmem.h>
  23 #include <linux/timer.h>
  24 #include <linux/slab.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/list.h>
  28 #include <linux/ctype.h>
  29 #include <linux/edac.h>
  30 #include <linux/bitops.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/page.h>
  33 #include "edac_core.h"
  34 #include "edac_module.h"
  35 #include <ras/ras_event.h>
  36
  37 #ifdef CONFIG_EDAC_ATOMIC_SCRUB
  38 #include <asm/edac.h>
  39 #else
  40 #define edac_atomic_scrub(va, size) do { } while (0)
  41 #endif
  42
  43 /* lock to memory controller's control array */
  44 static DEFINE_MUTEX(mem_ctls_mutex);
  45 static LIST_HEAD(mc_devices);
  46
  47 /*
  48  * Used to lock EDAC MC to just one module, avoiding two drivers e. g.
  49  *      apei/ghes and i7core_edac to be used at the same time.
  50  */
  51 static void const *edac_mc_owner;
  52
  53 static struct bus_type mc_bus[EDAC_MAX_MCS];
  54
  55 unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf,
  56                                  unsigned len)
  57 {
  58         struct mem_ctl_info *mci = dimm->mci;
  59         int i, n, count = 0;
  60         char *p = buf;
  61
  62         for (i = 0; i < mci->n_layers; i++) {
  63                 n = snprintf(p, len, "%s %d ",
  64                               edac_layer_name[mci->layers[i].type],
  65                               dimm->location[i]);
  66                 p += n;
  67                 len -= n;
  68                 count += n;
  69                 if (!len)
  70                         break;
  71         }
  72
  73         return count;
  74 }
  75
  76 #ifdef CONFIG_EDAC_DEBUG
  77
  78 static void edac_mc_dump_channel(struct rank_info *chan)
  79 {
  80         edac_dbg(4, "  channel->chan_idx = %d\n", chan->chan_idx);
  81         edac_dbg(4, "    channel = %p\n", chan);
  82         edac_dbg(4, "    channel->csrow = %p\n", chan->csrow);
  83         edac_dbg(4, "    channel->dimm = %p\n", chan->dimm);
  84 }
  85
  86 static void edac_mc_dump_dimm(struct dimm_info *dimm, int number)
  87 {
  88         char location[80];
  89
  90         edac_dimm_info_location(dimm, location, sizeof(location));
  91
  92         edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n",
  93                  dimm->mci->csbased ? "rank" : "dimm",
  94                  number, location, dimm->csrow, dimm->cschannel);
  95         edac_dbg(4, "  dimm = %p\n", dimm);
  96         edac_dbg(4, "  dimm->label = '%s'\n", dimm->label);
  97         edac_dbg(4, "  dimm->nr_pages = 0x%x\n", dimm->nr_pages);
  98         edac_dbg(4, "  dimm->grain = %d\n", dimm->grain);
  99         edac_dbg(4, "  dimm->nr_pages = 0x%x\n", dimm->nr_pages);
 100 }
 101
 102 static void edac_mc_dump_csrow(struct csrow_info *csrow)
 103 {
 104         edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx);
 105         edac_dbg(4, "  csrow = %p\n", csrow);
 106         edac_dbg(4, "  csrow->first_page = 0x%lx\n", csrow->first_page);
 107         edac_dbg(4, "  csrow->last_page = 0x%lx\n", csrow->last_page);
 108         edac_dbg(4, "  csrow->page_mask = 0x%lx\n", csrow->page_mask);
 109         edac_dbg(4, "  csrow->nr_channels = %d\n", csrow->nr_channels);
 110         edac_dbg(4, "  csrow->channels = %p\n", csrow->channels);
 111         edac_dbg(4, "  csrow->mci = %p\n", csrow->mci);
 112 }
 113
 114 static void edac_mc_dump_mci(struct mem_ctl_info *mci)
 115 {
 116         edac_dbg(3, "\tmci = %p\n", mci);
 117         edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap);
 118         edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap);
 119         edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap);
 120         edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check);
 121         edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n",
 122                  mci->nr_csrows, mci->csrows);
 123         edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n",
 124                  mci->tot_dimms, mci->dimms);
 125         edac_dbg(3, "\tdev = %p\n", mci->pdev);
 126         edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n",
 127                  mci->mod_name, mci->ctl_name);
 128         edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info);
 129 }
 130
 131 #endif                          /* CONFIG_EDAC_DEBUG */
 132
 133 const char * const edac_mem_types[] = {
 134         [MEM_EMPTY]     = "Empty csrow",
 135         [MEM_RESERVED]  = "Reserved csrow type",
 136         [MEM_UNKNOWN]   = "Unknown csrow type",
 137         [MEM_FPM]       = "Fast page mode RAM",
 138         [MEM_EDO]       = "Extended data out RAM",
 139         [MEM_BEDO]      = "Burst Extended data out RAM",
 140         [MEM_SDR]       = "Single data rate SDRAM",
 141         [MEM_RDR]       = "Registered single data rate SDRAM",
 142         [MEM_DDR]       = "Double data rate SDRAM",
 143         [MEM_RDDR]      = "Registered Double data rate SDRAM",
 144         [MEM_RMBS]      = "Rambus DRAM",
 145         [MEM_DDR2]      = "Unbuffered DDR2 RAM",
 146         [MEM_FB_DDR2]   = "Fully buffered DDR2",
 147         [MEM_RDDR2]     = "Registered DDR2 RAM",
 148         [MEM_XDR]       = "Rambus XDR",
 149         [MEM_DDR3]      = "Unbuffered DDR3 RAM",
 150         [MEM_RDDR3]     = "Registered DDR3 RAM",
 151         [MEM_LRDDR3]    = "Load-Reduced DDR3 RAM",
 152         [MEM_DDR4]      = "Unbuffered DDR4 RAM",
 153         [MEM_RDDR4]     = "Registered DDR4 RAM",
 154 };
 155 EXPORT_SYMBOL_GPL(edac_mem_types);
 156
 157 /**
 158  * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation
 159  * @p:          pointer to a pointer with the memory offset to be used. At
 160  *              return, this will be incremented to point to the next offset
 161  * @size:       Size of the data structure to be reserved
 162  * @n_elems:    Number of elements that should be reserved
 163  *
 164  * If 'size' is a constant, the compiler will optimize this whole function
 165  * down to either a no-op or the addition of a constant to the value of '*p'.
 166  *
 167  * The 'p' pointer is absolutely needed to keep the proper advancing
 168  * further in memory to the proper offsets when allocating the struct along
 169  * with its embedded structs, as edac_device_alloc_ctl_info() does it
 170  * above, for example.
 171  *
 172  * At return, the pointer 'p' will be incremented to be used on a next call
 173  * to this function.
 174  */
 175 void *edac_align_ptr(void **p, unsigned size, int n_elems)
 176 {
 177         unsigned align, r;
 178         void *ptr = *p;
 179
 180         *p += size * n_elems;
 181
 182         /*
 183          * 'p' can possibly be an unaligned item X such that sizeof(X) is
 184          * 'size'.  Adjust 'p' so that its alignment is at least as
 185          * stringent as what the compiler would provide for X and return
 186          * the aligned result.
 187          * Here we assume that the alignment of a "long long" is the most
 188          * stringent alignment that the compiler will ever provide by default.
 189          * As far as I know, this is a reasonable assumption.
 190          */
 191         if (size > sizeof(long))
 192                 align = sizeof(long long);
 193         else if (size > sizeof(int))
 194                 align = sizeof(long);
 195         else if (size > sizeof(short))
 196                 align = sizeof(int);
 197         else if (size > sizeof(char))
 198                 align = sizeof(short);
 199         else
 200                 return (char *)ptr;
 201
 202         r = (unsigned long)p % align;
 203
 204         if (r == 0)
 205                 return (char *)ptr;
 206
 207         *p += align - r;
 208
 209         return (void *)(((unsigned long)ptr) + align - r);
 210 }
 211
 212 static void _edac_mc_free(struct mem_ctl_info *mci)
 213 {
 214         int i, chn, row;
 215         struct csrow_info *csr;
 216         const unsigned int tot_dimms = mci->tot_dimms;
 217         const unsigned int tot_channels = mci->num_cschannel;
 218         const unsigned int tot_csrows = mci->nr_csrows;
 219
 220         if (mci->dimms) {
 221                 for (i = 0; i < tot_dimms; i++)
 222                         kfree(mci->dimms[i]);
 223                 kfree(mci->dimms);
 224         }
 225         if (mci->csrows) {
 226                 for (row = 0; row < tot_csrows; row++) {
 227                         csr = mci->csrows[row];
 228                         if (csr) {
 229                                 if (csr->channels) {
 230                                         for (chn = 0; chn < tot_channels; chn++)
 231                                                 kfree(csr->channels[chn]);
 232                                         kfree(csr->channels);
 233                                 }
 234                                 kfree(csr);
 235                         }
 236                 }
 237                 kfree(mci->csrows);
 238         }
 239         kfree(mci);
 240 }
 241
 242 /**
 243  * edac_mc_alloc: Allocate and partially fill a struct mem_ctl_info structure
 244  * @mc_num:             Memory controller number
 245  * @n_layers:           Number of MC hierarchy layers
 246  * layers:              Describes each layer as seen by the Memory Controller
 247  * @size_pvt:           size of private storage needed
 248  *
 249  *
 250  * Everything is kmalloc'ed as one big chunk - more efficient.
 251  * Only can be used if all structures have the same lifetime - otherwise
 252  * you have to allocate and initialize your own structures.
 253  *
 254  * Use edac_mc_free() to free mc structures allocated by this function.
 255  *
 256  * NOTE: drivers handle multi-rank memories in different ways: in some
 257  * drivers, one multi-rank memory stick is mapped as one entry, while, in
 258  * others, a single multi-rank memory stick would be mapped into several
 259  * entries. Currently, this function will allocate multiple struct dimm_info
 260  * on such scenarios, as grouping the multiple ranks require drivers change.
 261  *
 262  * Returns:
 263  *      On failure: NULL
 264  *      On success: struct mem_ctl_info pointer
 265  */
 266 struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
 267                                    unsigned n_layers,
 268                                    struct edac_mc_layer *layers,
 269                                    unsigned sz_pvt)
 270 {
 271         struct mem_ctl_info *mci;
 272         struct edac_mc_layer *layer;
 273         struct csrow_info *csr;
 274         struct rank_info *chan;
 275         struct dimm_info *dimm;
 276         u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
 277         unsigned pos[EDAC_MAX_LAYERS];
 278         unsigned size, tot_dimms = 1, count = 1;
 279         unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0;
 280         void *pvt, *p, *ptr = NULL;
 281         int i, j, row, chn, n, len, off;
 282         bool per_rank = false;
 283
 284         BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0);
 285         /*
 286          * Calculate the total amount of dimms and csrows/cschannels while
 287          * in the old API emulation mode
 288          */
 289         for (i = 0; i < n_layers; i++) {
 290                 tot_dimms *= layers[i].size;
 291                 if (layers[i].is_virt_csrow)
 292                         tot_csrows *= layers[i].size;
 293                 else
 294                         tot_channels *= layers[i].size;
 295
 296                 if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT)
 297                         per_rank = true;
 298         }
 299
 300         /* Figure out the offsets of the various items from the start of an mc
 301          * structure.  We want the alignment of each item to be at least as
 302          * stringent as what the compiler would provide if we could simply
 303          * hardcode everything into a single struct.
 304          */
 305         mci = edac_align_ptr(&ptr, sizeof(*mci), 1);
 306         layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers);
 307         for (i = 0; i < n_layers; i++) {
 308                 count *= layers[i].size;
 309                 edac_dbg(4, "errcount layer %d size %d\n", i, count);
 310                 ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
 311                 ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
 312                 tot_errcount += 2 * count;
 313         }
 314
 315         edac_dbg(4, "allocating %d error counters\n", tot_errcount);
 316         pvt = edac_align_ptr(&ptr, sz_pvt, 1);
 317         size = ((unsigned long)pvt) + sz_pvt;
 318
 319         edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n",
 320                  size,
 321                  tot_dimms,
 322                  per_rank ? "ranks" : "dimms",
 323                  tot_csrows * tot_channels);
 324
 325         mci = kzalloc(size, GFP_KERNEL);
 326         if (mci == NULL)
 327                 return NULL;
 328
 329         /* Adjust pointers so they point within the memory we just allocated
 330          * rather than an imaginary chunk of memory located at address 0.
 331          */
 332         layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer));
 333         for (i = 0; i < n_layers; i++) {
 334                 mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i]));
 335                 mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i]));
 336         }
 337         pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL;
 338
 339         /* setup index and various internal pointers */
 340         mci->mc_idx = mc_num;
 341         mci->tot_dimms = tot_dimms;
 342         mci->pvt_info = pvt;
 343         mci->n_layers = n_layers;
 344         mci->layers = layer;
 345         memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
 346         mci->nr_csrows = tot_csrows;
 347         mci->num_cschannel = tot_channels;
 348         mci->csbased = per_rank;
 349
 350         /*
 351          * Alocate and fill the csrow/channels structs
 352          */
 353         mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL);
 354         if (!mci->csrows)
 355                 goto error;
 356         for (row = 0; row < tot_csrows; row++) {
 357                 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL);
 358                 if (!csr)
 359                         goto error;
 360                 mci->csrows[row] = csr;
 361                 csr->csrow_idx = row;
 362                 csr->mci = mci;
 363                 csr->nr_channels = tot_channels;
 364                 csr->channels = kcalloc(tot_channels, sizeof(*csr->channels),
 365                                         GFP_KERNEL);
 366                 if (!csr->channels)
 367                         goto error;
 368
 369                 for (chn = 0; chn < tot_channels; chn++) {
 370                         chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL);
 371                         if (!chan)
 372                                 goto error;
 373                         csr->channels[chn] = chan;
 374                         chan->chan_idx = chn;
 375                         chan->csrow = csr;
 376                 }
 377         }
 378
 379         /*
 380          * Allocate and fill the dimm structs
 381          */
 382         mci->dimms  = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL);
 383         if (!mci->dimms)
 384                 goto error;
 385
 386         memset(&pos, 0, sizeof(pos));
 387         row = 0;
 388         chn = 0;
 389         for (i = 0; i < tot_dimms; i++) {
 390                 chan = mci->csrows[row]->channels[chn];
 391                 off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]);
 392                 if (off < 0 || off >= tot_dimms) {
 393                         edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n");
 394                         goto error;
 395                 }
 396
 397                 dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL);
 398                 if (!dimm)
 399                         goto error;
 400                 mci->dimms[off] = dimm;
 401                 dimm->mci = mci;
 402
 403                 /*
 404                  * Copy DIMM location and initialize it.
 405                  */
 406                 len = sizeof(dimm->label);
 407                 p = dimm->label;
 408                 n = snprintf(p, len, "mc#%u", mc_num);
 409                 p += n;
 410                 len -= n;
 411                 for (j = 0; j < n_layers; j++) {
 412                         n = snprintf(p, len, "%s#%u",
 413                                      edac_layer_name[layers[j].type],
 414                                      pos[j]);
 415                         p += n;
 416                         len -= n;
 417                         dimm->location[j] = pos[j];
 418
 419                         if (len <= 0)
 420                                 break;
 421                 }
 422
 423                 /* Link it to the csrows old API data */
 424                 chan->dimm = dimm;
 425                 dimm->csrow = row;
 426                 dimm->cschannel = chn;
 427
 428                 /* Increment csrow location */
 429                 if (layers[0].is_virt_csrow) {
 430                         chn++;
 431                         if (chn == tot_channels) {
 432                                 chn = 0;
 433                                 row++;
 434                         }
 435                 } else {
 436                         row++;
 437                         if (row == tot_csrows) {
 438                                 row = 0;
 439                                 chn++;
 440                         }
 441                 }
 442
 443                 /* Increment dimm location */
 444                 for (j = n_layers - 1; j >= 0; j--) {
 445                         pos[j]++;
 446                         if (pos[j] < layers[j].size)
 447                                 break;
 448                         pos[j] = 0;
 449                 }
 450         }
 451
 452         mci->op_state = OP_ALLOC;
 453
 454         return mci;
 455
 456 error:
 457         _edac_mc_free(mci);
 458
 459         return NULL;
 460 }
 461 EXPORT_SYMBOL_GPL(edac_mc_alloc);
 462
 463 /**
 464  * edac_mc_free
 465  *      'Free' a previously allocated 'mci' structure
 466  * @mci: pointer to a struct mem_ctl_info structure
 467  */
 468 void edac_mc_free(struct mem_ctl_info *mci)
 469 {
 470         edac_dbg(1, "\n");
 471
 472         /* If we're not yet registered with sysfs free only what was allocated
 473          * in edac_mc_alloc().
 474          */
 475         if (!device_is_registered(&mci->dev)) {
 476                 _edac_mc_free(mci);
 477                 return;
 478         }
 479
 480         /* the mci instance is freed here, when the sysfs object is dropped */
 481         edac_unregister_sysfs(mci);
 482 }
 483 EXPORT_SYMBOL_GPL(edac_mc_free);
 484
 485
 486 /**
 487  * find_mci_by_dev
 488  *
 489  *      scan list of controllers looking for the one that manages
 490  *      the 'dev' device
 491  * @dev: pointer to a struct device related with the MCI
 492  */
 493 struct mem_ctl_info *find_mci_by_dev(struct device *dev)
 494 {
 495         struct mem_ctl_info *mci;
 496         struct list_head *item;
 497
 498         edac_dbg(3, "\n");
 499
 500         list_for_each(item, &mc_devices) {
 501                 mci = list_entry(item, struct mem_ctl_info, link);
 502
 503                 if (mci->pdev == dev)
 504                         return mci;
 505         }
 506
 507         return NULL;
 508 }
 509 EXPORT_SYMBOL_GPL(find_mci_by_dev);
 510
 511 /*
 512  * handler for EDAC to check if NMI type handler has asserted interrupt
 513  */
 514 static int edac_mc_assert_error_check_and_clear(void)
 515 {
 516         int old_state;
 517
 518         if (edac_op_state == EDAC_OPSTATE_POLL)
 519                 return 1;
 520
 521         old_state = edac_err_assert;
 522         edac_err_assert = 0;
 523
 524         return old_state;
 525 }
 526
 527 /*
 528  * edac_mc_workq_function
 529  *      performs the operation scheduled by a workq request
 530  */
 531 static void edac_mc_workq_function(struct work_struct *work_req)
 532 {
 533         struct delayed_work *d_work = to_delayed_work(work_req);
 534         struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work);
 535
 536         mutex_lock(&mem_ctls_mutex);
 537
 538         /* if this control struct has movd to offline state, we are done */
 539         if (mci->op_state == OP_OFFLINE) {
 540                 mutex_unlock(&mem_ctls_mutex);
 541                 return;
 542         }
 543
 544         /* Only poll controllers that are running polled and have a check */
 545         if (edac_mc_assert_error_check_and_clear() && (mci->edac_check != NULL))
 546                 mci->edac_check(mci);
 547
 548         mutex_unlock(&mem_ctls_mutex);
 549
 550         /* Reschedule */
 551         edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
 552 }
 553
 554 /*
 555  * edac_mc_reset_delay_period(unsigned long value)
 556  *
 557  *      user space has updated our poll period value, need to
 558  *      reset our workq delays
 559  */
 560 void edac_mc_reset_delay_period(unsigned long value)
 561 {
 562         struct mem_ctl_info *mci;
 563         struct list_head *item;
 564
 565         mutex_lock(&mem_ctls_mutex);
 566
 567         list_for_each(item, &mc_devices) {
 568                 mci = list_entry(item, struct mem_ctl_info, link);
 569
 570                 edac_mod_work(&mci->work, value);
 571         }
 572         mutex_unlock(&mem_ctls_mutex);
 573 }
 574
 575
 576
 577 /* Return 0 on success, 1 on failure.
 578  * Before calling this function, caller must
 579  * assign a unique value to mci->mc_idx.
 580  *
 581  *      locking model:
 582  *
 583  *              called with the mem_ctls_mutex lock held
 584  */
 585 static int add_mc_to_global_list(struct mem_ctl_info *mci)
 586 {
 587         struct list_head *item, *insert_before;
 588         struct mem_ctl_info *p;
 589
 590         insert_before = &mc_devices;
 591
 592         p = find_mci_by_dev(mci->pdev);
 593         if (unlikely(p != NULL))
 594                 goto fail0;
 595
 596         list_for_each(item, &mc_devices) {
 597                 p = list_entry(item, struct mem_ctl_info, link);
 598
 599                 if (p->mc_idx >= mci->mc_idx) {
 600                         if (unlikely(p->mc_idx == mci->mc_idx))
 601                                 goto fail1;
 602
 603                         insert_before = item;
 604                         break;
 605                 }
 606         }
 607
 608         list_add_tail_rcu(&mci->link, insert_before);
 609         atomic_inc(&edac_handlers);
 610         return 0;
 611
 612 fail0:
 613         edac_printk(KERN_WARNING, EDAC_MC,
 614                 "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev),
 615                 edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx);
 616         return 1;
 617
 618 fail1:
 619         edac_printk(KERN_WARNING, EDAC_MC,
 620                 "bug in low-level driver: attempt to assign\n"
 621                 "    duplicate mc_idx %d in %s()\n", p->mc_idx, __func__);
 622         return 1;
 623 }
 624
 625 static int del_mc_from_global_list(struct mem_ctl_info *mci)
 626 {
 627         int handlers = atomic_dec_return(&edac_handlers);
 628         list_del_rcu(&mci->link);
 629
 630         /* these are for safe removal of devices from global list while
 631          * NMI handlers may be traversing list
 632          */
 633         synchronize_rcu();
 634         INIT_LIST_HEAD(&mci->link);
 635
 636         return handlers;
 637 }
 638
 639 /**
 640  * edac_mc_find: Search for a mem_ctl_info structure whose index is 'idx'.
 641  *
 642  * If found, return a pointer to the structure.
 643  * Else return NULL.
 644  *
 645  * Caller must hold mem_ctls_mutex.
 646  */
 647 struct mem_ctl_info *edac_mc_find(int idx)
 648 {
 649         struct list_head *item;
 650         struct mem_ctl_info *mci;
 651
 652         list_for_each(item, &mc_devices) {
 653                 mci = list_entry(item, struct mem_ctl_info, link);
 654
 655                 if (mci->mc_idx >= idx) {
 656                         if (mci->mc_idx == idx)
 657                                 return mci;
 658
 659                         break;
 660                 }
 661         }
 662
 663         return NULL;
 664 }
 665 EXPORT_SYMBOL(edac_mc_find);
 666
 667 /**
 668  * edac_mc_add_mc_with_groups: Insert the 'mci' structure into the mci
 669  *      global list and create sysfs entries associated with mci structure
 670  * @mci: pointer to the mci structure to be added to the list
 671  * @groups: optional attribute groups for the driver-specific sysfs entries
 672  *
 673  * Return:
 674  *      0       Success
 675  *      !0      Failure
 676  */
 677
 678 /* FIXME - should a warning be printed if no error detection? correction? */
 679 int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
 680                                const struct attribute_group **groups)
 681 {
 682         int ret = -EINVAL;
 683         edac_dbg(0, "\n");
 684
 685         if (mci->mc_idx >= EDAC_MAX_MCS) {
 686                 pr_warn_once("Too many memory controllers: %d\n", mci->mc_idx);
 687                 return -ENODEV;
 688         }
 689
 690 #ifdef CONFIG_EDAC_DEBUG
 691         if (edac_debug_level >= 3)
 692                 edac_mc_dump_mci(mci);
 693
 694         if (edac_debug_level >= 4) {
 695                 int i;
 696
 697                 for (i = 0; i < mci->nr_csrows; i++) {
 698                         struct csrow_info *csrow = mci->csrows[i];
 699                         u32 nr_pages = 0;
 700                         int j;
 701
 702                         for (j = 0; j < csrow->nr_channels; j++)
 703                                 nr_pages += csrow->channels[j]->dimm->nr_pages;
 704                         if (!nr_pages)
 705                                 continue;
 706                         edac_mc_dump_csrow(csrow);
 707                         for (j = 0; j < csrow->nr_channels; j++)
 708                                 if (csrow->channels[j]->dimm->nr_pages)
 709                                         edac_mc_dump_channel(csrow->channels[j]);
 710                 }
 711                 for (i = 0; i < mci->tot_dimms; i++)
 712                         if (mci->dimms[i]->nr_pages)
 713                                 edac_mc_dump_dimm(mci->dimms[i], i);
 714         }
 715 #endif
 716         mutex_lock(&mem_ctls_mutex);
 717
 718         if (edac_mc_owner && edac_mc_owner != mci->mod_name) {
 719                 ret = -EPERM;
 720                 goto fail0;
 721         }
 722
 723         if (add_mc_to_global_list(mci))
 724                 goto fail0;
 725
 726         /* set load time so that error rate can be tracked */
 727         mci->start_time = jiffies;
 728
 729         mci->bus = &mc_bus[mci->mc_idx];
 730
 731         if (edac_create_sysfs_mci_device(mci, groups)) {
 732                 edac_mc_printk(mci, KERN_WARNING,
 733                         "failed to create sysfs device\n");
 734                 goto fail1;
 735         }
 736
 737         if (mci->edac_check) {
 738                 mci->op_state = OP_RUNNING_POLL;
 739
 740                 INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function);
 741                 edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
 742
 743         } else {
 744                 mci->op_state = OP_RUNNING_INTERRUPT;
 745         }
 746
 747         /* Report action taken */
 748         edac_mc_printk(mci, KERN_INFO,
 749                 "Giving out device to module %s controller %s: DEV %s (%s)\n",
 750                 mci->mod_name, mci->ctl_name, mci->dev_name,
 751                 edac_op_state_to_string(mci->op_state));
 752
 753         edac_mc_owner = mci->mod_name;
 754
 755         mutex_unlock(&mem_ctls_mutex);
 756         return 0;
 757
 758 fail1:
 759         del_mc_from_global_list(mci);
 760
 761 fail0:
 762         mutex_unlock(&mem_ctls_mutex);
 763         return ret;
 764 }
 765 EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups);
 766
 767 /**
 768  * edac_mc_del_mc: Remove sysfs entries for specified mci structure and
 769  *                 remove mci structure from global list
 770  * @pdev: Pointer to 'struct device' representing mci structure to remove.
 771  *
 772  * Return pointer to removed mci structure, or NULL if device not found.
 773  */
 774 struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
 775 {
 776         struct mem_ctl_info *mci;
 777
 778         edac_dbg(0, "\n");
 779
 780         mutex_lock(&mem_ctls_mutex);
 781
 782         /* find the requested mci struct in the global list */
 783         mci = find_mci_by_dev(dev);
 784         if (mci == NULL) {
 785                 mutex_unlock(&mem_ctls_mutex);
 786                 return NULL;
 787         }
 788
 789         /* mark MCI offline: */
 790         mci->op_state = OP_OFFLINE;
 791
 792         if (!del_mc_from_global_list(mci))
 793                 edac_mc_owner = NULL;
 794
 795         mutex_unlock(&mem_ctls_mutex);
 796
 797         if (mci->edac_check)
 798                 edac_stop_work(&mci->work);
 799
 800         /* remove from sysfs */
 801         edac_remove_sysfs_mci_device(mci);
 802
 803         edac_printk(KERN_INFO, EDAC_MC,
 804                 "Removed device %d for %s %s: DEV %s\n", mci->mc_idx,
 805                 mci->mod_name, mci->ctl_name, edac_dev_name(mci));
 806
 807         return mci;
 808 }
 809 EXPORT_SYMBOL_GPL(edac_mc_del_mc);
 810
 811 static void edac_mc_scrub_block(unsigned long page, unsigned long offset,
 812                                 u32 size)
 813 {
 814         struct page *pg;
 815         void *virt_addr;
 816         unsigned long flags = 0;
 817
 818         edac_dbg(3, "\n");
 819
 820         /* ECC error page was not in our memory. Ignore it. */
 821         if (!pfn_valid(page))
 822                 return;
 823
 824         /* Find the actual page structure then map it and fix */
 825         pg = pfn_to_page(page);
 826
 827         if (PageHighMem(pg))
 828                 local_irq_save(flags);
 829
 830         virt_addr = kmap_atomic(pg);
 831
 832         /* Perform architecture specific atomic scrub operation */
 833         edac_atomic_scrub(virt_addr + offset, size);
 834
 835         /* Unmap and complete */
 836         kunmap_atomic(virt_addr);
 837
 838         if (PageHighMem(pg))
 839                 local_irq_restore(flags);
 840 }
 841
 842 /* FIXME - should return -1 */
 843 int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
 844 {
 845         struct csrow_info **csrows = mci->csrows;
 846         int row, i, j, n;
 847
 848         edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page);
 849         row = -1;
 850
 851         for (i = 0; i < mci->nr_csrows; i++) {
 852                 struct csrow_info *csrow = csrows[i];
 853                 n = 0;
 854                 for (j = 0; j < csrow->nr_channels; j++) {
 855                         struct dimm_info *dimm = csrow->channels[j]->dimm;
 856                         n += dimm->nr_pages;
 857                 }
 858                 if (n == 0)
 859                         continue;
 860
 861                 edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n",
 862                          mci->mc_idx,
 863                          csrow->first_page, page, csrow->last_page,
 864                          csrow->page_mask);
 865
 866                 if ((page >= csrow->first_page) &&
 867                     (page <= csrow->last_page) &&
 868                     ((page & csrow->page_mask) ==
 869                      (csrow->first_page & csrow->page_mask))) {
 870                         row = i;
 871                         break;
 872                 }
 873         }
 874
 875         if (row == -1)
 876                 edac_mc_printk(mci, KERN_ERR,
 877                         "could not look up page error address %lx\n",
 878                         (unsigned long)page);
 879
 880         return row;
 881 }
 882 EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page);
 883
 884 const char *edac_layer_name[] = {
 885         [EDAC_MC_LAYER_BRANCH] = "branch",
 886         [EDAC_MC_LAYER_CHANNEL] = "channel",
 887         [EDAC_MC_LAYER_SLOT] = "slot",
 888         [EDAC_MC_LAYER_CHIP_SELECT] = "csrow",
 889         [EDAC_MC_LAYER_ALL_MEM] = "memory",
 890 };
 891 EXPORT_SYMBOL_GPL(edac_layer_name);
 892
 893 static void edac_inc_ce_error(struct mem_ctl_info *mci,
 894                               bool enable_per_layer_report,
 895                               const int pos[EDAC_MAX_LAYERS],
 896                               const u16 count)
 897 {
 898         int i, index = 0;
 899
 900         mci->ce_mc += count;
 901
 902         if (!enable_per_layer_report) {
 903                 mci->ce_noinfo_count += count;
 904                 return;
 905         }
 906
 907         for (i = 0; i < mci->n_layers; i++) {
 908                 if (pos[i] < 0)
 909                         break;
 910                 index += pos[i];
 911                 mci->ce_per_layer[i][index] += count;
 912
 913                 if (i < mci->n_layers - 1)
 914                         index *= mci->layers[i + 1].size;
 915         }
 916 }
 917
 918 static void edac_inc_ue_error(struct mem_ctl_info *mci,
 919                                     bool enable_per_layer_report,
 920                                     const int pos[EDAC_MAX_LAYERS],
 921                                     const u16 count)
 922 {
 923         int i, index = 0;
 924
 925         mci->ue_mc += count;
 926
 927         if (!enable_per_layer_report) {
 928                 mci->ce_noinfo_count += count;
 929                 return;
 930         }
 931
 932         for (i = 0; i < mci->n_layers; i++) {
 933                 if (pos[i] < 0)
 934                         break;
 935                 index += pos[i];
 936                 mci->ue_per_layer[i][index] += count;
 937
 938                 if (i < mci->n_layers - 1)
 939                         index *= mci->layers[i + 1].size;
 940         }
 941 }
 942
 943 static void edac_ce_error(struct mem_ctl_info *mci,
 944                           const u16 error_count,
 945                           const int pos[EDAC_MAX_LAYERS],
 946                           const char *msg,
 947                           const char *location,
 948                           const char *label,
 949                           const char *detail,
 950                           const char *other_detail,
 951                           const bool enable_per_layer_report,
 952                           const unsigned long page_frame_number,
 953                           const unsigned long offset_in_page,
 954                           long grain)
 955 {
 956         unsigned long remapped_page;
 957         char *msg_aux = "";
 958
 959         if (*msg)
 960                 msg_aux = " ";
 961
 962         if (edac_mc_get_log_ce()) {
 963                 if (other_detail && *other_detail)
 964                         edac_mc_printk(mci, KERN_WARNING,
 965                                        "%d CE %s%son %s (%s %s - %s)\n",
 966                                        error_count, msg, msg_aux, label,
 967                                        location, detail, other_detail);
 968                 else
 969                         edac_mc_printk(mci, KERN_WARNING,
 970                                        "%d CE %s%son %s (%s %s)\n",
 971                                        error_count, msg, msg_aux, label,
 972                                        location, detail);
 973         }
 974         edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count);
 975
 976         if (mci->scrub_mode == SCRUB_SW_SRC) {
 977                 /*
 978                         * Some memory controllers (called MCs below) can remap
 979                         * memory so that it is still available at a different
 980                         * address when PCI devices map into memory.
 981                         * MC's that can't do this, lose the memory where PCI
 982                         * devices are mapped. This mapping is MC-dependent
 983                         * and so we call back into the MC driver for it to
 984                         * map the MC page to a physical (CPU) page which can
 985                         * then be mapped to a virtual page - which can then
 986                         * be scrubbed.
 987                         */
 988                 remapped_page = mci->ctl_page_to_phys ?
 989                         mci->ctl_page_to_phys(mci, page_frame_number) :
 990                         page_frame_number;
 991
 992                 edac_mc_scrub_block(remapped_page,
 993                                         offset_in_page, grain);
 994         }
 995 }
 996
 997 static void edac_ue_error(struct mem_ctl_info *mci,
 998                           const u16 error_count,
 999                           const int pos[EDAC_MAX_LAYERS],
1000                           const char *msg,
1001                           const char *location,
1002                           const char *label,
1003                           const char *detail,
1004                           const char *other_detail,
1005                           const bool enable_per_layer_report)
1006 {
1007         char *msg_aux = "";
1008
1009         if (*msg)
1010                 msg_aux = " ";
1011
1012         if (edac_mc_get_log_ue()) {
1013                 if (other_detail && *other_detail)
1014                         edac_mc_printk(mci, KERN_WARNING,
1015                                        "%d UE %s%son %s (%s %s - %s)\n",
1016                                        error_count, msg, msg_aux, label,
1017                                        location, detail, other_detail);
1018                 else
1019                         edac_mc_printk(mci, KERN_WARNING,
1020                                        "%d UE %s%son %s (%s %s)\n",
1021                                        error_count, msg, msg_aux, label,
1022                                        location, detail);
1023         }
1024
1025         if (edac_mc_get_panic_on_ue()) {
1026                 if (other_detail && *other_detail)
1027                         panic("UE %s%son %s (%s%s - %s)\n",
1028                               msg, msg_aux, label, location, detail, other_detail);
1029                 else
1030                         panic("UE %s%son %s (%s%s)\n",
1031                               msg, msg_aux, label, location, detail);
1032         }
1033
1034         edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count);
1035 }
1036
1037 /**
1038  * edac_raw_mc_handle_error - reports a memory event to userspace without doing
1039  *                            anything to discover the error location
1040  *
1041  * @type:               severity of the error (CE/UE/Fatal)
1042  * @mci:                a struct mem_ctl_info pointer
1043  * @e:                  error description
1044  *
1045  * This raw function is used internally by edac_mc_handle_error(). It should
1046  * only be called directly when the hardware error come directly from BIOS,
1047  * like in the case of APEI GHES driver.
1048  */
1049 void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type,
1050                               struct mem_ctl_info *mci,
1051                               struct edac_raw_error_desc *e)
1052 {
1053         char detail[80];
1054         int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
1055
1056         /* Memory type dependent details about the error */
1057         if (type == HW_EVENT_ERR_CORRECTED) {
1058                 snprintf(detail, sizeof(detail),
1059                         "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx",
1060                         e->page_frame_number, e->offset_in_page,
1061                         e->grain, e->syndrome);
1062                 edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label,
1063                               detail, e->other_detail, e->enable_per_layer_report,
1064                               e->page_frame_number, e->offset_in_page, e->grain);
1065         } else {
1066                 snprintf(detail, sizeof(detail),
1067                         "page:0x%lx offset:0x%lx grain:%ld",
1068                         e->page_frame_number, e->offset_in_page, e->grain);
1069
1070                 edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label,
1071                               detail, e->other_detail, e->enable_per_layer_report);
1072         }
1073
1074
1075 }
1076 EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error);
1077
1078 /**
1079  * edac_mc_handle_error - reports a memory event to userspace
1080  *
1081  * @type:               severity of the error (CE/UE/Fatal)
1082  * @mci:                a struct mem_ctl_info pointer
1083  * @error_count:        Number of errors of the same type
1084  * @page_frame_number:  mem page where the error occurred
1085  * @offset_in_page:     offset of the error inside the page
1086  * @syndrome:           ECC syndrome
1087  * @top_layer:          Memory layer[0] position
1088  * @mid_layer:          Memory layer[1] position
1089  * @low_layer:          Memory layer[2] position
1090  * @msg:                Message meaningful to the end users that
1091  *                      explains the event
1092  * @other_detail:       Technical details about the event that
1093  *                      may help hardware manufacturers and
1094  *                      EDAC developers to analyse the event
1095  */
1096 void edac_mc_handle_error(const enum hw_event_mc_err_type type,
1097                           struct mem_ctl_info *mci,
1098                           const u16 error_count,
1099                           const unsigned long page_frame_number,
1100                           const unsigned long offset_in_page,
1101                           const unsigned long syndrome,
1102                           const int top_layer,
1103                           const int mid_layer,
1104                           const int low_layer,
1105                           const char *msg,
1106                           const char *other_detail)
1107 {
1108         char *p;
1109         int row = -1, chan = -1;
1110         int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer };
1111         int i, n_labels = 0;
1112         u8 grain_bits;
1113         struct edac_raw_error_desc *e = &mci->error_desc;
1114
1115         edac_dbg(3, "MC%d\n", mci->mc_idx);
1116
1117         /* Fills the error report buffer */
1118         memset(e, 0, sizeof (*e));
1119         e->error_count = error_count;
1120         e->top_layer = top_layer;
1121         e->mid_layer = mid_layer;
1122         e->low_layer = low_layer;
1123         e->page_frame_number = page_frame_number;
1124         e->offset_in_page = offset_in_page;
1125         e->syndrome = syndrome;
1126         e->msg = msg;
1127         e->other_detail = other_detail;
1128
1129         /*
1130          * Check if the event report is consistent and if the memory
1131          * location is known. If it is known, enable_per_layer_report will be
1132          * true, the DIMM(s) label info will be filled and the per-layer
1133          * error counters will be incremented.
1134          */
1135         for (i = 0; i < mci->n_layers; i++) {
1136                 if (pos[i] >= (int)mci->layers[i].size) {
1137
1138                         edac_mc_printk(mci, KERN_ERR,
1139                                        "INTERNAL ERROR: %s value is out of range (%d >= %d)\n",
1140                                        edac_layer_name[mci->layers[i].type],
1141                                        pos[i], mci->layers[i].size);
1142                         /*
1143                          * Instead of just returning it, let's use what's
1144                          * known about the error. The increment routines and
1145                          * the DIMM filter logic will do the right thing by
1146                          * pointing the likely damaged DIMMs.
1147                          */
1148                         pos[i] = -1;
1149                 }
1150                 if (pos[i] >= 0)
1151                         e->enable_per_layer_report = true;
1152         }
1153
1154         /*
1155          * Get the dimm label/grain that applies to the match criteria.
1156          * As the error algorithm may not be able to point to just one memory
1157          * stick, the logic here will get all possible labels that could
1158          * pottentially be affected by the error.
1159          * On FB-DIMM memory controllers, for uncorrected errors, it is common
1160          * to have only the MC channel and the MC dimm (also called "branch")
1161          * but the channel is not known, as the memory is arranged in pairs,
1162          * where each memory belongs to a separate channel within the same
1163          * branch.
1164          */
1165         p = e->label;
1166         *p = '\0';
1167
1168         for (i = 0; i < mci->tot_dimms; i++) {
1169                 struct dimm_info *dimm = mci->dimms[i];
1170
1171                 if (top_layer >= 0 && top_layer != dimm->location[0])
1172                         continue;
1173                 if (mid_layer >= 0 && mid_layer != dimm->location[1])
1174                         continue;
1175                 if (low_layer >= 0 && low_layer != dimm->location[2])
1176                         continue;
1177
1178                 /* get the max grain, over the error match range */
1179                 if (dimm->grain > e->grain)
1180                         e->grain = dimm->grain;
1181
1182                 /*
1183                  * If the error is memory-controller wide, there's no need to
1184                  * seek for the affected DIMMs because the whole
1185                  * channel/memory controller/...  may be affected.
1186                  * Also, don't show errors for empty DIMM slots.
1187                  */
1188                 if (e->enable_per_layer_report && dimm->nr_pages) {
1189                         if (n_labels >= EDAC_MAX_LABELS) {
1190                                 e->enable_per_layer_report = false;
1191                                 break;
1192                         }
1193                         n_labels++;
1194                         if (p != e->label) {
1195                                 strcpy(p, OTHER_LABEL);
1196                                 p += strlen(OTHER_LABEL);
1197                         }
1198                         strcpy(p, dimm->label);
1199                         p += strlen(p);
1200                         *p = '\0';
1201
1202                         /*
1203                          * get csrow/channel of the DIMM, in order to allow
1204                          * incrementing the compat API counters
1205                          */
1206                         edac_dbg(4, "%s csrows map: (%d,%d)\n",
1207                                  mci->csbased ? "rank" : "dimm",
1208                                  dimm->csrow, dimm->cschannel);
1209                         if (row == -1)
1210                                 row = dimm->csrow;
1211                         else if (row >= 0 && row != dimm->csrow)
1212                                 row = -2;
1213
1214                         if (chan == -1)
1215                                 chan = dimm->cschannel;
1216                         else if (chan >= 0 && chan != dimm->cschannel)
1217                                 chan = -2;
1218                 }
1219         }
1220
1221         if (!e->enable_per_layer_report) {
1222                 strcpy(e->label, "any memory");
1223         } else {
1224                 edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan);
1225                 if (p == e->label)
1226                         strcpy(e->label, "unknown memory");
1227                 if (type == HW_EVENT_ERR_CORRECTED) {
1228                         if (row >= 0) {
1229                                 mci->csrows[row]->ce_count += error_count;
1230                                 if (chan >= 0)
1231                                         mci->csrows[row]->channels[chan]->ce_count += error_count;
1232                         }
1233                 } else
1234                         if (row >= 0)
1235                                 mci->csrows[row]->ue_count += error_count;
1236         }
1237
1238         /* Fill the RAM location data */
1239         p = e->location;
1240
1241         for (i = 0; i < mci->n_layers; i++) {
1242                 if (pos[i] < 0)
1243                         continue;
1244
1245                 p += sprintf(p, "%s:%d ",
1246                              edac_layer_name[mci->layers[i].type],
1247                              pos[i]);
1248         }
1249         if (p > e->location)
1250                 *(p - 1) = '\0';
1251
1252         /* Report the error via the trace interface */
1253         grain_bits = fls_long(e->grain) + 1;
1254         trace_mc_event(type, e->msg, e->label, e->error_count,
1255                        mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
1256                        (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
1257                        grain_bits, e->syndrome, e->other_detail);
1258
1259         edac_raw_mc_handle_error(type, mci, e);
1260 }
1261 EXPORT_SYMBOL_GPL(edac_mc_handle_error);