drivers/edac/edac_mce_amd.c

   1 #include <linux/module.h>
   2 #include "edac_mce_amd.h"
   3
   4 static bool report_gart_errors;
   5 static void (*nb_bus_decoder)(int node_id, struct err_regs *regs, int ecc_type);
   6
   7 void amd_report_gart_errors(bool v)
   8 {
   9         report_gart_errors = v;
  10 }
  11 EXPORT_SYMBOL_GPL(amd_report_gart_errors);
  12
  13 void amd_register_ecc_decoder(void (*f)(int, struct err_regs *, int))
  14 {
  15         nb_bus_decoder = f;
  16 }
  17 EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
  18
  19 void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *, int))
  20 {
  21         if (nb_bus_decoder) {
  22                 WARN_ON(nb_bus_decoder != f);
  23
  24                 nb_bus_decoder = NULL;
  25         }
  26 }
  27 EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
  28
  29 /*
  30  * string representation for the different MCA reported error types, see F3x48
  31  * or MSR0000_0411.
  32  */
  33 const char *tt_msgs[] = {        /* transaction type */
  34         "instruction",
  35         "data",
  36         "generic",
  37         "reserved"
  38 };
  39 EXPORT_SYMBOL_GPL(tt_msgs);
  40
  41 const char *ll_msgs[] = {       /* cache level */
  42         "L0",
  43         "L1",
  44         "L2",
  45         "L3/generic"
  46 };
  47 EXPORT_SYMBOL_GPL(ll_msgs);
  48
  49 const char *rrrr_msgs[] = {
  50         "generic",
  51         "generic read",
  52         "generic write",
  53         "data read",
  54         "data write",
  55         "inst fetch",
  56         "prefetch",
  57         "evict",
  58         "snoop",
  59         "reserved RRRR= 9",
  60         "reserved RRRR= 10",
  61         "reserved RRRR= 11",
  62         "reserved RRRR= 12",
  63         "reserved RRRR= 13",
  64         "reserved RRRR= 14",
  65         "reserved RRRR= 15"
  66 };
  67 EXPORT_SYMBOL_GPL(rrrr_msgs);
  68
  69 const char *pp_msgs[] = {       /* participating processor */
  70         "local node originated (SRC)",
  71         "local node responded to request (RES)",
  72         "local node observed as 3rd party (OBS)",
  73         "generic"
  74 };
  75 EXPORT_SYMBOL_GPL(pp_msgs);
  76
  77 const char *to_msgs[] = {
  78         "no timeout",
  79         "timed out"
  80 };
  81 EXPORT_SYMBOL_GPL(to_msgs);
  82
  83 const char *ii_msgs[] = {       /* memory or i/o */
  84         "mem access",
  85         "reserved",
  86         "i/o access",
  87         "generic"
  88 };
  89 EXPORT_SYMBOL_GPL(ii_msgs);
  90
  91 /*
  92  * Map the 4 or 5 (family-specific) bits of Extended Error code to the
  93  * string table.
  94  */
  95 const char *ext_msgs[] = {
  96         "K8 ECC error",                                 /* 0_0000b */
  97         "CRC error on link",                            /* 0_0001b */
  98         "Sync error packets on link",                   /* 0_0010b */
  99         "Master Abort during link operation",           /* 0_0011b */
 100         "Target Abort during link operation",           /* 0_0100b */
 101         "Invalid GART PTE entry during table walk",     /* 0_0101b */
 102         "Unsupported atomic RMW command received",      /* 0_0110b */
 103         "WDT error: NB transaction timeout",            /* 0_0111b */
 104         "ECC/ChipKill ECC error",                       /* 0_1000b */
 105         "SVM DEV Error",                                /* 0_1001b */
 106         "Link Data error",                              /* 0_1010b */
 107         "Link/L3/Probe Filter Protocol error",          /* 0_1011b */
 108         "NB Internal Arrays Parity error",              /* 0_1100b */
 109         "DRAM Address/Control Parity error",            /* 0_1101b */
 110         "Link Transmission error",                      /* 0_1110b */
 111         "GART/DEV Table Walk Data error"                /* 0_1111b */
 112         "Res 0x100 error",                              /* 1_0000b */
 113         "Res 0x101 error",                              /* 1_0001b */
 114         "Res 0x102 error",                              /* 1_0010b */
 115         "Res 0x103 error",                              /* 1_0011b */
 116         "Res 0x104 error",                              /* 1_0100b */
 117         "Res 0x105 error",                              /* 1_0101b */
 118         "Res 0x106 error",                              /* 1_0110b */
 119         "Res 0x107 error",                              /* 1_0111b */
 120         "Res 0x108 error",                              /* 1_1000b */
 121         "Res 0x109 error",                              /* 1_1001b */
 122         "Res 0x10A error",                              /* 1_1010b */
 123         "Res 0x10B error",                              /* 1_1011b */
 124         "ECC error in L3 Cache Data",                   /* 1_1100b */
 125         "L3 Cache Tag error",                           /* 1_1101b */
 126         "L3 Cache LRU Parity error",                    /* 1_1110b */
 127         "Probe Filter error"                            /* 1_1111b */
 128 };
 129 EXPORT_SYMBOL_GPL(ext_msgs);
 130
 131 void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
 132 {
 133         int ecc;
 134         u32 ec  = ERROR_CODE(regs->nbsl);
 135         u32 xec = EXT_ERROR_CODE(regs->nbsl);
 136
 137         if (!handle_errors)
 138                 return;
 139
 140         pr_emerg(" Northbridge Error, node %d", node_id);
 141
 142         /*
 143          * F10h, revD can disable ErrCpu[3:0] so check that first and also the
 144          * value encoding has changed so interpret those differently
 145          */
 146         if ((boot_cpu_data.x86 == 0x10) &&
 147             (boot_cpu_data.x86_model > 8)) {
 148                 if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
 149                         pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
 150         } else {
 151                 pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));
 152         }
 153
 154         pr_emerg(" Error: %sorrected",
 155                  ((regs->nbsh & K8_NBSH_UC_ERR) ? "Unc" : "C"));
 156         pr_cont(", Report Error: %s",
 157                  ((regs->nbsh & K8_NBSH_ERR_EN) ? "yes" : "no"));
 158         pr_cont(", MiscV: %svalid, CPU context corrupt: %s",
 159                 ((regs->nbsh & K8_NBSH_MISCV) ? "" : "In"),
 160                 ((regs->nbsh & K8_NBSH_PCC)   ? "yes" : "no"));
 161
 162         /* do the two bits[14:13] together */
 163         ecc = regs->nbsh & (0x3 << 13);
 164         if (ecc)
 165                 pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
 166
 167         pr_cont("\n");
 168
 169         if (TLB_ERROR(ec)) {
 170                 /*
 171                  * GART errors are intended to help graphics driver developers
 172                  * to detect bad GART PTEs. It is recommended by AMD to disable
 173                  * GART table walk error reporting by default[1] (currently
 174                  * being disabled in mce_cpu_quirks()) and according to the
 175                  * comment in mce_cpu_quirks(), such GART errors can be
 176                  * incorrectly triggered. We may see these errors anyway and
 177                  * unless requested by the user, they won't be reported.
 178                  *
 179                  * [1] section 13.10.1 on BIOS and Kernel Developers Guide for
 180                  *     AMD NPT family 0Fh processors
 181                  */
 182                 if (!report_gart_errors)
 183                         return;
 184
 185                 pr_emerg(" GART TLB error, Transaction: %s, Cache Level %s\n",
 186                          TT_MSG(ec), LL_MSG(ec));
 187         } else if (MEM_ERROR(ec)) {
 188                 pr_emerg(" Memory/Cache error, Transaction: %s, Type: %s,"
 189                          " Cache Level: %s",
 190                          RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
 191         } else if (BUS_ERROR(ec)) {
 192                 pr_emerg(" Bus (Link/DRAM) error\n");
 193                 if (nb_bus_decoder)
 194                         nb_bus_decoder(node_id, regs, ecc);
 195         } else {
 196                 /* shouldn't reach here! */
 197                 pr_warning("%s: unknown MCE error 0x%x\n", __func__, ec);
 198         }
 199
 200         pr_emerg("%s.\n", EXT_ERR_MSG(xec));
 201 }
 202 EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
 203
 204 void decode_mce(struct mce *m)
 205 {
 206         struct err_regs regs;
 207         int node;
 208
 209         if (m->bank != 4)
 210                 return;
 211
 212         regs.nbsl  = (u32) m->status;
 213         regs.nbsh  = (u32)(m->status >> 32);
 214         regs.nbeal = (u32) m->addr;
 215         regs.nbeah = (u32)(m->addr >> 32);
 216         node       = topology_cpu_node_id(m->extcpu);
 217
 218         amd_decode_nb_mce(node, &regs, 1);
 219 }