1 #include <linux/module.h>
2 #include "edac_mce_amd.h"
4 static bool report_gart_errors;
5 static void (*nb_bus_decoder)(int node_id, struct err_regs *regs);
7 void amd_report_gart_errors(bool v)
9 report_gart_errors = v;
11 EXPORT_SYMBOL_GPL(amd_report_gart_errors);
13 void amd_register_ecc_decoder(void (*f)(int, struct err_regs *))
17 EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
19 void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *))
22 WARN_ON(nb_bus_decoder != f);
24 nb_bus_decoder = NULL;
27 EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
30 * string representation for the different MCA reported error types, see F3x48
33 const char *tt_msgs[] = { /* transaction type */
39 EXPORT_SYMBOL_GPL(tt_msgs);
41 const char *ll_msgs[] = { /* cache level */
47 EXPORT_SYMBOL_GPL(ll_msgs);
49 const char *rrrr_msgs[] = {
67 EXPORT_SYMBOL_GPL(rrrr_msgs);
69 const char *pp_msgs[] = { /* participating processor */
70 "local node originated (SRC)",
71 "local node responded to request (RES)",
72 "local node observed as 3rd party (OBS)",
75 EXPORT_SYMBOL_GPL(pp_msgs);
77 const char *to_msgs[] = {
81 EXPORT_SYMBOL_GPL(to_msgs);
83 const char *ii_msgs[] = { /* memory or i/o */
89 EXPORT_SYMBOL_GPL(ii_msgs);
92 * Map the 4 or 5 (family-specific) bits of Extended Error code to the
95 const char *ext_msgs[] = {
96 "K8 ECC error", /* 0_0000b */
97 "CRC error on link", /* 0_0001b */
98 "Sync error packets on link", /* 0_0010b */
99 "Master Abort during link operation", /* 0_0011b */
100 "Target Abort during link operation", /* 0_0100b */
101 "Invalid GART PTE entry during table walk", /* 0_0101b */
102 "Unsupported atomic RMW command received", /* 0_0110b */
103 "WDT error: NB transaction timeout", /* 0_0111b */
104 "ECC/ChipKill ECC error", /* 0_1000b */
105 "SVM DEV Error", /* 0_1001b */
106 "Link Data error", /* 0_1010b */
107 "Link/L3/Probe Filter Protocol error", /* 0_1011b */
108 "NB Internal Arrays Parity error", /* 0_1100b */
109 "DRAM Address/Control Parity error", /* 0_1101b */
110 "Link Transmission error", /* 0_1110b */
111 "GART/DEV Table Walk Data error" /* 0_1111b */
112 "Res 0x100 error", /* 1_0000b */
113 "Res 0x101 error", /* 1_0001b */
114 "Res 0x102 error", /* 1_0010b */
115 "Res 0x103 error", /* 1_0011b */
116 "Res 0x104 error", /* 1_0100b */
117 "Res 0x105 error", /* 1_0101b */
118 "Res 0x106 error", /* 1_0110b */
119 "Res 0x107 error", /* 1_0111b */
120 "Res 0x108 error", /* 1_1000b */
121 "Res 0x109 error", /* 1_1001b */
122 "Res 0x10A error", /* 1_1010b */
123 "Res 0x10B error", /* 1_1011b */
124 "ECC error in L3 Cache Data", /* 1_1100b */
125 "L3 Cache Tag error", /* 1_1101b */
126 "L3 Cache LRU Parity error", /* 1_1110b */
127 "Probe Filter error" /* 1_1111b */
129 EXPORT_SYMBOL_GPL(ext_msgs);
131 void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
133 u32 ec = ERROR_CODE(regs->nbsl);
134 u32 xec = EXT_ERROR_CODE(regs->nbsl);
139 pr_emerg(" Northbridge Error, node %d", node_id);
142 * F10h, revD can disable ErrCpu[3:0] so check that first and also the
143 * value encoding has changed so interpret those differently
145 if ((boot_cpu_data.x86 == 0x10) &&
146 (boot_cpu_data.x86_model > 8)) {
147 if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
148 pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
150 pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));
154 pr_emerg("%s.\n", EXT_ERR_MSG(xec));
156 if (BUS_ERROR(ec) && nb_bus_decoder)
157 nb_bus_decoder(node_id, regs);
159 EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
161 static inline void amd_decode_err_code(unsigned int ec)
165 * GART errors are intended to help graphics driver developers
166 * to detect bad GART PTEs. It is recommended by AMD to disable
167 * GART table walk error reporting by default[1] (currently
168 * being disabled in mce_cpu_quirks()) and according to the
169 * comment in mce_cpu_quirks(), such GART errors can be
170 * incorrectly triggered. We may see these errors anyway and
171 * unless requested by the user, they won't be reported.
173 * [1] section 13.10.1 on BIOS and Kernel Developers Guide for
174 * AMD NPT family 0Fh processors
176 if (!report_gart_errors)
179 pr_emerg(" Transaction: %s, Cache Level %s\n",
180 TT_MSG(ec), LL_MSG(ec));
181 } else if (MEM_ERROR(ec)) {
182 pr_emerg(" Transaction: %s, Type: %s, Cache Level: %s",
183 RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
184 } else if (BUS_ERROR(ec)) {
185 pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, "
186 "Participating Processor: %s\n",
187 RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
190 pr_warning("Huh? Unknown MCE error 0x%x\n", ec);
193 void decode_mce(struct mce *m)
195 struct err_regs regs;
198 pr_emerg("MC%d_STATUS: ", m->bank);
200 pr_cont("%sorrected error, report: %s, MiscV: %svalid, "
201 "CPU context corrupt: %s",
202 ((m->status & MCI_STATUS_UC) ? "Unc" : "C"),
203 ((m->status & MCI_STATUS_EN) ? "yes" : "no"),
204 ((m->status & MCI_STATUS_MISCV) ? "" : "in"),
205 ((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
207 /* do the two bits[14:13] together */
208 ecc = m->status & (3ULL << 45);
210 pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
214 amd_decode_err_code(m->status & 0xffff);
217 regs.nbsl = (u32) m->status;
218 regs.nbsh = (u32)(m->status >> 32);
219 regs.nbeal = (u32) m->addr;
220 regs.nbeah = (u32)(m->addr >> 32);
221 node = per_cpu(cpu_llc_id, m->extcpu);
223 amd_decode_nb_mce(node, ®s, 1);