2 * Intel 3000/3010 Memory Controller kernel module
3 * Copyright (C) 2007 Akamai Technologies, Inc.
4 * Shamelessly copied from:
5 * Intel D82875P Memory Controller kernel module
6 * (C) 2003 Linux Networx (http://lnxi.com)
8 * This file may be distributed under the terms of the
9 * GNU General Public License.
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/edac.h>
17 #include "edac_core.h"
19 #define I3000_REVISION "1.1"
21 #define EDAC_MOD_STR "i3000_edac"
24 #define I3000_RANKS_PER_CHANNEL 4
25 #define I3000_CHANNELS 2
27 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
29 #define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */
30 #define I3000_MCHBAR_MASK 0xffffc000
31 #define I3000_MMR_WINDOW_SIZE 16384
33 #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
38 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
44 #define I3000_DEAP_GRAIN (1 << 7)
47 * Helper functions to decode the DEAP/EDEAP hardware registers.
49 * The type promotion here is deliberate; we're deriving an
50 * unsigned long pfn and offset from hardware regs which are u8/u32.
53 static inline unsigned long deap_pfn(u8 edeap, u32 deap)
56 deap |= (edeap & 1) << (32 - PAGE_SHIFT);
60 static inline unsigned long deap_offset(u32 deap)
62 return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
65 static inline int deap_channel(u32 deap)
70 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
72 * 7:0 DRAM ECC Syndrome
75 #define I3000_ERRSTS 0xc8 /* Error Status Register (16b)
78 * 11 MCH Thermal Sensor Event
81 * 9 LOCK to non-DRAM Memory Flag (LCKF)
82 * 8 Received Refresh Timeout Flag (RRTOF)
84 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
85 * 0 Single-bit DRAM ECC Error Flag (DSERR)
87 #define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */
88 #define I3000_ERRSTS_UE 0x0002
89 #define I3000_ERRSTS_CE 0x0001
91 #define I3000_ERRCMD 0xca /* Error Command (16b)
94 * 11 SERR on MCH Thermal Sensor Event
97 * 9 SERR on LOCK to non-DRAM Memory
99 * 8 SERR on DRAM Refresh Timeout
102 * 1 SERR Multi-Bit DRAM ECC Error
104 * 0 SERR on Single-Bit ECC Error
108 /* Intel MMIO register space - device 0 function 0 - MMR space */
110 #define I3000_DRB_SHIFT 25 /* 32MiB grain */
112 #define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
114 * 7:0 Channel 0 DRAM Rank Boundary Address
116 #define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
118 * 7:0 Channel 1 DRAM Rank Boundary Address
121 #define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
124 * 6:4 DRAM odd Rank Attribute
126 * 2:0 DRAM even Rank Attribute
128 * Each attribute defines the page
129 * size of the corresponding rank:
137 #define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
139 static inline unsigned char odd_rank_attrib(unsigned char dra)
141 return (dra & 0x70) >> 4;
144 static inline unsigned char even_rank_attrib(unsigned char dra)
149 #define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
152 * 29 Initialization Complete (IC)
154 * 10:8 Refresh Mode Select (RMS)
156 * 6:4 Mode Select (SMS)
161 #define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
163 * 31 Enhanced Addressing Enable (ENHADE)
171 struct i3000_dev_info {
172 const char *ctl_name;
175 struct i3000_error_info {
183 static const struct i3000_dev_info i3000_devs[] = {
185 .ctl_name = "i3000"},
188 static struct pci_dev *mci_pdev;
189 static int i3000_registered = 1;
190 static struct edac_pci_ctl_info *i3000_pci;
192 static void i3000_get_error_info(struct mem_ctl_info *mci,
193 struct i3000_error_info *info)
195 struct pci_dev *pdev;
197 pdev = to_pci_dev(mci->pdev);
200 * This is a mess because there is no atomic way to read all the
201 * registers at once and the registers can transition from CE being
204 pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
205 if (!(info->errsts & I3000_ERRSTS_BITS))
207 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
208 pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
209 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
210 pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
213 * If the error is the same for both reads then the first set
214 * of reads is valid. If there is a change then there is a CE
215 * with no info and the second set of reads is valid and
218 if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
219 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
220 pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
221 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
225 * Clear any error bits.
226 * (Yes, we really clear bits by writing 1 to them.)
228 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
232 static int i3000_process_error_info(struct mem_ctl_info *mci,
233 struct i3000_error_info *info,
236 int row, multi_chan, channel;
237 unsigned long pfn, offset;
239 multi_chan = mci->csrows[0]->nr_channels - 1;
241 if (!(info->errsts & I3000_ERRSTS_BITS))
247 if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
248 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
250 "UE overwrote CE", "", NULL);
251 info->errsts = info->errsts2;
254 pfn = deap_pfn(info->edeap, info->deap);
255 offset = deap_offset(info->deap);
256 channel = deap_channel(info->deap);
258 row = edac_mc_find_csrow_by_page(mci, pfn);
260 if (info->errsts & I3000_ERRSTS_UE)
261 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
264 "i3000 UE", "", NULL);
266 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
267 pfn, offset, info->derrsyn,
268 row, multi_chan ? channel : 0, -1,
269 "i3000 CE", "", NULL);
274 static void i3000_check(struct mem_ctl_info *mci)
276 struct i3000_error_info info;
278 debugf1("MC%d\n", mci->mc_idx);
279 i3000_get_error_info(mci, &info);
280 i3000_process_error_info(mci, &info, 1);
283 static int i3000_is_interleaved(const unsigned char *c0dra,
284 const unsigned char *c1dra,
285 const unsigned char *c0drb,
286 const unsigned char *c1drb)
291 * If the channels aren't populated identically then
292 * we're not interleaved.
294 for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
295 if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
296 even_rank_attrib(c0dra[i]) !=
297 even_rank_attrib(c1dra[i]))
301 * If the rank boundaries for the two channels are different
302 * then we're not interleaved.
304 for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
305 if (c0drb[i] != c1drb[i])
311 static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
315 struct mem_ctl_info *mci = NULL;
316 struct edac_mc_layer layers[2];
317 unsigned long last_cumul_size, nr_pages;
318 int interleaved, nr_channels;
319 unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
320 unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
321 unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
322 unsigned long mchbar;
323 void __iomem *window;
327 pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
328 mchbar &= I3000_MCHBAR_MASK;
329 window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE);
331 printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
336 c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */
337 c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */
338 c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */
339 c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */
341 for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
342 c0drb[i] = readb(window + I3000_C0DRB + i);
343 c1drb[i] = readb(window + I3000_C1DRB + i);
349 * Figure out how many channels we have.
351 * If we have what the datasheet calls "asymmetric channels"
352 * (essentially the same as what was called "virtual single
353 * channel mode" in the i82875) then it's a single channel as
354 * far as EDAC is concerned.
356 interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
357 nr_channels = interleaved ? 2 : 1;
359 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
360 layers[0].size = I3000_RANKS / nr_channels;
361 layers[0].is_virt_csrow = true;
362 layers[1].type = EDAC_MC_LAYER_CHANNEL;
363 layers[1].size = nr_channels;
364 layers[1].is_virt_csrow = false;
365 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
369 debugf3("MC: init mci\n");
371 mci->pdev = &pdev->dev;
372 mci->mtype_cap = MEM_FLAG_DDR2;
374 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
375 mci->edac_cap = EDAC_FLAG_SECDED;
377 mci->mod_name = EDAC_MOD_STR;
378 mci->mod_ver = I3000_REVISION;
379 mci->ctl_name = i3000_devs[dev_idx].ctl_name;
380 mci->dev_name = pci_name(pdev);
381 mci->edac_check = i3000_check;
382 mci->ctl_page_to_phys = NULL;
385 * The dram rank boundary (DRB) reg values are boundary addresses
386 * for each DRAM rank with a granularity of 32MB. DRB regs are
387 * cumulative; the last one will contain the total memory
388 * contained in all ranks.
390 * If we're in interleaved mode then we're only walking through
391 * the ranks of controller 0, so we double all the values we see.
393 for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
396 struct csrow_info *csrow = mci->csrows[i];
399 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
402 debugf3("MC: (%d) cumul_size 0x%x\n",
404 if (cumul_size == last_cumul_size)
407 csrow->first_page = last_cumul_size;
408 csrow->last_page = cumul_size - 1;
409 nr_pages = cumul_size - last_cumul_size;
410 last_cumul_size = cumul_size;
412 for (j = 0; j < nr_channels; j++) {
413 struct dimm_info *dimm = csrow->channels[j]->dimm;
415 dimm->nr_pages = nr_pages / nr_channels;
416 dimm->grain = I3000_DEAP_GRAIN;
417 dimm->mtype = MEM_DDR2;
418 dimm->dtype = DEV_UNKNOWN;
419 dimm->edac_mode = EDAC_UNKNOWN;
424 * Clear any error bits.
425 * (Yes, we really clear bits by writing 1 to them.)
427 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
431 if (edac_mc_add_mc(mci)) {
432 debugf3("MC: failed edac_mc_add_mc()\n");
436 /* allocating generic PCI control info */
437 i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
440 "%s(): Unable to create PCI control\n",
443 "%s(): PCI error report via EDAC not setup\n",
447 /* get this far and it's successful */
448 debugf3("MC: success\n");
458 /* returns count (>= 0), or negative on error */
459 static int __devinit i3000_init_one(struct pci_dev *pdev,
460 const struct pci_device_id *ent)
466 if (pci_enable_device(pdev) < 0)
469 rc = i3000_probe1(pdev, ent->driver_data);
471 mci_pdev = pci_dev_get(pdev);
476 static void __devexit i3000_remove_one(struct pci_dev *pdev)
478 struct mem_ctl_info *mci;
483 edac_pci_release_generic_ctl(i3000_pci);
485 mci = edac_mc_del_mc(&pdev->dev);
492 static DEFINE_PCI_DEVICE_TABLE(i3000_pci_tbl) = {
494 PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
498 } /* 0 terminated list. */
501 MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
503 static struct pci_driver i3000_driver = {
504 .name = EDAC_MOD_STR,
505 .probe = i3000_init_one,
506 .remove = __devexit_p(i3000_remove_one),
507 .id_table = i3000_pci_tbl,
510 static int __init i3000_init(void)
516 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
519 pci_rc = pci_register_driver(&i3000_driver);
524 i3000_registered = 0;
525 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
526 PCI_DEVICE_ID_INTEL_3000_HB, NULL);
528 debugf0("i3000 pci_get_device fail\n");
533 pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
535 debugf0("i3000 init fail\n");
544 pci_unregister_driver(&i3000_driver);
548 pci_dev_put(mci_pdev);
553 static void __exit i3000_exit(void)
557 pci_unregister_driver(&i3000_driver);
558 if (!i3000_registered) {
559 i3000_remove_one(mci_pdev);
560 pci_dev_put(mci_pdev);
564 module_init(i3000_init);
565 module_exit(i3000_exit);
567 MODULE_LICENSE("GPL");
568 MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
569 MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
571 module_param(edac_op_state, int, 0444);
572 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");