2 * Intel 5000(P/V/X) class Memory Controllers kernel module
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Douglas Thompson Linux Networx (http://lnxi.com)
10 * This module is based on the following document:
12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://developer.intel.com/design/chipsets/datashts/313070.htm
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/pci_ids.h>
21 #include <linux/slab.h>
22 #include <linux/edac.h>
23 #include <asm/mmzone.h>
25 #include "edac_core.h"
28 * Alter this version for the I5000 module when modifications are made
30 #define I5000_REVISION " Ver: 2.0.12"
31 #define EDAC_MOD_STR "i5000_edac"
33 #define i5000_printk(level, fmt, arg...) \
34 edac_printk(level, "i5000", fmt, ##arg)
36 #define i5000_mc_printk(mci, level, fmt, arg...) \
37 edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
39 #ifndef PCI_DEVICE_ID_INTEL_FBD_0
40 #define PCI_DEVICE_ID_INTEL_FBD_0 0x25F5
42 #ifndef PCI_DEVICE_ID_INTEL_FBD_1
43 #define PCI_DEVICE_ID_INTEL_FBD_1 0x25F6
47 * Function 0: System Address
48 * Function 1: Memory Branch Map, Control, Errors Register
49 * Function 2: FSB Error Registers
51 * All 3 functions of Device 16 (0,1,2) share the SAME DID
53 #define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
55 /* OFFSETS for Function 0 */
57 /* OFFSETS for Function 1 */
60 #define MAXDIMMPERCH 0x57
63 #define RED_ECC_LOCATOR(x) ((x) & 0x3FFFF)
64 #define REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
65 #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3FE00)
73 #define FERR_FAT_FBD 0x98
74 #define NERR_FAT_FBD 0x9C
75 #define EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
76 #define FERR_FAT_FBDCHAN 0x30000000
77 #define FERR_FAT_M3ERR 0x00000004
78 #define FERR_FAT_M2ERR 0x00000002
79 #define FERR_FAT_M1ERR 0x00000001
80 #define FERR_FAT_MASK (FERR_FAT_M1ERR | \
84 #define FERR_NF_FBD 0xA0
86 /* Thermal and SPD or BFD errors */
87 #define FERR_NF_M28ERR 0x01000000
88 #define FERR_NF_M27ERR 0x00800000
89 #define FERR_NF_M26ERR 0x00400000
90 #define FERR_NF_M25ERR 0x00200000
91 #define FERR_NF_M24ERR 0x00100000
92 #define FERR_NF_M23ERR 0x00080000
93 #define FERR_NF_M22ERR 0x00040000
94 #define FERR_NF_M21ERR 0x00020000
96 /* Correctable errors */
97 #define FERR_NF_M20ERR 0x00010000
98 #define FERR_NF_M19ERR 0x00008000
99 #define FERR_NF_M18ERR 0x00004000
100 #define FERR_NF_M17ERR 0x00002000
102 /* Non-Retry or redundant Retry errors */
103 #define FERR_NF_M16ERR 0x00001000
104 #define FERR_NF_M15ERR 0x00000800
105 #define FERR_NF_M14ERR 0x00000400
106 #define FERR_NF_M13ERR 0x00000200
108 /* Uncorrectable errors */
109 #define FERR_NF_M12ERR 0x00000100
110 #define FERR_NF_M11ERR 0x00000080
111 #define FERR_NF_M10ERR 0x00000040
112 #define FERR_NF_M9ERR 0x00000020
113 #define FERR_NF_M8ERR 0x00000010
114 #define FERR_NF_M7ERR 0x00000008
115 #define FERR_NF_M6ERR 0x00000004
116 #define FERR_NF_M5ERR 0x00000002
117 #define FERR_NF_M4ERR 0x00000001
119 #define FERR_NF_UNCORRECTABLE (FERR_NF_M12ERR | \
128 #define FERR_NF_CORRECTABLE (FERR_NF_M20ERR | \
132 #define FERR_NF_DIMM_SPARE (FERR_NF_M27ERR | \
134 #define FERR_NF_THERMAL (FERR_NF_M26ERR | \
138 #define FERR_NF_SPD_PROTOCOL (FERR_NF_M22ERR)
139 #define FERR_NF_NORTH_CRC (FERR_NF_M21ERR)
140 #define FERR_NF_NON_RETRY (FERR_NF_M13ERR | \
144 #define NERR_NF_FBD 0xA4
145 #define FERR_NF_MASK (FERR_NF_UNCORRECTABLE | \
146 FERR_NF_CORRECTABLE | \
147 FERR_NF_DIMM_SPARE | \
149 FERR_NF_SPD_PROTOCOL | \
150 FERR_NF_NORTH_CRC | \
153 #define EMASK_FBD 0xA8
154 #define EMASK_FBD_M28ERR 0x08000000
155 #define EMASK_FBD_M27ERR 0x04000000
156 #define EMASK_FBD_M26ERR 0x02000000
157 #define EMASK_FBD_M25ERR 0x01000000
158 #define EMASK_FBD_M24ERR 0x00800000
159 #define EMASK_FBD_M23ERR 0x00400000
160 #define EMASK_FBD_M22ERR 0x00200000
161 #define EMASK_FBD_M21ERR 0x00100000
162 #define EMASK_FBD_M20ERR 0x00080000
163 #define EMASK_FBD_M19ERR 0x00040000
164 #define EMASK_FBD_M18ERR 0x00020000
165 #define EMASK_FBD_M17ERR 0x00010000
167 #define EMASK_FBD_M15ERR 0x00004000
168 #define EMASK_FBD_M14ERR 0x00002000
169 #define EMASK_FBD_M13ERR 0x00001000
170 #define EMASK_FBD_M12ERR 0x00000800
171 #define EMASK_FBD_M11ERR 0x00000400
172 #define EMASK_FBD_M10ERR 0x00000200
173 #define EMASK_FBD_M9ERR 0x00000100
174 #define EMASK_FBD_M8ERR 0x00000080
175 #define EMASK_FBD_M7ERR 0x00000040
176 #define EMASK_FBD_M6ERR 0x00000020
177 #define EMASK_FBD_M5ERR 0x00000010
178 #define EMASK_FBD_M4ERR 0x00000008
179 #define EMASK_FBD_M3ERR 0x00000004
180 #define EMASK_FBD_M2ERR 0x00000002
181 #define EMASK_FBD_M1ERR 0x00000001
183 #define ENABLE_EMASK_FBD_FATAL_ERRORS (EMASK_FBD_M1ERR | \
187 #define ENABLE_EMASK_FBD_UNCORRECTABLE (EMASK_FBD_M4ERR | \
196 #define ENABLE_EMASK_FBD_CORRECTABLE (EMASK_FBD_M17ERR | \
200 #define ENABLE_EMASK_FBD_DIMM_SPARE (EMASK_FBD_M27ERR | \
202 #define ENABLE_EMASK_FBD_THERMALS (EMASK_FBD_M26ERR | \
206 #define ENABLE_EMASK_FBD_SPD_PROTOCOL (EMASK_FBD_M22ERR)
207 #define ENABLE_EMASK_FBD_NORTH_CRC (EMASK_FBD_M21ERR)
208 #define ENABLE_EMASK_FBD_NON_RETRY (EMASK_FBD_M15ERR | \
212 #define ENABLE_EMASK_ALL (ENABLE_EMASK_FBD_NON_RETRY | \
213 ENABLE_EMASK_FBD_NORTH_CRC | \
214 ENABLE_EMASK_FBD_SPD_PROTOCOL | \
215 ENABLE_EMASK_FBD_THERMALS | \
216 ENABLE_EMASK_FBD_DIMM_SPARE | \
217 ENABLE_EMASK_FBD_FATAL_ERRORS | \
218 ENABLE_EMASK_FBD_CORRECTABLE | \
219 ENABLE_EMASK_FBD_UNCORRECTABLE)
221 #define ERR0_FBD 0xAC
222 #define ERR1_FBD 0xB0
223 #define ERR2_FBD 0xB4
224 #define MCERR_FBD 0xB8
225 #define NRECMEMA 0xBE
226 #define NREC_BANK(x) (((x)>>12) & 0x7)
227 #define NREC_RDWR(x) (((x)>>11) & 1)
228 #define NREC_RANK(x) (((x)>>8) & 0x7)
229 #define NRECMEMB 0xC0
230 #define NREC_CAS(x) (((x)>>16) & 0xFFFFFF)
231 #define NREC_RAS(x) ((x) & 0x7FFF)
232 #define NRECFGLOG 0xC4
233 #define NREEECFBDA 0xC8
234 #define NREEECFBDB 0xCC
235 #define NREEECFBDC 0xD0
236 #define NREEECFBDD 0xD4
237 #define NREEECFBDE 0xD8
240 #define REC_BANK(x) (((x)>>12) & 0x7)
241 #define REC_RDWR(x) (((x)>>11) & 1)
242 #define REC_RANK(x) (((x)>>8) & 0x7)
244 #define REC_CAS(x) (((x)>>16) & 0xFFFFFF)
245 #define REC_RAS(x) ((x) & 0x7FFF)
246 #define RECFGLOG 0xE8
253 /* OFFSETS for Function 2 */
257 * Function 0: Memory Map Branch 0
260 * Function 0: Memory Map Branch 1
262 #define PCI_DEVICE_ID_I5000_BRANCH_0 0x25F5
263 #define PCI_DEVICE_ID_I5000_BRANCH_1 0x25F6
265 #define AMB_PRESENT_0 0x64
266 #define AMB_PRESENT_1 0x66
273 #define CHANNELS_PER_BRANCH (2)
275 /* Defines to extract the vaious fields from the
276 * MTRx - Memory Technology Registers
278 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8))
279 #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4)
280 #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4)
281 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
282 #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1)
283 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
284 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
285 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
286 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
287 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
289 #ifdef CONFIG_EDAC_DEBUG
290 static char *numrow_toString[] = {
297 static char *numcol_toString[] = {
298 "1,024 - 10 columns",
299 "2,048 - 11 columns",
300 "4,096 - 12 columns",
305 /* enables the report of miscellaneous messages as CE errors - default off */
306 static int misc_messages;
308 /* Enumeration of supported devices */
311 I5000V = 1, /* future */
312 I5000X = 2 /* future */
315 /* Device name and register DID (Device ID) */
316 struct i5000_dev_info {
317 const char *ctl_name; /* name for this device */
318 u16 fsb_mapping_errors; /* DID for the branchmap,control */
321 /* Table of devices attributes supported by this driver */
322 static const struct i5000_dev_info i5000_devs[] = {
325 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
329 struct i5000_dimm_info {
330 int megabytes; /* size, 0 means not present */
334 #define MAX_CHANNELS 6 /* max possible channels */
335 #define MAX_CSROWS (8*2) /* max possible csrows per channel */
337 /* driver private data structure */
339 struct pci_dev *system_address; /* 16.0 */
340 struct pci_dev *branchmap_werrors; /* 16.1 */
341 struct pci_dev *fsb_error_regs; /* 16.2 */
342 struct pci_dev *branch_0; /* 21.0 */
343 struct pci_dev *branch_1; /* 22.0 */
345 u16 tolm; /* top of low memory */
346 u64 ambase; /* AMB BAR */
348 u16 mir0, mir1, mir2;
350 u16 b0_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
351 u16 b0_ambpresent0; /* Branch 0, Channel 0 */
352 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
354 u16 b1_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
355 u16 b1_ambpresent0; /* Branch 1, Channel 8 */
356 u16 b1_ambpresent1; /* Branch 1, Channel 1 */
358 /* DIMM information matrix, allocating architecture maximums */
359 struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
361 /* Actual values for this controller */
362 int maxch; /* Max channels */
363 int maxdimmperch; /* Max DIMMs per channel */
366 /* I5000 MCH error information retrieved from Hardware */
367 struct i5000_error_info {
369 /* These registers are always read from the MC */
370 u32 ferr_fat_fbd; /* First Errors Fatal */
371 u32 nerr_fat_fbd; /* Next Errors Fatal */
372 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
373 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
375 /* These registers are input ONLY if there was a Recoverable Error */
376 u32 redmemb; /* Recoverable Mem Data Error log B */
377 u16 recmema; /* Recoverable Mem Error log A */
378 u32 recmemb; /* Recoverable Mem Error log B */
380 /* These registers are input ONLY if there was a
381 * Non-Recoverable Error */
382 u16 nrecmema; /* Non-Recoverable Mem log A */
383 u16 nrecmemb; /* Non-Recoverable Mem log B */
387 static struct edac_pci_ctl_info *i5000_pci;
390 * i5000_get_error_info Retrieve the hardware error information from
391 * the hardware and cache it in the 'info'
394 static void i5000_get_error_info(struct mem_ctl_info *mci,
395 struct i5000_error_info *info)
397 struct i5000_pvt *pvt;
402 /* read in the 1st FATAL error register */
403 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
405 /* Mask only the bits that the doc says are valid
407 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
409 /* If there is an error, then read in the */
410 /* NEXT FATAL error register and the Memory Error Log Register A */
411 if (value & FERR_FAT_MASK) {
412 info->ferr_fat_fbd = value;
414 /* harvest the various error data we need */
415 pci_read_config_dword(pvt->branchmap_werrors,
416 NERR_FAT_FBD, &info->nerr_fat_fbd);
417 pci_read_config_word(pvt->branchmap_werrors,
418 NRECMEMA, &info->nrecmema);
419 pci_read_config_word(pvt->branchmap_werrors,
420 NRECMEMB, &info->nrecmemb);
422 /* Clear the error bits, by writing them back */
423 pci_write_config_dword(pvt->branchmap_werrors,
424 FERR_FAT_FBD, value);
426 info->ferr_fat_fbd = 0;
427 info->nerr_fat_fbd = 0;
432 /* read in the 1st NON-FATAL error register */
433 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
435 /* If there is an error, then read in the 1st NON-FATAL error
436 * register as well */
437 if (value & FERR_NF_MASK) {
438 info->ferr_nf_fbd = value;
440 /* harvest the various error data we need */
441 pci_read_config_dword(pvt->branchmap_werrors,
442 NERR_NF_FBD, &info->nerr_nf_fbd);
443 pci_read_config_word(pvt->branchmap_werrors,
444 RECMEMA, &info->recmema);
445 pci_read_config_dword(pvt->branchmap_werrors,
446 RECMEMB, &info->recmemb);
447 pci_read_config_dword(pvt->branchmap_werrors,
448 REDMEMB, &info->redmemb);
450 /* Clear the error bits, by writing them back */
451 pci_write_config_dword(pvt->branchmap_werrors,
454 info->ferr_nf_fbd = 0;
455 info->nerr_nf_fbd = 0;
463 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
464 * struct i5000_error_info *info,
465 * int handle_errors);
467 * handle the Intel FATAL errors, if any
469 static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
470 struct i5000_error_info *info,
473 char msg[EDAC_MC_LABEL_LEN + 1 + 160];
474 char *specific = NULL;
483 /* mask off the Error bits that are possible */
484 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
486 return; /* if no error, return now */
488 branch = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
491 /* Use the NON-Recoverable macros to extract data */
492 bank = NREC_BANK(info->nrecmema);
493 rank = NREC_RANK(info->nrecmema);
494 rdwr = NREC_RDWR(info->nrecmema);
495 ras = NREC_RAS(info->nrecmemb);
496 cas = NREC_CAS(info->nrecmemb);
498 debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
499 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
500 rank, channel, channel + 1, branch >> 1, bank,
501 rdwr ? "Write" : "Read", ras, cas);
503 /* Only 1 bit will be on */
506 specific = "Alert on non-redundant retry or fast "
510 specific = "Northbound CRC error on non-redundant "
518 * This error is generated to inform that the intelligent
519 * throttling is disabled and the temperature passed the
520 * specified middle point. Since this is something the BIOS
521 * should take care of, we'll warn only once to avoid
522 * worthlessly flooding the log.
528 specific = ">Tmid Thermal event with intelligent "
529 "throttling disabled";
534 /* Form out message */
535 snprintf(msg, sizeof(msg),
536 "Bank=%d RAS=%d CAS=%d FATAL Err=0x%x (%s)",
537 bank, ras, cas, allErrors, specific);
539 /* Call the helper to output message */
540 edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 0, 0, 0,
541 branch >> 1, -1, rank,
542 rdwr ? "Write error" : "Read error",
547 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
548 * struct i5000_error_info *info,
549 * int handle_errors);
551 * handle the Intel NON-FATAL errors, if any
553 static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
554 struct i5000_error_info *info,
557 char msg[EDAC_MC_LABEL_LEN + 1 + 170];
558 char *specific = NULL;
570 /* mask off the Error bits that are possible */
571 allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
573 return; /* if no error, return now */
575 /* ONLY ONE of the possible error bits will be set, as per the docs */
576 ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
578 debugf0("\tUncorrected bits= 0x%x\n", ue_errors);
580 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
583 * According with i5000 datasheet, bit 28 has no significance
584 * for errors M4Err-M12Err and M17Err-M21Err, on FERR_NF_FBD
586 channel = branch & 2;
588 bank = NREC_BANK(info->nrecmema);
589 rank = NREC_RANK(info->nrecmema);
590 rdwr = NREC_RDWR(info->nrecmema);
591 ras = NREC_RAS(info->nrecmemb);
592 cas = NREC_CAS(info->nrecmemb);
595 ("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
596 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
597 rank, channel, channel + 1, branch >> 1, bank,
598 rdwr ? "Write" : "Read", ras, cas);
602 specific = "Non-Aliased Uncorrectable Patrol Data ECC";
605 specific = "Non-Aliased Uncorrectable Spare-Copy "
609 specific = "Non-Aliased Uncorrectable Mirrored Demand "
613 specific = "Non-Aliased Uncorrectable Non-Mirrored "
617 specific = "Aliased Uncorrectable Patrol Data ECC";
620 specific = "Aliased Uncorrectable Spare-Copy Data ECC";
623 specific = "Aliased Uncorrectable Mirrored Demand "
627 specific = "Aliased Uncorrectable Non-Mirrored Demand "
631 specific = "Uncorrectable Data ECC on Replay";
635 /* Form out message */
636 snprintf(msg, sizeof(msg),
637 "Rank=%d Bank=%d RAS=%d CAS=%d, UE Err=0x%x (%s)",
638 rank, bank, ras, cas, ue_errors, specific);
640 /* Call the helper to output message */
641 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
642 channel >> 1, -1, rank,
643 rdwr ? "Write error" : "Read error",
647 /* Check correctable errors */
648 ce_errors = allErrors & FERR_NF_CORRECTABLE;
650 debugf0("\tCorrected bits= 0x%x\n", ce_errors);
652 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
655 if (REC_ECC_LOCATOR_ODD(info->redmemb))
658 /* Convert channel to be based from zero, instead of
659 * from branch base of 0 */
662 bank = REC_BANK(info->recmema);
663 rank = REC_RANK(info->recmema);
664 rdwr = REC_RDWR(info->recmema);
665 ras = REC_RAS(info->recmemb);
666 cas = REC_CAS(info->recmemb);
668 debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
669 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
670 rank, channel, branch >> 1, bank,
671 rdwr ? "Write" : "Read", ras, cas);
675 specific = "Correctable Non-Mirrored Demand Data ECC";
678 specific = "Correctable Mirrored Demand Data ECC";
681 specific = "Correctable Spare-Copy Data ECC";
684 specific = "Correctable Patrol Data ECC";
688 /* Form out message */
689 snprintf(msg, sizeof(msg),
690 "Rank=%d Bank=%d RDWR=%s RAS=%d "
691 "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,
692 rdwr ? "Write" : "Read", ras, cas, ce_errors,
695 /* Call the helper to output message */
696 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
697 channel >> 1, channel % 2, rank,
698 rdwr ? "Write error" : "Read error",
705 misc_errors = allErrors & (FERR_NF_NON_RETRY | FERR_NF_NORTH_CRC |
706 FERR_NF_SPD_PROTOCOL | FERR_NF_DIMM_SPARE);
708 switch (misc_errors) {
710 specific = "Non-Retry or Redundant Retry FBD Memory "
711 "Alert or Redundant Fast Reset Timeout";
714 specific = "Non-Retry or Redundant Retry FBD "
715 "Configuration Alert";
718 specific = "Non-Retry or Redundant Retry FBD "
719 "Northbound CRC error on read data";
722 specific = "FBD Northbound CRC error on "
726 specific = "SPD protocol error";
729 specific = "DIMM-spare copy started";
732 specific = "DIMM-spare copy completed";
735 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
737 /* Form out message */
738 snprintf(msg, sizeof(msg),
739 "Err=%#x (%s)", misc_errors, specific);
741 /* Call the helper to output message */
742 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
744 "Misc error", msg, NULL);
749 * i5000_process_error_info Process the error info that is
750 * in the 'info' structure, previously retrieved from hardware
752 static void i5000_process_error_info(struct mem_ctl_info *mci,
753 struct i5000_error_info *info,
756 /* First handle any fatal errors that occurred */
757 i5000_process_fatal_error_info(mci, info, handle_errors);
759 /* now handle any non-fatal errors that occurred */
760 i5000_process_nonfatal_error_info(mci, info, handle_errors);
764 * i5000_clear_error Retrieve any error from the hardware
765 * but do NOT process that error.
766 * Used for 'clearing' out of previous errors
767 * Called by the Core module.
769 static void i5000_clear_error(struct mem_ctl_info *mci)
771 struct i5000_error_info info;
773 i5000_get_error_info(mci, &info);
777 * i5000_check_error Retrieve and process errors reported by the
778 * hardware. Called by the Core module.
780 static void i5000_check_error(struct mem_ctl_info *mci)
782 struct i5000_error_info info;
783 debugf4("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__);
784 i5000_get_error_info(mci, &info);
785 i5000_process_error_info(mci, &info, 1);
789 * i5000_get_devices Find and perform 'get' operation on the MCH's
790 * device/functions we want to reference for this driver
792 * Need to 'get' device 16 func 1 and func 2
794 static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
796 //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx];
797 struct i5000_pvt *pvt;
798 struct pci_dev *pdev;
802 /* Attempt to 'get' the MCH register we want */
805 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
806 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
808 /* End of list, leave */
810 i5000_printk(KERN_ERR,
811 "'system address,Process Bus' "
813 "vendor 0x%x device 0x%x FUNC 1 "
816 PCI_DEVICE_ID_INTEL_I5000_DEV16);
821 /* Scan for device 16 func 1 */
822 if (PCI_FUNC(pdev->devfn) == 1)
826 pvt->branchmap_werrors = pdev;
828 /* Attempt to 'get' the MCH register we want */
831 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
832 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
835 i5000_printk(KERN_ERR,
836 "MC: 'branchmap,control,errors' "
838 "vendor 0x%x device 0x%x Func 2 "
841 PCI_DEVICE_ID_INTEL_I5000_DEV16);
843 pci_dev_put(pvt->branchmap_werrors);
847 /* Scan for device 16 func 1 */
848 if (PCI_FUNC(pdev->devfn) == 2)
852 pvt->fsb_error_regs = pdev;
854 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
855 pci_name(pvt->system_address),
856 pvt->system_address->vendor, pvt->system_address->device);
857 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
858 pci_name(pvt->branchmap_werrors),
859 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
860 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
861 pci_name(pvt->fsb_error_regs),
862 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
865 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
866 PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
869 i5000_printk(KERN_ERR,
870 "MC: 'BRANCH 0' device not found:"
871 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
872 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
874 pci_dev_put(pvt->branchmap_werrors);
875 pci_dev_put(pvt->fsb_error_regs);
879 pvt->branch_0 = pdev;
881 /* If this device claims to have more than 2 channels then
882 * fetch Branch 1's information
884 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
886 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
887 PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
890 i5000_printk(KERN_ERR,
891 "MC: 'BRANCH 1' device not found:"
892 "vendor 0x%x device 0x%x Func 0 "
895 PCI_DEVICE_ID_I5000_BRANCH_1);
897 pci_dev_put(pvt->branchmap_werrors);
898 pci_dev_put(pvt->fsb_error_regs);
899 pci_dev_put(pvt->branch_0);
903 pvt->branch_1 = pdev;
910 * i5000_put_devices 'put' all the devices that we have
913 static void i5000_put_devices(struct mem_ctl_info *mci)
915 struct i5000_pvt *pvt;
919 pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */
920 pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */
921 pci_dev_put(pvt->branch_0); /* DEV 21 */
923 /* Only if more than 2 channels do we release the second branch */
924 if (pvt->maxch >= CHANNELS_PER_BRANCH)
925 pci_dev_put(pvt->branch_1); /* DEV 22 */
929 * determine_amb_resent
931 * the information is contained in NUM_MTRS different registers
932 * determineing which of the NUM_MTRS requires knowing
933 * which channel is in question
935 * 2 branches, each with 2 channels
936 * b0_ambpresent0 for channel '0'
937 * b0_ambpresent1 for channel '1'
938 * b1_ambpresent0 for channel '2'
939 * b1_ambpresent1 for channel '3'
941 static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
945 if (channel < CHANNELS_PER_BRANCH) {
947 amb_present = pvt->b0_ambpresent1;
949 amb_present = pvt->b0_ambpresent0;
952 amb_present = pvt->b1_ambpresent1;
954 amb_present = pvt->b1_ambpresent0;
961 * determine_mtr(pvt, csrow, channel)
963 * return the proper MTR register as determine by the csrow and channel desired
965 static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel)
969 if (channel < CHANNELS_PER_BRANCH)
970 mtr = pvt->b0_mtr[csrow >> 1];
972 mtr = pvt->b1_mtr[csrow >> 1];
979 static void decode_mtr(int slot_row, u16 mtr)
983 ans = MTR_DIMMS_PRESENT(mtr);
985 debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr,
986 ans ? "Present" : "NOT Present");
990 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
991 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
992 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
993 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
994 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
997 static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel,
998 struct i5000_dimm_info *dinfo)
1001 int amb_present_reg;
1004 mtr = determine_mtr(pvt, csrow, channel);
1005 if (MTR_DIMMS_PRESENT(mtr)) {
1006 amb_present_reg = determine_amb_present_reg(pvt, channel);
1008 /* Determine if there is a DIMM present in this DIMM slot */
1009 if (amb_present_reg & (1 << (csrow >> 1))) {
1010 dinfo->dual_rank = MTR_DIMM_RANK(mtr);
1012 if (!((dinfo->dual_rank == 0) &&
1013 ((csrow & 0x1) == 0x1))) {
1014 /* Start with the number of bits for a Bank
1016 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
1017 /* Add thenumber of ROW bits */
1018 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
1019 /* add the number of COLUMN bits */
1020 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
1022 addrBits += 6; /* add 64 bits per DIMM */
1023 addrBits -= 20; /* divide by 2^^20 */
1024 addrBits -= 3; /* 8 bits per bytes */
1026 dinfo->megabytes = 1 << addrBits;
1033 * calculate_dimm_size
1035 * also will output a DIMM matrix map, if debug is enabled, for viewing
1036 * how the DIMMs are populated
1038 static void calculate_dimm_size(struct i5000_pvt *pvt)
1040 struct i5000_dimm_info *dinfo;
1041 int csrow, max_csrows;
1042 char *p, *mem_buffer;
1046 /* ================= Generate some debug output ================= */
1048 mem_buffer = p = kmalloc(space, GFP_KERNEL);
1050 i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
1051 __FILE__, __func__);
1055 n = snprintf(p, space, "\n");
1059 /* Scan all the actual CSROWS (which is # of DIMMS * 2)
1060 * and calculate the information for each DIMM
1061 * Start with the highest csrow first, to display it first
1062 * and work toward the 0th csrow
1064 max_csrows = pvt->maxdimmperch * 2;
1065 for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
1067 /* on an odd csrow, first output a 'boundary' marker,
1068 * then reset the message buffer */
1070 n = snprintf(p, space, "---------------------------"
1071 "--------------------------------");
1074 debugf2("%s\n", mem_buffer);
1078 n = snprintf(p, space, "csrow %2d ", csrow);
1082 for (channel = 0; channel < pvt->maxch; channel++) {
1083 dinfo = &pvt->dimm_info[csrow][channel];
1084 handle_channel(pvt, csrow, channel, dinfo);
1085 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
1089 n = snprintf(p, space, "\n");
1094 /* Output the last bottom 'boundary' marker */
1095 n = snprintf(p, space, "---------------------------"
1096 "--------------------------------\n");
1100 /* now output the 'channel' labels */
1101 n = snprintf(p, space, " ");
1104 for (channel = 0; channel < pvt->maxch; channel++) {
1105 n = snprintf(p, space, "channel %d | ", channel);
1109 n = snprintf(p, space, "\n");
1113 /* output the last message and free buffer */
1114 debugf2("%s\n", mem_buffer);
1119 * i5000_get_mc_regs read in the necessary registers and
1122 * Fills in the private data members
1124 static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1126 struct i5000_pvt *pvt;
1134 pvt = mci->pvt_info;
1136 pci_read_config_dword(pvt->system_address, AMBASE,
1137 (u32 *) & pvt->ambase);
1138 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1139 ((u32 *) & pvt->ambase) + sizeof(u32));
1141 maxdimmperch = pvt->maxdimmperch;
1144 debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1145 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1147 /* Get the Branch Map regs */
1148 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1150 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1153 actual_tolm = pvt->tolm << 28;
1154 debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm);
1156 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1157 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1158 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1160 /* Get the MIR[0-2] regs */
1161 limit = (pvt->mir0 >> 4) & 0x0FFF;
1162 way0 = pvt->mir0 & 0x1;
1163 way1 = pvt->mir0 & 0x2;
1164 debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1165 limit = (pvt->mir1 >> 4) & 0x0FFF;
1166 way0 = pvt->mir1 & 0x1;
1167 way1 = pvt->mir1 & 0x2;
1168 debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1169 limit = (pvt->mir2 >> 4) & 0x0FFF;
1170 way0 = pvt->mir2 & 0x1;
1171 way1 = pvt->mir2 & 0x2;
1172 debugf2("MIR2: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1174 /* Get the MTR[0-3] regs */
1175 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1176 int where = MTR0 + (slot_row * sizeof(u32));
1178 pci_read_config_word(pvt->branch_0, where,
1179 &pvt->b0_mtr[slot_row]);
1181 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
1182 pvt->b0_mtr[slot_row]);
1184 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1185 pci_read_config_word(pvt->branch_1, where,
1186 &pvt->b1_mtr[slot_row]);
1187 debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
1188 where, pvt->b1_mtr[slot_row]);
1190 pvt->b1_mtr[slot_row] = 0;
1194 /* Read and dump branch 0's MTRs */
1195 debugf2("\nMemory Technology Registers:\n");
1196 debugf2(" Branch 0:\n");
1197 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1198 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1200 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
1201 &pvt->b0_ambpresent0);
1202 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1203 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
1204 &pvt->b0_ambpresent1);
1205 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1207 /* Only if we have 2 branchs (4 channels) */
1208 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1209 pvt->b1_ambpresent0 = 0;
1210 pvt->b1_ambpresent1 = 0;
1212 /* Read and dump branch 1's MTRs */
1213 debugf2(" Branch 1:\n");
1214 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1215 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1217 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
1218 &pvt->b1_ambpresent0);
1219 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
1220 pvt->b1_ambpresent0);
1221 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
1222 &pvt->b1_ambpresent1);
1223 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
1224 pvt->b1_ambpresent1);
1227 /* Go and determine the size of each DIMM and place in an
1229 calculate_dimm_size(pvt);
1233 * i5000_init_csrows Initialize the 'csrows' table within
1234 * the mci control structure with the
1235 * addressing of memory.
1239 * 1 no actual memory found on this MC
1241 static int i5000_init_csrows(struct mem_ctl_info *mci)
1243 struct i5000_pvt *pvt;
1244 struct csrow_info *p_csrow;
1245 struct dimm_info *dimm;
1246 int empty, channel_count;
1253 pvt = mci->pvt_info;
1255 channel_count = pvt->maxch;
1256 max_csrows = pvt->maxdimmperch * 2;
1258 empty = 1; /* Assume NO memory */
1261 * TODO: it would be better to not use csrow here, filling
1262 * directly the dimm_info structs, based on branch, channel, dim number
1264 for (csrow = 0; csrow < max_csrows; csrow++) {
1265 p_csrow = &mci->csrows[csrow];
1267 p_csrow->csrow_idx = csrow;
1269 /* use branch 0 for the basis */
1270 mtr = pvt->b0_mtr[csrow >> 1];
1271 mtr1 = pvt->b1_mtr[csrow >> 1];
1273 /* if no DIMMS on this row, continue */
1274 if (!MTR_DIMMS_PRESENT(mtr) && !MTR_DIMMS_PRESENT(mtr1))
1278 for (channel = 0; channel < pvt->maxch; channel++) {
1279 dimm = p_csrow->channels[channel].dimm;
1280 csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1283 /* Assume DDR2 for now */
1284 dimm->mtype = MEM_FB_DDR2;
1286 /* ask what device type on this row */
1287 if (MTR_DRAM_WIDTH(mtr))
1288 dimm->dtype = DEV_X8;
1290 dimm->dtype = DEV_X4;
1292 dimm->edac_mode = EDAC_S8ECD8ED;
1293 dimm->nr_pages = (csrow_megs << 8) / pvt->maxch;
1303 * i5000_enable_error_reporting
1304 * Turn on the memory reporting features of the hardware
1306 static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1308 struct i5000_pvt *pvt;
1311 pvt = mci->pvt_info;
1313 /* Read the FBD Error Mask Register */
1314 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1317 /* Enable with a '0' */
1318 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1320 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1325 * i5000_get_dimm_and_channel_counts(pdev, &nr_csrows, &num_channels)
1327 * ask the device how many channels are present and how many CSROWS
1330 static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
1331 int *num_dimms_per_channel,
1336 /* Need to retrieve just how many channels and dimms per channel are
1337 * supported on this memory controller
1339 pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
1340 *num_dimms_per_channel = (int)value *2;
1342 pci_read_config_byte(pdev, MAXCH, &value);
1343 *num_channels = (int)value;
1347 * i5000_probe1 Probe for ONE instance of device to see if it is
1350 * 0 for FOUND a device
1351 * < 0 for error code
1353 static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1355 struct mem_ctl_info *mci;
1356 struct edac_mc_layer layers[3];
1357 struct i5000_pvt *pvt;
1359 int num_dimms_per_channel;
1361 debugf0("MC: %s: %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1364 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1366 /* We only are looking for func 0 of the set */
1367 if (PCI_FUNC(pdev->devfn) != 0)
1370 /* Ask the devices for the number of CSROWS and CHANNELS so
1371 * that we can calculate the memory resources, etc
1373 * The Chipset will report what it can handle which will be greater
1374 * or equal to what the motherboard manufacturer will implement.
1376 * As we don't have a motherboard identification routine to determine
1377 * actual number of slots/dimms per channel, we thus utilize the
1378 * resource as specified by the chipset. Thus, we might have
1379 * have more DIMMs per channel than actually on the mobo, but this
1380 * allows the driver to support up to the chipset max, without
1381 * some fancy mobo determination.
1383 i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
1386 debugf0("MC: %s(): Number of Branches=2 Channels= %d DIMMS= %d\n",
1387 __func__, num_channels, num_dimms_per_channel);
1389 /* allocate a new MC control structure */
1390 layers[0].type = EDAC_MC_LAYER_BRANCH;
1392 layers[0].is_virt_csrow = true;
1393 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1394 layers[1].size = num_channels;
1395 layers[1].is_virt_csrow = false;
1396 layers[2].type = EDAC_MC_LAYER_SLOT;
1397 layers[2].size = num_dimms_per_channel;
1398 layers[2].is_virt_csrow = true;
1399 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1403 kobject_get(&mci->edac_mci_kobj);
1404 debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci);
1406 mci->dev = &pdev->dev; /* record ptr to the generic device */
1408 pvt = mci->pvt_info;
1409 pvt->system_address = pdev; /* Record this device in our private */
1410 pvt->maxch = num_channels;
1411 pvt->maxdimmperch = num_dimms_per_channel;
1413 /* 'get' the pci devices we want to reserve for our use */
1414 if (i5000_get_devices(mci, dev_idx))
1417 /* Time to get serious */
1418 i5000_get_mc_regs(mci); /* retrieve the hardware registers */
1421 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1422 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1423 mci->edac_cap = EDAC_FLAG_NONE;
1424 mci->mod_name = "i5000_edac.c";
1425 mci->mod_ver = I5000_REVISION;
1426 mci->ctl_name = i5000_devs[dev_idx].ctl_name;
1427 mci->dev_name = pci_name(pdev);
1428 mci->ctl_page_to_phys = NULL;
1430 /* Set the function pointer to an actual operation function */
1431 mci->edac_check = i5000_check_error;
1433 /* initialize the MC control structure 'csrows' table
1434 * with the mapping and control information */
1435 if (i5000_init_csrows(mci)) {
1436 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1437 " because i5000_init_csrows() returned nonzero "
1439 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1441 debugf1("MC: Enable error reporting now\n");
1442 i5000_enable_error_reporting(mci);
1445 /* add this new MC control structure to EDAC's list of MCs */
1446 if (edac_mc_add_mc(mci)) {
1447 debugf0("MC: %s: %s(): failed edac_mc_add_mc()\n",
1448 __FILE__, __func__);
1449 /* FIXME: perhaps some code should go here that disables error
1450 * reporting if we just enabled it
1455 i5000_clear_error(mci);
1457 /* allocating generic PCI control info */
1458 i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1461 "%s(): Unable to create PCI control\n",
1464 "%s(): PCI error report via EDAC not setup\n",
1470 /* Error exit unwinding stack */
1473 i5000_put_devices(mci);
1476 kobject_put(&mci->edac_mci_kobj);
1482 * i5000_init_one constructor for one instance of device
1488 static int __devinit i5000_init_one(struct pci_dev *pdev,
1489 const struct pci_device_id *id)
1493 debugf0("MC: %s: %s()\n", __FILE__, __func__);
1495 /* wake up device */
1496 rc = pci_enable_device(pdev);
1500 /* now probe and enable the device */
1501 return i5000_probe1(pdev, id->driver_data);
1505 * i5000_remove_one destructor for one instance of device
1508 static void __devexit i5000_remove_one(struct pci_dev *pdev)
1510 struct mem_ctl_info *mci;
1512 debugf0("%s: %s()\n", __FILE__, __func__);
1515 edac_pci_release_generic_ctl(i5000_pci);
1517 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1520 /* retrieve references to resources, and free those resources */
1521 i5000_put_devices(mci);
1522 kobject_put(&mci->edac_mci_kobj);
1527 * pci_device_id table for which devices we are looking for
1529 * The "E500P" device is the first device supported.
1531 static DEFINE_PCI_DEVICE_TABLE(i5000_pci_tbl) = {
1532 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
1533 .driver_data = I5000P},
1535 {0,} /* 0 terminated list. */
1538 MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
1541 * i5000_driver pci_driver structure for this module
1544 static struct pci_driver i5000_driver = {
1545 .name = KBUILD_BASENAME,
1546 .probe = i5000_init_one,
1547 .remove = __devexit_p(i5000_remove_one),
1548 .id_table = i5000_pci_tbl,
1552 * i5000_init Module entry function
1553 * Try to initialize this module for its devices
1555 static int __init i5000_init(void)
1559 debugf2("MC: %s: %s()\n", __FILE__, __func__);
1561 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1564 pci_rc = pci_register_driver(&i5000_driver);
1566 return (pci_rc < 0) ? pci_rc : 0;
1570 * i5000_exit() Module exit function
1571 * Unregister the driver
1573 static void __exit i5000_exit(void)
1575 debugf2("MC: %s: %s()\n", __FILE__, __func__);
1576 pci_unregister_driver(&i5000_driver);
1579 module_init(i5000_init);
1580 module_exit(i5000_exit);
1582 MODULE_LICENSE("GPL");
1584 ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
1585 MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
1588 module_param(edac_op_state, int, 0444);
1589 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1590 module_param(misc_messages, int, 0444);
1591 MODULE_PARM_DESC(misc_messages, "Log miscellaneous non fatal messages");