2 * Intel 5100 Memory Controllers kernel module
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * This module is based on the following document:
9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
10 * http://download.intel.com/design/chipsets/datashts/318378.pdf
12 * The intel 5100 has two independent channels. EDAC core currently
13 * can not reflect this configuration so instead the chip-select
14 * rows for each respective channel are layed out one after another,
15 * the first half belonging to channel 0, the second half belonging
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <linux/pci_ids.h>
22 #include <linux/edac.h>
23 #include <linux/delay.h>
24 #include <linux/mmzone.h>
26 #include "edac_core.h"
28 /* register addresses */
30 /* device 16, func 1 */
31 #define I5100_MC 0x40 /* Memory Control Register */
32 #define I5100_MC_SCRBEN_MASK (1 << 7)
33 #define I5100_MC_SCRBDONE_MASK (1 << 4)
34 #define I5100_MS 0x44 /* Memory Status Register */
35 #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */
36 #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */
37 #define I5100_TOLM 0x6c /* Top of Low Memory */
38 #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
39 #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
40 #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
41 #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
42 #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */
43 #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)
44 #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)
45 #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)
46 #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)
47 #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)
48 #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)
49 #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)
50 #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)
51 #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)
52 #define I5100_FERR_NF_MEM_M1ERR_MASK 1
53 #define I5100_FERR_NF_MEM_ANY_MASK \
54 (I5100_FERR_NF_MEM_M16ERR_MASK | \
55 I5100_FERR_NF_MEM_M15ERR_MASK | \
56 I5100_FERR_NF_MEM_M14ERR_MASK | \
57 I5100_FERR_NF_MEM_M12ERR_MASK | \
58 I5100_FERR_NF_MEM_M11ERR_MASK | \
59 I5100_FERR_NF_MEM_M10ERR_MASK | \
60 I5100_FERR_NF_MEM_M6ERR_MASK | \
61 I5100_FERR_NF_MEM_M5ERR_MASK | \
62 I5100_FERR_NF_MEM_M4ERR_MASK | \
63 I5100_FERR_NF_MEM_M1ERR_MASK)
64 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
65 #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */
67 /* device 21 and 22, func 0 */
68 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
69 #define I5100_DMIR 0x15c /* DIMM Interleave Range */
70 #define I5100_VALIDLOG 0x18c /* Valid Log Markers */
71 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
72 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
73 #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */
74 #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */
75 #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */
76 #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */
77 #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */
79 /* bit field accessors */
81 static inline u32 i5100_mc_scrben(u32 mc)
86 static inline u32 i5100_mc_errdeten(u32 mc)
91 static inline u32 i5100_mc_scrbdone(u32 mc)
96 static inline u16 i5100_spddata_rdo(u16 a)
101 static inline u16 i5100_spddata_sbe(u16 a)
106 static inline u16 i5100_spddata_busy(u16 a)
111 static inline u16 i5100_spddata_data(u16 a)
113 return a & ((1 << 8) - 1);
116 static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
119 return ((dti & ((1 << 4) - 1)) << 28) |
120 ((ckovrd & 1) << 27) |
121 ((sa & ((1 << 3) - 1)) << 24) |
122 ((ba & ((1 << 8) - 1)) << 16) |
123 ((data & ((1 << 8) - 1)) << 8) |
127 static inline u16 i5100_tolm_tolm(u16 a)
129 return a >> 12 & ((1 << 4) - 1);
132 static inline u16 i5100_mir_limit(u16 a)
134 return a >> 4 & ((1 << 12) - 1);
137 static inline u16 i5100_mir_way1(u16 a)
142 static inline u16 i5100_mir_way0(u16 a)
147 static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
152 static inline u32 i5100_ferr_nf_mem_any(u32 a)
154 return a & I5100_FERR_NF_MEM_ANY_MASK;
157 static inline u32 i5100_nerr_nf_mem_any(u32 a)
159 return i5100_ferr_nf_mem_any(a);
162 static inline u32 i5100_dmir_limit(u32 a)
164 return a >> 16 & ((1 << 11) - 1);
167 static inline u32 i5100_dmir_rank(u32 a, u32 i)
169 return a >> (4 * i) & ((1 << 2) - 1);
172 static inline u16 i5100_mtr_present(u16 a)
177 static inline u16 i5100_mtr_ethrottle(u16 a)
182 static inline u16 i5100_mtr_width(u16 a)
187 static inline u16 i5100_mtr_numbank(u16 a)
192 static inline u16 i5100_mtr_numrow(u16 a)
194 return a >> 2 & ((1 << 2) - 1);
197 static inline u16 i5100_mtr_numcol(u16 a)
199 return a & ((1 << 2) - 1);
203 static inline u32 i5100_validlog_redmemvalid(u32 a)
208 static inline u32 i5100_validlog_recmemvalid(u32 a)
213 static inline u32 i5100_validlog_nrecmemvalid(u32 a)
218 static inline u32 i5100_nrecmema_merr(u32 a)
220 return a >> 15 & ((1 << 5) - 1);
223 static inline u32 i5100_nrecmema_bank(u32 a)
225 return a >> 12 & ((1 << 3) - 1);
228 static inline u32 i5100_nrecmema_rank(u32 a)
230 return a >> 8 & ((1 << 3) - 1);
233 static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
235 return a & ((1 << 8) - 1);
238 static inline u32 i5100_nrecmemb_cas(u32 a)
240 return a >> 16 & ((1 << 13) - 1);
243 static inline u32 i5100_nrecmemb_ras(u32 a)
245 return a & ((1 << 16) - 1);
248 static inline u32 i5100_redmemb_ecc_locator(u32 a)
250 return a & ((1 << 18) - 1);
253 static inline u32 i5100_recmema_merr(u32 a)
255 return i5100_nrecmema_merr(a);
258 static inline u32 i5100_recmema_bank(u32 a)
260 return i5100_nrecmema_bank(a);
263 static inline u32 i5100_recmema_rank(u32 a)
265 return i5100_nrecmema_rank(a);
268 static inline u32 i5100_recmema_dm_buf_id(u32 a)
270 return i5100_nrecmema_dm_buf_id(a);
273 static inline u32 i5100_recmemb_cas(u32 a)
275 return i5100_nrecmemb_cas(a);
278 static inline u32 i5100_recmemb_ras(u32 a)
280 return i5100_nrecmemb_ras(a);
283 /* some generic limits */
284 #define I5100_MAX_RANKS_PER_CHAN 6
285 #define I5100_CHANNELS 2
286 #define I5100_MAX_RANKS_PER_DIMM 4
287 #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */
288 #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4
289 #define I5100_MAX_RANK_INTERLEAVE 4
290 #define I5100_MAX_DMIRS 5
291 #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)
294 /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */
295 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
298 * mainboard chip select map -- maps i5100 chip selects to
299 * DIMM slot chip selects. In the case of only 4 ranks per
300 * channel, the mapping is fairly obvious but not unique.
301 * we map -1 -> NC and assume both channels use the same
305 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
307 /* memory interleave range */
311 } mir[I5100_CHANNELS];
313 /* adjusted memory interleave range register */
314 unsigned amir[I5100_CHANNELS];
316 /* dimm interleave range */
318 unsigned rank[I5100_MAX_RANK_INTERLEAVE];
320 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
322 /* memory technology registers... */
324 unsigned present; /* 0 or 1 */
325 unsigned ethrottle; /* 0 or 1 */
326 unsigned width; /* 4 or 8 bits */
327 unsigned numbank; /* 2 or 3 lines */
328 unsigned numrow; /* 13 .. 16 lines */
329 unsigned numcol; /* 11 .. 12 lines */
330 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
332 u64 tolm; /* top of low memory in bytes */
333 unsigned ranksperchan; /* number of ranks per channel */
335 struct pci_dev *mc; /* device 16 func 1 */
336 struct pci_dev *ch0mm; /* device 21 func 0 */
337 struct pci_dev *ch1mm; /* device 22 func 0 */
339 struct delayed_work i5100_scrubbing;
343 /* map a rank/chan to a slot number on the mainboard */
344 static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
347 const struct i5100_priv *priv = mci->pvt_info;
350 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
352 const int numrank = priv->dimm_numrank[chan][i];
354 for (j = 0; j < numrank; j++)
355 if (priv->dimm_csmap[i][j] == rank)
362 static const char *i5100_err_msg(unsigned err)
364 static const char *merrs[] = {
366 "uncorrectable data ECC on replay", /* 1 */
369 "aliased uncorrectable demand data ECC", /* 4 */
370 "aliased uncorrectable spare-copy data ECC", /* 5 */
371 "aliased uncorrectable patrol data ECC", /* 6 */
375 "non-aliased uncorrectable demand data ECC", /* 10 */
376 "non-aliased uncorrectable spare-copy data ECC", /* 11 */
377 "non-aliased uncorrectable patrol data ECC", /* 12 */
379 "correctable demand data ECC", /* 14 */
380 "correctable spare-copy data ECC", /* 15 */
381 "correctable patrol data ECC", /* 16 */
383 "SPD protocol error", /* 18 */
385 "spare copy initiated", /* 20 */
386 "spare copy completed", /* 21 */
390 for (i = 0; i < ARRAY_SIZE(merrs); i++)
397 /* convert csrow index into a rank (per channel -- 0..5) */
398 static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)
400 const struct i5100_priv *priv = mci->pvt_info;
402 return csrow % priv->ranksperchan;
405 /* convert csrow index into a channel (0..1) */
406 static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)
408 const struct i5100_priv *priv = mci->pvt_info;
410 return csrow / priv->ranksperchan;
413 static unsigned i5100_rank_to_csrow(const struct mem_ctl_info *mci,
416 const struct i5100_priv *priv = mci->pvt_info;
418 return chan * priv->ranksperchan + rank;
421 static void i5100_handle_ce(struct mem_ctl_info *mci,
425 unsigned long syndrome,
430 const int csrow = i5100_rank_to_csrow(mci, chan, rank);
433 "CE chan %d, bank %u, rank %u, syndrome 0x%lx, "
434 "cas %u, ras %u, csrow %u, label \"%s\": %s\n",
435 chan, bank, rank, syndrome, cas, ras,
436 csrow, mci->csrows[csrow].channels[0].label, msg);
439 mci->csrows[csrow].ce_count++;
440 mci->csrows[csrow].channels[0].ce_count++;
443 static void i5100_handle_ue(struct mem_ctl_info *mci,
447 unsigned long syndrome,
452 const int csrow = i5100_rank_to_csrow(mci, chan, rank);
455 "UE chan %d, bank %u, rank %u, syndrome 0x%lx, "
456 "cas %u, ras %u, csrow %u, label \"%s\": %s\n",
457 chan, bank, rank, syndrome, cas, ras,
458 csrow, mci->csrows[csrow].channels[0].label, msg);
461 mci->csrows[csrow].ue_count++;
464 static void i5100_read_log(struct mem_ctl_info *mci, int chan,
467 struct i5100_priv *priv = mci->pvt_info;
468 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
471 unsigned syndrome = 0;
472 unsigned ecc_loc = 0;
479 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
481 if (i5100_validlog_redmemvalid(dw)) {
482 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
484 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
485 ecc_loc = i5100_redmemb_ecc_locator(dw2);
488 if (i5100_validlog_recmemvalid(dw)) {
491 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
492 merr = i5100_recmema_merr(dw2);
493 bank = i5100_recmema_bank(dw2);
494 rank = i5100_recmema_rank(dw2);
496 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
497 cas = i5100_recmemb_cas(dw2);
498 ras = i5100_recmemb_ras(dw2);
500 /* FIXME: not really sure if this is what merr is...
503 msg = i5100_err_msg(ferr);
505 msg = i5100_err_msg(nerr);
507 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
510 if (i5100_validlog_nrecmemvalid(dw)) {
513 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
514 merr = i5100_nrecmema_merr(dw2);
515 bank = i5100_nrecmema_bank(dw2);
516 rank = i5100_nrecmema_rank(dw2);
518 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
519 cas = i5100_nrecmemb_cas(dw2);
520 ras = i5100_nrecmemb_ras(dw2);
522 /* FIXME: not really sure if this is what merr is...
525 msg = i5100_err_msg(ferr);
527 msg = i5100_err_msg(nerr);
529 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
532 pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
535 static void i5100_check_error(struct mem_ctl_info *mci)
537 struct i5100_priv *priv = mci->pvt_info;
541 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
542 if (i5100_ferr_nf_mem_any(dw)) {
545 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
547 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM,
549 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
551 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
552 i5100_ferr_nf_mem_any(dw),
553 i5100_nerr_nf_mem_any(dw2));
557 /* The i5100 chipset will scrub the entire memory once, then
558 * set a done bit. Continuous scrubbing is achieved by enqueing
559 * delayed work to a workqueue, checking every few minutes if
560 * the scrubbing has completed and if so reinitiating it.
563 static void i5100_refresh_scrubbing(struct work_struct *work)
565 struct delayed_work *i5100_scrubbing = container_of(work,
568 struct i5100_priv *priv = container_of(i5100_scrubbing,
573 pci_read_config_dword(priv->mc, I5100_MC, &dw);
575 if (priv->scrub_enable) {
577 pci_read_config_dword(priv->mc, I5100_MC, &dw);
579 if (i5100_mc_scrbdone(dw)) {
580 dw |= I5100_MC_SCRBEN_MASK;
581 pci_write_config_dword(priv->mc, I5100_MC, dw);
582 pci_read_config_dword(priv->mc, I5100_MC, &dw);
585 schedule_delayed_work(&(priv->i5100_scrubbing),
586 I5100_SCRUB_REFRESH_RATE);
590 * The bandwidth is based on experimentation, feel free to refine it.
592 static int i5100_set_scrub_rate(struct mem_ctl_info *mci,
595 struct i5100_priv *priv = mci->pvt_info;
598 pci_read_config_dword(priv->mc, I5100_MC, &dw);
600 priv->scrub_enable = 1;
601 dw |= I5100_MC_SCRBEN_MASK;
602 schedule_delayed_work(&(priv->i5100_scrubbing),
603 I5100_SCRUB_REFRESH_RATE);
605 priv->scrub_enable = 0;
606 dw &= ~I5100_MC_SCRBEN_MASK;
607 cancel_delayed_work(&(priv->i5100_scrubbing));
609 pci_write_config_dword(priv->mc, I5100_MC, dw);
611 pci_read_config_dword(priv->mc, I5100_MC, &dw);
613 *bandwidth = 5900000 * i5100_mc_scrben(dw);
618 static int i5100_get_scrub_rate(struct mem_ctl_info *mci,
621 struct i5100_priv *priv = mci->pvt_info;
624 pci_read_config_dword(priv->mc, I5100_MC, &dw);
626 *bandwidth = 5900000 * i5100_mc_scrben(dw);
631 static struct pci_dev *pci_get_device_func(unsigned vendor,
635 struct pci_dev *ret = NULL;
638 ret = pci_get_device(vendor, device, ret);
643 if (PCI_FUNC(ret->devfn) == func)
650 static unsigned long __devinit i5100_npages(struct mem_ctl_info *mci,
653 struct i5100_priv *priv = mci->pvt_info;
654 const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);
655 const unsigned chan = i5100_csrow_to_chan(mci, csrow);
659 if (!priv->mtr[chan][chan_rank].present)
663 I5100_DIMM_ADDR_LINES +
664 priv->mtr[chan][chan_rank].numcol +
665 priv->mtr[chan][chan_rank].numrow +
666 priv->mtr[chan][chan_rank].numbank;
668 return (unsigned long)
669 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
672 static void __devinit i5100_init_mtr(struct mem_ctl_info *mci)
674 struct i5100_priv *priv = mci->pvt_info;
675 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
678 for (i = 0; i < I5100_CHANNELS; i++) {
680 struct pci_dev *pdev = mms[i];
682 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
683 const unsigned addr =
684 (j < 4) ? I5100_MTR_0 + j * 2 :
685 I5100_MTR_4 + (j - 4) * 2;
688 pci_read_config_word(pdev, addr, &w);
690 priv->mtr[i][j].present = i5100_mtr_present(w);
691 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
692 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
693 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
694 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
695 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
701 * FIXME: make this into a real i2c adapter (so that dimm-decode
704 static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
705 u8 ch, u8 slot, u8 addr, u8 *byte)
707 struct i5100_priv *priv = mci->pvt_info;
711 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
712 if (i5100_spddata_busy(w))
715 pci_write_config_dword(priv->mc, I5100_SPDCMD,
716 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
719 /* wait up to 100ms */
720 et = jiffies + HZ / 10;
723 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
724 if (!i5100_spddata_busy(w))
729 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
732 *byte = i5100_spddata_data(w);
738 * fill dimm chip select map
741 * o not the only way to may chip selects to dimm slots
742 * o investigate if there is some way to obtain this map from the bios
744 static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci)
746 struct i5100_priv *priv = mci->pvt_info;
749 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
752 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
753 priv->dimm_csmap[i][j] = -1; /* default NC */
756 /* only 2 chip selects per slot... */
757 if (priv->ranksperchan == 4) {
758 priv->dimm_csmap[0][0] = 0;
759 priv->dimm_csmap[0][1] = 3;
760 priv->dimm_csmap[1][0] = 1;
761 priv->dimm_csmap[1][1] = 2;
762 priv->dimm_csmap[2][0] = 2;
763 priv->dimm_csmap[3][0] = 3;
765 priv->dimm_csmap[0][0] = 0;
766 priv->dimm_csmap[0][1] = 1;
767 priv->dimm_csmap[1][0] = 2;
768 priv->dimm_csmap[1][1] = 3;
769 priv->dimm_csmap[2][0] = 4;
770 priv->dimm_csmap[2][1] = 5;
774 static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev,
775 struct mem_ctl_info *mci)
777 struct i5100_priv *priv = mci->pvt_info;
780 for (i = 0; i < I5100_CHANNELS; i++) {
783 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
786 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
787 priv->dimm_numrank[i][j] = 0;
789 priv->dimm_numrank[i][j] = (rank & 3) + 1;
793 i5100_init_dimm_csmap(mci);
796 static void __devinit i5100_init_interleaving(struct pci_dev *pdev,
797 struct mem_ctl_info *mci)
801 struct i5100_priv *priv = mci->pvt_info;
802 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
805 pci_read_config_word(pdev, I5100_TOLM, &w);
806 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
808 pci_read_config_word(pdev, I5100_MIR0, &w);
809 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
810 priv->mir[0].way[1] = i5100_mir_way1(w);
811 priv->mir[0].way[0] = i5100_mir_way0(w);
813 pci_read_config_word(pdev, I5100_MIR1, &w);
814 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
815 priv->mir[1].way[1] = i5100_mir_way1(w);
816 priv->mir[1].way[0] = i5100_mir_way0(w);
818 pci_read_config_word(pdev, I5100_AMIR_0, &w);
820 pci_read_config_word(pdev, I5100_AMIR_1, &w);
823 for (i = 0; i < I5100_CHANNELS; i++) {
826 for (j = 0; j < 5; j++) {
829 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
831 priv->dmir[i][j].limit =
832 (u64) i5100_dmir_limit(dw) << 28;
833 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
834 priv->dmir[i][j].rank[k] =
835 i5100_dmir_rank(dw, k);
842 static void __devinit i5100_init_csrows(struct mem_ctl_info *mci)
845 unsigned long total_pages = 0UL;
846 struct i5100_priv *priv = mci->pvt_info;
848 for (i = 0; i < mci->nr_csrows; i++) {
849 const unsigned long npages = i5100_npages(mci, i);
850 const unsigned chan = i5100_csrow_to_chan(mci, i);
851 const unsigned rank = i5100_csrow_to_rank(mci, i);
857 * FIXME: these two are totally bogus -- I don't see how to
858 * map them correctly to this structure...
860 mci->csrows[i].first_page = total_pages;
861 mci->csrows[i].last_page = total_pages + npages - 1;
862 mci->csrows[i].page_mask = 0UL;
864 mci->csrows[i].nr_pages = npages;
865 mci->csrows[i].grain = 32;
866 mci->csrows[i].csrow_idx = i;
867 mci->csrows[i].dtype =
868 (priv->mtr[chan][rank].width == 4) ? DEV_X4 : DEV_X8;
869 mci->csrows[i].ue_count = 0;
870 mci->csrows[i].ce_count = 0;
871 mci->csrows[i].mtype = MEM_RDDR2;
872 mci->csrows[i].edac_mode = EDAC_SECDED;
873 mci->csrows[i].mci = mci;
874 mci->csrows[i].nr_channels = 1;
875 mci->csrows[i].channels[0].chan_idx = 0;
876 mci->csrows[i].channels[0].ce_count = 0;
877 mci->csrows[i].channels[0].csrow = mci->csrows + i;
878 snprintf(mci->csrows[i].channels[0].label,
879 sizeof(mci->csrows[i].channels[0].label),
880 "DIMM%u", i5100_rank_to_slot(mci, chan, rank));
882 total_pages += npages;
886 static int __devinit i5100_init_one(struct pci_dev *pdev,
887 const struct pci_device_id *id)
890 struct mem_ctl_info *mci;
891 struct i5100_priv *priv;
892 struct pci_dev *ch0mm, *ch1mm;
897 if (PCI_FUNC(pdev->devfn) != 1)
900 rc = pci_enable_device(pdev);
907 pci_read_config_dword(pdev, I5100_MC, &dw);
908 if (!i5100_mc_errdeten(dw)) {
909 printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
914 /* figure out how many ranks, from strapped state of 48GB_Mode input */
915 pci_read_config_dword(pdev, I5100_MS, &dw);
916 ranksperch = !!(dw & (1 << 8)) * 2 + 4;
918 /* enable error reporting... */
919 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
920 dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
921 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
923 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
924 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
925 PCI_DEVICE_ID_INTEL_5100_21, 0);
931 rc = pci_enable_device(ch0mm);
937 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */
938 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
939 PCI_DEVICE_ID_INTEL_5100_22, 0);
942 goto bail_disable_ch0;
945 rc = pci_enable_device(ch1mm);
951 mci = edac_mc_alloc(sizeof(*priv), ranksperch * 2, 1, 0);
954 goto bail_disable_ch1;
957 mci->dev = &pdev->dev;
959 priv = mci->pvt_info;
960 priv->ranksperchan = ranksperch;
965 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
967 /* If scrubbing was already enabled by the bios, start maintaining it */
968 pci_read_config_dword(pdev, I5100_MC, &dw);
969 if (i5100_mc_scrben(dw)) {
970 priv->scrub_enable = 1;
971 schedule_delayed_work(&(priv->i5100_scrubbing),
972 I5100_SCRUB_REFRESH_RATE);
975 i5100_init_dimm_layout(pdev, mci);
976 i5100_init_interleaving(pdev, mci);
978 mci->mtype_cap = MEM_FLAG_FB_DDR2;
979 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
980 mci->edac_cap = EDAC_FLAG_SECDED;
981 mci->mod_name = "i5100_edac.c";
982 mci->mod_ver = "not versioned";
983 mci->ctl_name = "i5100";
984 mci->dev_name = pci_name(pdev);
985 mci->ctl_page_to_phys = NULL;
987 mci->edac_check = i5100_check_error;
988 mci->set_sdram_scrub_rate = i5100_set_scrub_rate;
989 mci->get_sdram_scrub_rate = i5100_get_scrub_rate;
991 i5100_init_csrows(mci);
993 /* this strange construction seems to be in every driver, dunno why */
994 switch (edac_op_state) {
995 case EDAC_OPSTATE_POLL:
996 case EDAC_OPSTATE_NMI:
999 edac_op_state = EDAC_OPSTATE_POLL;
1003 if (edac_mc_add_mc(mci)) {
1011 priv->scrub_enable = 0;
1012 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1016 pci_disable_device(ch1mm);
1022 pci_disable_device(ch0mm);
1028 pci_disable_device(pdev);
1034 static void __devexit i5100_remove_one(struct pci_dev *pdev)
1036 struct mem_ctl_info *mci;
1037 struct i5100_priv *priv;
1039 mci = edac_mc_del_mc(&pdev->dev);
1044 priv = mci->pvt_info;
1046 priv->scrub_enable = 0;
1047 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1049 pci_disable_device(pdev);
1050 pci_disable_device(priv->ch0mm);
1051 pci_disable_device(priv->ch1mm);
1052 pci_dev_put(priv->ch0mm);
1053 pci_dev_put(priv->ch1mm);
1058 static const struct pci_device_id i5100_pci_tbl[] __devinitdata = {
1059 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
1063 MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);
1065 static struct pci_driver i5100_driver = {
1066 .name = KBUILD_BASENAME,
1067 .probe = i5100_init_one,
1068 .remove = __devexit_p(i5100_remove_one),
1069 .id_table = i5100_pci_tbl,
1072 static int __init i5100_init(void)
1076 pci_rc = pci_register_driver(&i5100_driver);
1078 return (pci_rc < 0) ? pci_rc : 0;
1081 static void __exit i5100_exit(void)
1083 pci_unregister_driver(&i5100_driver);
1086 module_init(i5100_init);
1087 module_exit(i5100_exit);
1089 MODULE_LICENSE("GPL");
1091 ("Arthur Jones <ajones@riverbed.com>");
1092 MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");