2 * Intel 5400 class Memory Controllers kernel module (Seaburg)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Copyright (c) 2008 by:
8 * Ben Woodard <woodard@redhat.com>
9 * Mauro Carvalho Chehab <mchehab@redhat.com>
11 * Red Hat Inc. http://www.redhat.com
13 * Forked and adapted from the i5000_edac driver which was
14 * written by Douglas Thompson Linux Networx <norsk5@xmission.com>
16 * This module is based on the following document:
18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
19 * http://developer.intel.com/design/chipsets/datashts/313070.htm
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/pci_ids.h>
27 #include <linux/slab.h>
28 #include <linux/edac.h>
29 #include <linux/mmzone.h>
31 #include "edac_core.h"
34 * Alter this version for the I5400 module when modifications are made
36 #define I5400_REVISION " Ver: 1.0.0"
38 #define EDAC_MOD_STR "i5400_edac"
40 #define i5400_printk(level, fmt, arg...) \
41 edac_printk(level, "i5400", fmt, ##arg)
43 #define i5400_mc_printk(mci, level, fmt, arg...) \
44 edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg)
46 /* Limits for i5400 */
47 #define NUM_MTRS_PER_BRANCH 4
48 #define CHANNELS_PER_BRANCH 2
49 #define MAX_DIMMS_PER_CHANNEL NUM_MTRS_PER_BRANCH
50 #define MAX_CHANNELS 4
51 /* max possible csrows per channel */
52 #define MAX_CSROWS (MAX_DIMMS_PER_CHANNEL)
55 * Function 0: System Address
56 * Function 1: Memory Branch Map, Control, Errors Register
57 * Function 2: FSB Error Registers
59 * All 3 functions of Device 16 (0,1,2) share the SAME DID and
60 * uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2),
61 * PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD1
62 * for device 21 (0,1).
65 /* OFFSETS for Function 0 */
66 #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
67 #define MAXCH 0x56 /* Max Channel Number */
68 #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
70 /* OFFSETS for Function 1 */
73 #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */
79 /* Fatal error registers */
80 #define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */
81 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
83 #define NERR_FAT_FBD 0x9c
84 #define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */
86 /* Non-fatal error register */
87 #define NERR_NF_FBD 0xa4
89 /* Enable error mask */
90 #define EMASK_FBD 0xa8
95 #define MCERR_FBD 0xb8
97 /* No OFFSETS for Device 16 Function 2 */
101 * Function 0: Memory Map Branch 0
104 * Function 0: Memory Map Branch 1
107 /* OFFSETS for Function 0 */
108 #define AMBPRESENT_0 0x64
109 #define AMBPRESENT_1 0x66
115 /* OFFSETS for Function 1 */
116 #define NRECFGLOG 0x74
117 #define RECFGLOG 0x78
118 #define NRECMEMA 0xbe
119 #define NRECMEMB 0xc0
120 #define NRECFB_DIMMA 0xc4
121 #define NRECFB_DIMMB 0xc8
122 #define NRECFB_DIMMC 0xcc
123 #define NRECFB_DIMMD 0xd0
124 #define NRECFB_DIMME 0xd4
125 #define NRECFB_DIMMF 0xd8
129 #define RECFB_DIMMA 0xf8
130 #define RECFB_DIMMB 0xec
131 #define RECFB_DIMMC 0xf0
132 #define RECFB_DIMMD 0xf4
133 #define RECFB_DIMME 0xf8
134 #define RECFB_DIMMF 0xfC
137 * Error indicator bits and masks
138 * Error masks are according with Table 5-17 of i5400 datasheet
142 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
143 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
144 EMASK_M3 = 1<<2, /* Reserved */
145 EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */
146 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
147 EMASK_M6 = 1<<5, /* Unsupported on i5400 */
148 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
149 EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */
150 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */
151 EMASK_M10 = 1<<9, /* Unsupported on i5400 */
152 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
153 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */
154 EMASK_M13 = 1<<12, /* Memory Write error on first attempt */
155 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */
156 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */
157 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */
158 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */
159 EMASK_M18 = 1<<17, /* Unsupported on i5400 */
160 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */
161 EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */
162 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */
163 EMASK_M22 = 1<<21, /* SPD protocol Error */
164 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */
165 EMASK_M24 = 1<<23, /* Refresh error */
166 EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */
167 EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */
168 EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */
169 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */
170 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */
174 * Names to translate bit error into something useful
176 static const char *error_name[] = {
177 [0] = "Memory Write error on non-redundant retry",
178 [1] = "Memory or FB-DIMM configuration CRC read error",
180 [3] = "Uncorrectable Data ECC on Replay",
181 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
182 /* M6 Unsupported on i5400 */
183 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
184 [7] = "Aliased Uncorrectable Patrol Data ECC",
185 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
186 /* M10 Unsupported on i5400 */
187 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
188 [11] = "Non-Aliased Uncorrectable Patrol Data ECC",
189 [12] = "Memory Write error on first attempt",
190 [13] = "FB-DIMM Configuration Write error on first attempt",
191 [14] = "Memory or FB-DIMM configuration CRC read error",
192 [15] = "Channel Failed-Over Occurred",
193 [16] = "Correctable Non-Mirrored Demand Data ECC",
194 /* M18 Unsupported on i5400 */
195 [18] = "Correctable Resilver- or Spare-Copy Data ECC",
196 [19] = "Correctable Patrol Data ECC",
197 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",
198 [21] = "SPD protocol Error",
199 [22] = "Non-Redundant Fast Reset Timeout",
200 [23] = "Refresh error",
201 [24] = "Memory Write error on redundant retry",
202 [25] = "Redundant Fast Reset Timeout",
203 [26] = "Correctable Counter Threshold Exceeded",
204 [27] = "DIMM-Spare Copy Completed",
205 [28] = "DIMM-Isolation Completed",
209 #define ERROR_FAT_MASK (EMASK_M1 | \
213 /* Correctable errors */
214 #define ERROR_NF_CORRECTABLE (EMASK_M27 | \
220 #define ERROR_NF_DIMM_SPARE (EMASK_M29 | \
222 #define ERROR_NF_SPD_PROTOCOL (EMASK_M22)
223 #define ERROR_NF_NORTH_CRC (EMASK_M21)
225 /* Recoverable errors */
226 #define ERROR_NF_RECOVERABLE (EMASK_M26 | \
239 /* uncorrectable errors */
240 #define ERROR_NF_UNCORRECTABLE (EMASK_M4)
242 /* mask to all non-fatal errors */
243 #define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \
244 ERROR_NF_UNCORRECTABLE | \
245 ERROR_NF_RECOVERABLE | \
246 ERROR_NF_DIMM_SPARE | \
247 ERROR_NF_SPD_PROTOCOL | \
251 * Define error masks for the several registers
254 /* Enable all fatal and non fatal errors */
255 #define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK)
257 /* mask for fatal error registers */
258 #define FERR_FAT_MASK ERROR_FAT_MASK
260 /* masks for non-fatal error register */
261 static inline int to_nf_mask(unsigned int mask)
263 return (mask & EMASK_M29) | (mask >> 3);
266 static inline int from_nf_ferr(unsigned int mask)
268 return (mask & EMASK_M29) | /* Bit 28 */
269 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */
272 #define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)
273 #define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)
274 #define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)
275 #define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)
276 #define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)
277 #define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)
278 #define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)
280 /* Defines to extract the vaious fields from the
281 * MTRx - Memory Technology Registers
283 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10))
284 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9))
285 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4)
286 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
287 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
288 #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1)
289 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
290 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
291 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
292 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
293 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
295 /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */
296 static inline int extract_fbdchan_indx(u32 x)
298 return (x>>28) & 0x3;
301 #ifdef CONFIG_EDAC_DEBUG
303 static const char *numrow_toString[] = {
311 static const char *numcol_toString[] = {
312 "1,024 - 10 columns",
313 "2,048 - 11 columns",
314 "4,096 - 12 columns",
319 /* Device name and register DID (Device ID) */
320 struct i5400_dev_info {
321 const char *ctl_name; /* name for this device */
322 u16 fsb_mapping_errors; /* DID for the branchmap,control */
325 /* Table of devices attributes supported by this driver */
326 static const struct i5400_dev_info i5400_devs[] = {
329 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_5400_ERR,
333 struct i5400_dimm_info {
334 int megabytes; /* size, 0 means not present */
337 /* driver private data structure */
339 struct pci_dev *system_address; /* 16.0 */
340 struct pci_dev *branchmap_werrors; /* 16.1 */
341 struct pci_dev *fsb_error_regs; /* 16.2 */
342 struct pci_dev *branch_0; /* 21.0 */
343 struct pci_dev *branch_1; /* 22.0 */
345 u16 tolm; /* top of low memory */
346 u64 ambase; /* AMB BAR */
350 u16 b0_mtr[NUM_MTRS_PER_BRANCH]; /* Memory Technlogy Reg */
351 u16 b0_ambpresent0; /* Branch 0, Channel 0 */
352 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
354 u16 b1_mtr[NUM_MTRS_PER_BRANCH]; /* Memory Technlogy Reg */
355 u16 b1_ambpresent0; /* Branch 1, Channel 8 */
356 u16 b1_ambpresent1; /* Branch 1, Channel 1 */
358 /* DIMM information matrix, allocating architecture maximums */
359 struct i5400_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
361 /* Actual values for this controller */
362 int maxch; /* Max channels */
363 int maxdimmperch; /* Max DIMMs per channel */
366 /* I5400 MCH error information retrieved from Hardware */
367 struct i5400_error_info {
368 /* These registers are always read from the MC */
369 u32 ferr_fat_fbd; /* First Errors Fatal */
370 u32 nerr_fat_fbd; /* Next Errors Fatal */
371 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
372 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
374 /* These registers are input ONLY if there was a Recoverable Error */
375 u32 redmemb; /* Recoverable Mem Data Error log B */
376 u16 recmema; /* Recoverable Mem Error log A */
377 u32 recmemb; /* Recoverable Mem Error log B */
379 /* These registers are input ONLY if there was a Non-Rec Error */
380 u16 nrecmema; /* Non-Recoverable Mem log A */
381 u16 nrecmemb; /* Non-Recoverable Mem log B */
385 /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and
386 5400 better to use an inline function than a macro in this case */
387 static inline int nrec_bank(struct i5400_error_info *info)
389 return ((info->nrecmema) >> 12) & 0x7;
391 static inline int nrec_rank(struct i5400_error_info *info)
393 return ((info->nrecmema) >> 8) & 0xf;
395 static inline int nrec_buf_id(struct i5400_error_info *info)
397 return ((info->nrecmema)) & 0xff;
399 static inline int nrec_rdwr(struct i5400_error_info *info)
401 return (info->nrecmemb) >> 31;
403 /* This applies to both NREC and REC string so it can be used with nrec_rdwr
405 static inline const char *rdwr_str(int rdwr)
407 return rdwr ? "Write" : "Read";
409 static inline int nrec_cas(struct i5400_error_info *info)
411 return ((info->nrecmemb) >> 16) & 0x1fff;
413 static inline int nrec_ras(struct i5400_error_info *info)
415 return (info->nrecmemb) & 0xffff;
417 static inline int rec_bank(struct i5400_error_info *info)
419 return ((info->recmema) >> 12) & 0x7;
421 static inline int rec_rank(struct i5400_error_info *info)
423 return ((info->recmema) >> 8) & 0xf;
425 static inline int rec_rdwr(struct i5400_error_info *info)
427 return (info->recmemb) >> 31;
429 static inline int rec_cas(struct i5400_error_info *info)
431 return ((info->recmemb) >> 16) & 0x1fff;
433 static inline int rec_ras(struct i5400_error_info *info)
435 return (info->recmemb) & 0xffff;
438 static struct edac_pci_ctl_info *i5400_pci;
441 * i5400_get_error_info Retrieve the hardware error information from
442 * the hardware and cache it in the 'info'
445 static void i5400_get_error_info(struct mem_ctl_info *mci,
446 struct i5400_error_info *info)
448 struct i5400_pvt *pvt;
453 /* read in the 1st FATAL error register */
454 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
456 /* Mask only the bits that the doc says are valid
458 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
460 /* If there is an error, then read in the
461 NEXT FATAL error register and the Memory Error Log Register A
463 if (value & FERR_FAT_MASK) {
464 info->ferr_fat_fbd = value;
466 /* harvest the various error data we need */
467 pci_read_config_dword(pvt->branchmap_werrors,
468 NERR_FAT_FBD, &info->nerr_fat_fbd);
469 pci_read_config_word(pvt->branchmap_werrors,
470 NRECMEMA, &info->nrecmema);
471 pci_read_config_word(pvt->branchmap_werrors,
472 NRECMEMB, &info->nrecmemb);
474 /* Clear the error bits, by writing them back */
475 pci_write_config_dword(pvt->branchmap_werrors,
476 FERR_FAT_FBD, value);
478 info->ferr_fat_fbd = 0;
479 info->nerr_fat_fbd = 0;
484 /* read in the 1st NON-FATAL error register */
485 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
487 /* If there is an error, then read in the 1st NON-FATAL error
488 * register as well */
489 if (value & FERR_NF_MASK) {
490 info->ferr_nf_fbd = value;
492 /* harvest the various error data we need */
493 pci_read_config_dword(pvt->branchmap_werrors,
494 NERR_NF_FBD, &info->nerr_nf_fbd);
495 pci_read_config_word(pvt->branchmap_werrors,
496 RECMEMA, &info->recmema);
497 pci_read_config_dword(pvt->branchmap_werrors,
498 RECMEMB, &info->recmemb);
499 pci_read_config_dword(pvt->branchmap_werrors,
500 REDMEMB, &info->redmemb);
502 /* Clear the error bits, by writing them back */
503 pci_write_config_dword(pvt->branchmap_werrors,
506 info->ferr_nf_fbd = 0;
507 info->nerr_nf_fbd = 0;
515 * i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
516 * struct i5400_error_info *info,
517 * int handle_errors);
519 * handle the Intel FATAL and unrecoverable errors, if any
521 static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
522 struct i5400_error_info *info,
523 unsigned long allErrors)
525 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
537 return; /* if no error, return now */
539 if (allErrors & ERROR_FAT_MASK)
541 else if (allErrors & FERR_NF_UNCORRECTABLE)
542 type = "NON-FATAL uncorrected";
544 type = "NON-FATAL recoverable";
546 /* ONLY ONE of the possible error bits will be set, as per the docs */
548 branch = extract_fbdchan_indx(info->ferr_fat_fbd);
551 /* Use the NON-Recoverable macros to extract data */
552 bank = nrec_bank(info);
553 rank = nrec_rank(info);
554 buf_id = nrec_buf_id(info);
555 rdwr = nrec_rdwr(info);
556 ras = nrec_ras(info);
557 cas = nrec_cas(info);
559 debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
560 "DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n",
561 rank, channel, channel + 1, branch >> 1, bank,
562 buf_id, rdwr_str(rdwr), ras, cas);
564 /* Only 1 bit will be on */
565 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
567 /* Form out message */
568 snprintf(msg, sizeof(msg),
569 "%s (Branch=%d DRAM-Bank=%d Buffer ID = %d RDWR=%s "
570 "RAS=%d CAS=%d %s Err=0x%lx (%s))",
571 type, branch >> 1, bank, buf_id, rdwr_str(rdwr), ras, cas,
572 type, allErrors, error_name[errnum]);
574 /* Call the helper to output message */
575 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
579 * i5400_process_fatal_error_info(struct mem_ctl_info *mci,
580 * struct i5400_error_info *info,
581 * int handle_errors);
583 * handle the Intel NON-FATAL errors, if any
585 static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
586 struct i5400_error_info *info)
588 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
589 unsigned long allErrors;
598 /* mask off the Error bits that are possible */
599 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK);
601 return; /* if no error, return now */
603 /* ONLY ONE of the possible error bits will be set, as per the docs */
605 if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) {
606 i5400_proccess_non_recoverable_info(mci, info, allErrors);
610 /* Correctable errors */
611 if (allErrors & ERROR_NF_CORRECTABLE) {
612 debugf0("\tCorrected bits= 0x%lx\n", allErrors);
614 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
617 if (REC_ECC_LOCATOR_ODD(info->redmemb))
620 /* Convert channel to be based from zero, instead of
621 * from branch base of 0 */
624 bank = rec_bank(info);
625 rank = rec_rank(info);
626 rdwr = rec_rdwr(info);
630 /* Only 1 bit will be on */
631 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
633 debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
634 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
635 rank, channel, branch >> 1, bank,
636 rdwr_str(rdwr), ras, cas);
638 /* Form out message */
639 snprintf(msg, sizeof(msg),
640 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s "
641 "RAS=%d CAS=%d, CE Err=0x%lx (%s))",
642 branch >> 1, bank, rdwr_str(rdwr), ras, cas,
643 allErrors, error_name[errnum]);
645 /* Call the helper to output message */
646 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
651 /* Miscellaneous errors */
652 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
654 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
656 i5400_mc_printk(mci, KERN_EMERG,
657 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))",
658 branch >> 1, allErrors, error_name[errnum]);
662 * i5400_process_error_info Process the error info that is
663 * in the 'info' structure, previously retrieved from hardware
665 static void i5400_process_error_info(struct mem_ctl_info *mci,
666 struct i5400_error_info *info)
669 /* First handle any fatal errors that occurred */
670 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
671 i5400_proccess_non_recoverable_info(mci, info, allErrors);
673 /* now handle any non-fatal errors that occurred */
674 i5400_process_nonfatal_error_info(mci, info);
678 * i5400_clear_error Retrieve any error from the hardware
679 * but do NOT process that error.
680 * Used for 'clearing' out of previous errors
681 * Called by the Core module.
683 static void i5400_clear_error(struct mem_ctl_info *mci)
685 struct i5400_error_info info;
687 i5400_get_error_info(mci, &info);
691 * i5400_check_error Retrieve and process errors reported by the
692 * hardware. Called by the Core module.
694 static void i5400_check_error(struct mem_ctl_info *mci)
696 struct i5400_error_info info;
697 debugf4("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__);
698 i5400_get_error_info(mci, &info);
699 i5400_process_error_info(mci, &info);
703 * i5400_put_devices 'put' all the devices that we have
706 static void i5400_put_devices(struct mem_ctl_info *mci)
708 struct i5400_pvt *pvt;
712 /* Decrement usage count for devices */
713 pci_dev_put(pvt->branch_1);
714 pci_dev_put(pvt->branch_0);
715 pci_dev_put(pvt->fsb_error_regs);
716 pci_dev_put(pvt->branchmap_werrors);
720 * i5400_get_devices Find and perform 'get' operation on the MCH's
721 * device/functions we want to reference for this driver
723 * Need to 'get' device 16 func 1 and func 2
725 static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
727 struct i5400_pvt *pvt;
728 struct pci_dev *pdev;
731 pvt->branchmap_werrors = NULL;
732 pvt->fsb_error_regs = NULL;
733 pvt->branch_0 = NULL;
734 pvt->branch_1 = NULL;
736 /* Attempt to 'get' the MCH register we want */
739 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
740 PCI_DEVICE_ID_INTEL_5400_ERR, pdev);
742 /* End of list, leave */
743 i5400_printk(KERN_ERR,
744 "'system address,Process Bus' "
746 "vendor 0x%x device 0x%x ERR func 1 "
749 PCI_DEVICE_ID_INTEL_5400_ERR);
753 /* Store device 16 func 1 */
754 if (PCI_FUNC(pdev->devfn) == 1)
757 pvt->branchmap_werrors = pdev;
761 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
762 PCI_DEVICE_ID_INTEL_5400_ERR, pdev);
764 /* End of list, leave */
765 i5400_printk(KERN_ERR,
766 "'system address,Process Bus' "
768 "vendor 0x%x device 0x%x ERR func 2 "
771 PCI_DEVICE_ID_INTEL_5400_ERR);
773 pci_dev_put(pvt->branchmap_werrors);
777 /* Store device 16 func 2 */
778 if (PCI_FUNC(pdev->devfn) == 2)
781 pvt->fsb_error_regs = pdev;
783 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
784 pci_name(pvt->system_address),
785 pvt->system_address->vendor, pvt->system_address->device);
786 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
787 pci_name(pvt->branchmap_werrors),
788 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
789 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
790 pci_name(pvt->fsb_error_regs),
791 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
793 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL,
794 PCI_DEVICE_ID_INTEL_5400_FBD0, NULL);
795 if (!pvt->branch_0) {
796 i5400_printk(KERN_ERR,
797 "MC: 'BRANCH 0' device not found:"
798 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
799 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0);
801 pci_dev_put(pvt->fsb_error_regs);
802 pci_dev_put(pvt->branchmap_werrors);
806 /* If this device claims to have more than 2 channels then
807 * fetch Branch 1's information
809 if (pvt->maxch < CHANNELS_PER_BRANCH)
812 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL,
813 PCI_DEVICE_ID_INTEL_5400_FBD1, NULL);
814 if (!pvt->branch_1) {
815 i5400_printk(KERN_ERR,
816 "MC: 'BRANCH 1' device not found:"
817 "vendor 0x%x device 0x%x Func 0 "
820 PCI_DEVICE_ID_INTEL_5400_FBD1);
822 pci_dev_put(pvt->branch_0);
823 pci_dev_put(pvt->fsb_error_regs);
824 pci_dev_put(pvt->branchmap_werrors);
832 * determine_amb_present
834 * the information is contained in NUM_MTRS_PER_BRANCH different
835 * registers determining which of the NUM_MTRS_PER_BRANCH requires
836 * knowing which channel is in question
838 * 2 branches, each with 2 channels
839 * b0_ambpresent0 for channel '0'
840 * b0_ambpresent1 for channel '1'
841 * b1_ambpresent0 for channel '2'
842 * b1_ambpresent1 for channel '3'
844 static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)
848 if (channel < CHANNELS_PER_BRANCH) {
850 amb_present = pvt->b0_ambpresent1;
852 amb_present = pvt->b0_ambpresent0;
855 amb_present = pvt->b1_ambpresent1;
857 amb_present = pvt->b1_ambpresent0;
864 * determine_mtr(pvt, csrow, channel)
866 * return the proper MTR register as determine by the csrow and desired channel
868 static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel)
873 /* There is one MTR for each slot pair of FB-DIMMs,
874 Each slot pair may be at branch 0 or branch 1.
878 if (n >= NUM_MTRS_PER_BRANCH) {
879 debugf0("ERROR: trying to access an invalid csrow: %d\n",
884 if (channel < CHANNELS_PER_BRANCH)
885 mtr = pvt->b0_mtr[n];
887 mtr = pvt->b1_mtr[n];
894 static void decode_mtr(int slot_row, u16 mtr)
898 ans = MTR_DIMMS_PRESENT(mtr);
900 debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr,
901 ans ? "Present" : "NOT Present");
905 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
907 debugf2("\t\tELECTRICAL THROTTLING is %s\n",
908 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
910 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
911 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
912 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
913 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
916 static void handle_channel(struct i5400_pvt *pvt, int csrow, int channel,
917 struct i5400_dimm_info *dinfo)
923 mtr = determine_mtr(pvt, csrow, channel);
924 if (MTR_DIMMS_PRESENT(mtr)) {
925 amb_present_reg = determine_amb_present_reg(pvt, channel);
927 /* Determine if there is a DIMM present in this DIMM slot */
928 if (amb_present_reg & (1 << csrow)) {
929 /* Start with the number of bits for a Bank
931 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
932 /* Add thenumber of ROW bits */
933 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
934 /* add the number of COLUMN bits */
935 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
936 /* add the number of RANK bits */
937 addrBits += MTR_DIMM_RANK(mtr);
939 addrBits += 6; /* add 64 bits per DIMM */
940 addrBits -= 20; /* divide by 2^^20 */
941 addrBits -= 3; /* 8 bits per bytes */
943 dinfo->megabytes = 1 << addrBits;
949 * calculate_dimm_size
951 * also will output a DIMM matrix map, if debug is enabled, for viewing
952 * how the DIMMs are populated
954 static void calculate_dimm_size(struct i5400_pvt *pvt)
956 struct i5400_dimm_info *dinfo;
957 int csrow, max_csrows;
958 char *p, *mem_buffer;
962 /* ================= Generate some debug output ================= */
964 mem_buffer = p = kmalloc(space, GFP_KERNEL);
966 i5400_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
971 /* Scan all the actual CSROWS
972 * and calculate the information for each DIMM
973 * Start with the highest csrow first, to display it first
974 * and work toward the 0th csrow
976 max_csrows = pvt->maxdimmperch;
977 for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
979 /* on an odd csrow, first output a 'boundary' marker,
980 * then reset the message buffer */
982 n = snprintf(p, space, "---------------------------"
983 "--------------------------------");
986 debugf2("%s\n", mem_buffer);
990 n = snprintf(p, space, "csrow %2d ", csrow);
994 for (channel = 0; channel < pvt->maxch; channel++) {
995 dinfo = &pvt->dimm_info[csrow][channel];
996 handle_channel(pvt, csrow, channel, dinfo);
997 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
1001 debugf2("%s\n", mem_buffer);
1006 /* Output the last bottom 'boundary' marker */
1007 n = snprintf(p, space, "---------------------------"
1008 "--------------------------------");
1011 debugf2("%s\n", mem_buffer);
1015 /* now output the 'channel' labels */
1016 n = snprintf(p, space, " ");
1019 for (channel = 0; channel < pvt->maxch; channel++) {
1020 n = snprintf(p, space, "channel %d | ", channel);
1025 /* output the last message and free buffer */
1026 debugf2("%s\n", mem_buffer);
1031 * i5400_get_mc_regs read in the necessary registers and
1034 * Fills in the private data members
1036 static void i5400_get_mc_regs(struct mem_ctl_info *mci)
1038 struct i5400_pvt *pvt;
1046 pvt = mci->pvt_info;
1048 pci_read_config_dword(pvt->system_address, AMBASE,
1049 (u32 *) &pvt->ambase);
1050 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1051 ((u32 *) &pvt->ambase) + sizeof(u32));
1053 maxdimmperch = pvt->maxdimmperch;
1056 debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1057 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1059 /* Get the Branch Map regs */
1060 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1062 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1065 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
1066 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
1067 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
1069 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1070 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1072 /* Get the MIR[0-1] regs */
1073 limit = (pvt->mir0 >> 4) & 0x0fff;
1074 way0 = pvt->mir0 & 0x1;
1075 way1 = pvt->mir0 & 0x2;
1076 debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1077 limit = (pvt->mir1 >> 4) & 0xfff;
1078 way0 = pvt->mir1 & 0x1;
1079 way1 = pvt->mir1 & 0x2;
1080 debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1082 /* Get the set of MTR[0-3] regs by each branch */
1083 for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++) {
1084 int where = MTR0 + (slot_row * sizeof(u16));
1086 /* Branch 0 set of MTR registers */
1087 pci_read_config_word(pvt->branch_0, where,
1088 &pvt->b0_mtr[slot_row]);
1090 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
1091 pvt->b0_mtr[slot_row]);
1093 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1094 pvt->b1_mtr[slot_row] = 0;
1098 /* Branch 1 set of MTR registers */
1099 pci_read_config_word(pvt->branch_1, where,
1100 &pvt->b1_mtr[slot_row]);
1101 debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row, where,
1102 pvt->b1_mtr[slot_row]);
1105 /* Read and dump branch 0's MTRs */
1106 debugf2("\nMemory Technology Registers:\n");
1107 debugf2(" Branch 0:\n");
1108 for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++)
1109 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1111 pci_read_config_word(pvt->branch_0, AMBPRESENT_0,
1112 &pvt->b0_ambpresent0);
1113 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1114 pci_read_config_word(pvt->branch_0, AMBPRESENT_1,
1115 &pvt->b0_ambpresent1);
1116 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1118 /* Only if we have 2 branchs (4 channels) */
1119 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1120 pvt->b1_ambpresent0 = 0;
1121 pvt->b1_ambpresent1 = 0;
1123 /* Read and dump branch 1's MTRs */
1124 debugf2(" Branch 1:\n");
1125 for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++)
1126 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1128 pci_read_config_word(pvt->branch_1, AMBPRESENT_0,
1129 &pvt->b1_ambpresent0);
1130 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
1131 pvt->b1_ambpresent0);
1132 pci_read_config_word(pvt->branch_1, AMBPRESENT_1,
1133 &pvt->b1_ambpresent1);
1134 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
1135 pvt->b1_ambpresent1);
1138 /* Go and determine the size of each DIMM and place in an
1140 calculate_dimm_size(pvt);
1144 * i5400_init_csrows Initialize the 'csrows' table within
1145 * the mci control structure with the
1146 * addressing of memory.
1150 * 1 no actual memory found on this MC
1152 static int i5400_init_csrows(struct mem_ctl_info *mci)
1154 struct i5400_pvt *pvt;
1155 struct csrow_info *p_csrow;
1156 int empty, channel_count;
1162 struct dimm_info *dimm;
1164 pvt = mci->pvt_info;
1166 channel_count = pvt->maxch;
1167 max_csrows = pvt->maxdimmperch;
1169 empty = 1; /* Assume NO memory */
1171 for (csrow = 0; csrow < max_csrows; csrow++) {
1172 p_csrow = &mci->csrows[csrow];
1174 /* use branch 0 for the basis */
1175 mtr = determine_mtr(pvt, csrow, 0);
1177 /* if no DIMMS on this row, continue */
1178 if (!MTR_DIMMS_PRESENT(mtr))
1181 for (channel = 0; channel < pvt->maxch; channel++) {
1182 size_mb = pvt->dimm_info[csrow][channel].megabytes;
1184 dimm = p_csrow->channels[channel].dimm;
1185 dimm->nr_pages = size_mb << 8;
1187 dimm->dtype = MTR_DRAM_WIDTH(mtr) ? DEV_X8 : DEV_X4;
1188 dimm->mtype = MEM_RDDR2;
1189 dimm->edac_mode = EDAC_SECDED;
1199 * i5400_enable_error_reporting
1200 * Turn on the memory reporting features of the hardware
1202 static void i5400_enable_error_reporting(struct mem_ctl_info *mci)
1204 struct i5400_pvt *pvt;
1207 pvt = mci->pvt_info;
1209 /* Read the FBD Error Mask Register */
1210 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1213 /* Enable with a '0' */
1214 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1216 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1221 * i5400_probe1 Probe for ONE instance of device to see if it is
1224 * 0 for FOUND a device
1225 * < 0 for error code
1227 static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
1229 struct mem_ctl_info *mci;
1230 struct i5400_pvt *pvt;
1232 int num_dimms_per_channel;
1235 if (dev_idx >= ARRAY_SIZE(i5400_devs))
1238 debugf0("MC: %s: %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1241 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1243 /* We only are looking for func 0 of the set */
1244 if (PCI_FUNC(pdev->devfn) != 0)
1247 /* As we don't have a motherboard identification routine to determine
1248 * actual number of slots/dimms per channel, we thus utilize the
1249 * resource as specified by the chipset. Thus, we might have
1250 * have more DIMMs per channel than actually on the mobo, but this
1251 * allows the driver to support up to the chipset max, without
1252 * some fancy mobo determination.
1254 num_dimms_per_channel = MAX_DIMMS_PER_CHANNEL;
1255 num_channels = MAX_CHANNELS;
1256 num_csrows = num_dimms_per_channel;
1258 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
1259 __func__, num_channels, num_dimms_per_channel, num_csrows);
1261 /* allocate a new MC control structure */
1262 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1267 debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci);
1269 mci->dev = &pdev->dev; /* record ptr to the generic device */
1271 pvt = mci->pvt_info;
1272 pvt->system_address = pdev; /* Record this device in our private */
1273 pvt->maxch = num_channels;
1274 pvt->maxdimmperch = num_dimms_per_channel;
1276 /* 'get' the pci devices we want to reserve for our use */
1277 if (i5400_get_devices(mci, dev_idx))
1280 /* Time to get serious */
1281 i5400_get_mc_regs(mci); /* retrieve the hardware registers */
1284 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1285 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1286 mci->edac_cap = EDAC_FLAG_NONE;
1287 mci->mod_name = "i5400_edac.c";
1288 mci->mod_ver = I5400_REVISION;
1289 mci->ctl_name = i5400_devs[dev_idx].ctl_name;
1290 mci->dev_name = pci_name(pdev);
1291 mci->ctl_page_to_phys = NULL;
1293 /* Set the function pointer to an actual operation function */
1294 mci->edac_check = i5400_check_error;
1296 /* initialize the MC control structure 'csrows' table
1297 * with the mapping and control information */
1298 if (i5400_init_csrows(mci)) {
1299 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1300 " because i5400_init_csrows() returned nonzero "
1302 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1304 debugf1("MC: Enable error reporting now\n");
1305 i5400_enable_error_reporting(mci);
1308 /* add this new MC control structure to EDAC's list of MCs */
1309 if (edac_mc_add_mc(mci)) {
1310 debugf0("MC: %s: %s(): failed edac_mc_add_mc()\n",
1311 __FILE__, __func__);
1312 /* FIXME: perhaps some code should go here that disables error
1313 * reporting if we just enabled it
1318 i5400_clear_error(mci);
1320 /* allocating generic PCI control info */
1321 i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1324 "%s(): Unable to create PCI control\n",
1327 "%s(): PCI error report via EDAC not setup\n",
1333 /* Error exit unwinding stack */
1336 i5400_put_devices(mci);
1344 * i5400_init_one constructor for one instance of device
1350 static int __devinit i5400_init_one(struct pci_dev *pdev,
1351 const struct pci_device_id *id)
1355 debugf0("MC: %s: %s()\n", __FILE__, __func__);
1357 /* wake up device */
1358 rc = pci_enable_device(pdev);
1362 /* now probe and enable the device */
1363 return i5400_probe1(pdev, id->driver_data);
1367 * i5400_remove_one destructor for one instance of device
1370 static void __devexit i5400_remove_one(struct pci_dev *pdev)
1372 struct mem_ctl_info *mci;
1374 debugf0("%s: %s()\n", __FILE__, __func__);
1377 edac_pci_release_generic_ctl(i5400_pci);
1379 mci = edac_mc_del_mc(&pdev->dev);
1383 /* retrieve references to resources, and free those resources */
1384 i5400_put_devices(mci);
1390 * pci_device_id table for which devices we are looking for
1392 * The "E500P" device is the first device supported.
1394 static DEFINE_PCI_DEVICE_TABLE(i5400_pci_tbl) = {
1395 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)},
1396 {0,} /* 0 terminated list. */
1399 MODULE_DEVICE_TABLE(pci, i5400_pci_tbl);
1402 * i5400_driver pci_driver structure for this module
1405 static struct pci_driver i5400_driver = {
1406 .name = "i5400_edac",
1407 .probe = i5400_init_one,
1408 .remove = __devexit_p(i5400_remove_one),
1409 .id_table = i5400_pci_tbl,
1413 * i5400_init Module entry function
1414 * Try to initialize this module for its devices
1416 static int __init i5400_init(void)
1420 debugf2("MC: %s: %s()\n", __FILE__, __func__);
1422 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1425 pci_rc = pci_register_driver(&i5400_driver);
1427 return (pci_rc < 0) ? pci_rc : 0;
1431 * i5400_exit() Module exit function
1432 * Unregister the driver
1434 static void __exit i5400_exit(void)
1436 debugf2("MC: %s: %s()\n", __FILE__, __func__);
1437 pci_unregister_driver(&i5400_driver);
1440 module_init(i5400_init);
1441 module_exit(i5400_exit);
1443 MODULE_LICENSE("GPL");
1444 MODULE_AUTHOR("Ben Woodard <woodard@redhat.com>");
1445 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1446 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1447 MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - "
1450 module_param(edac_op_state, int, 0444);
1451 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");