2 * Intel D82875P Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Thayne Harbaugh
9 * Wang Zhenyu at intel.com
11 * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
13 * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
16 #include <linux/config.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/pci_ids.h>
21 #include <linux/slab.h>
24 #define I82875P_REVISION " Ver: 2.0.0 " __DATE__
26 #define i82875p_printk(level, fmt, arg...) \
27 edac_printk(level, "i82875p", fmt, ##arg)
29 #define i82875p_mc_printk(mci, level, fmt, arg...) \
30 edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
32 #ifndef PCI_DEVICE_ID_INTEL_82875_0
33 #define PCI_DEVICE_ID_INTEL_82875_0 0x2578
34 #endif /* PCI_DEVICE_ID_INTEL_82875_0 */
36 #ifndef PCI_DEVICE_ID_INTEL_82875_6
37 #define PCI_DEVICE_ID_INTEL_82875_6 0x257e
38 #endif /* PCI_DEVICE_ID_INTEL_82875_6 */
40 /* four csrows in dual channel, eight in single channel */
41 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
43 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
44 #define I82875P_EAP 0x58 /* Error Address Pointer (32b)
50 #define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
52 * 7:0 DRAM ECC Syndrome
55 #define I82875P_DES 0x5d /* DRAM Error Status (8b)
61 #define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
64 * 9 non-DRAM lock error (ndlock)
65 * 8 Sftwr Generated SMI
68 * 5 MCH detects unimplemented cycle
69 * 4 AGP access outside GA
70 * 3 Invalid AGP access
71 * 2 Invalid GA translation table
72 * 1 Unsupported AGP command
76 #define I82875P_ERRCMD 0xca /* Error Command (16b)
79 * 9 SERR on non-DRAM lock
82 * 6 target abort on high exception
83 * 5 detect unimplemented cyc
84 * 4 AGP access outside of GA
85 * 3 SERR on invalid AGP access
86 * 2 invalid translation table
87 * 1 SERR on unsupported AGP command
91 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
92 #define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
95 * 9 fast back-to-back - ro 0
96 * 8 SERR enable - ro 0
97 * 7 addr/data stepping - ro 0
98 * 6 parity err enable - ro 0
99 * 5 VGA palette snoop - ro 0
100 * 4 mem wr & invalidate - ro 0
101 * 3 special cycle - ro 0
102 * 2 bus master - ro 0
103 * 1 mem access dev6 - 0(dis),1(en)
104 * 0 IO access dev3 - 0(dis),1(en)
107 #define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
109 * 31:12 mem base addr [31:12]
110 * 11:4 address mask - ro 0
111 * 3 prefetchable - ro 0(non),1(pre)
112 * 2:1 mem type - ro 0
116 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
118 #define I82875P_DRB_SHIFT 26 /* 64MiB grain */
119 #define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
122 * 6:0 64MiB row boundary addr
125 #define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
138 #define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
143 * 22:21 nr chan 00=1,01=2
145 * 19:18 Data Integ Mode 00=none,01=ecc
151 * 1:0 DRAM type 01=DDR
159 struct pci_dev *ovrfl_pdev;
160 void __iomem *ovrfl_window;
163 struct i82875p_dev_info {
164 const char *ctl_name;
167 struct i82875p_error_info {
175 static const struct i82875p_dev_info i82875p_devs[] = {
177 .ctl_name = "i82875p"
181 static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code has
182 * already registered driver
185 static int i82875p_registered = 1;
187 static void i82875p_get_error_info(struct mem_ctl_info *mci,
188 struct i82875p_error_info *info)
190 struct pci_dev *pdev;
192 pdev = to_pci_dev(mci->dev);
195 * This is a mess because there is no atomic way to read all the
196 * registers at once and the registers can transition from CE being
199 pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
200 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
201 pci_read_config_byte(pdev, I82875P_DES, &info->des);
202 pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
203 pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
205 pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
208 * If the error is the same then we can for both reads then
209 * the first set of reads is valid. If there is a change then
210 * there is a CE no info and the second set of reads is valid
211 * and should be UE info.
213 if (!(info->errsts2 & 0x0081))
216 if ((info->errsts ^ info->errsts2) & 0x0081) {
217 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
218 pci_read_config_byte(pdev, I82875P_DES, &info->des);
219 pci_read_config_byte(pdev, I82875P_DERRSYN,
224 static int i82875p_process_error_info(struct mem_ctl_info *mci,
225 struct i82875p_error_info *info, int handle_errors)
229 multi_chan = mci->csrows[0].nr_channels - 1;
231 if (!(info->errsts2 & 0x0081))
237 if ((info->errsts ^ info->errsts2) & 0x0081) {
238 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
239 info->errsts = info->errsts2;
242 info->eap >>= PAGE_SHIFT;
243 row = edac_mc_find_csrow_by_page(mci, info->eap);
245 if (info->errsts & 0x0080)
246 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
248 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
249 multi_chan ? (info->des & 0x1) : 0,
255 static void i82875p_check(struct mem_ctl_info *mci)
257 struct i82875p_error_info info;
259 debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
260 i82875p_get_error_info(mci, &info);
261 i82875p_process_error_info(mci, &info, 1);
264 #ifdef CONFIG_PROC_FS
265 extern int pci_proc_attach_device(struct pci_dev *);
268 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
272 struct mem_ctl_info *mci = NULL;
273 struct i82875p_pvt *pvt = NULL;
274 unsigned long last_cumul_size;
275 struct pci_dev *ovrfl_pdev;
276 void __iomem *ovrfl_window = NULL;
278 u32 drc_chan; /* Number of channels 0=1chan,1=2chan */
280 u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
281 struct i82875p_error_info discard;
283 debugf0("%s()\n", __func__);
284 ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
288 * Intel tells BIOS developers to hide device 6 which
289 * configures the overflow device access containing
290 * the DRBs - this is where we expose device 6.
291 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
293 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
295 pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
301 #ifdef CONFIG_PROC_FS
302 if (!ovrfl_pdev->procent && pci_proc_attach_device(ovrfl_pdev)) {
303 i82875p_printk(KERN_ERR,
304 "%s(): Failed to attach overflow device\n", __func__);
309 if (pci_enable_device(ovrfl_pdev)) {
310 i82875p_printk(KERN_ERR,
311 "%s(): Failed to enable overflow device\n", __func__);
315 if (pci_request_regions(ovrfl_pdev, pci_name(ovrfl_pdev))) {
321 /* cache is irrelevant for PCI bus reads/writes */
322 ovrfl_window = ioremap_nocache(pci_resource_start(ovrfl_pdev, 0),
323 pci_resource_len(ovrfl_pdev, 0));
326 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
331 /* need to find out the number of channels */
332 drc = readl(ovrfl_window + I82875P_DRC);
333 drc_chan = ((drc >> 21) & 0x1);
334 nr_chans = drc_chan + 1;
336 drc_ddim = (drc >> 18) & 0x1;
337 mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
345 debugf3("%s(): init mci\n", __func__);
346 mci->dev = &pdev->dev;
347 mci->mtype_cap = MEM_FLAG_DDR;
348 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
349 mci->edac_cap = EDAC_FLAG_UNKNOWN;
352 mci->mod_name = EDAC_MOD_STR;
353 mci->mod_ver = I82875P_REVISION;
354 mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
355 mci->edac_check = i82875p_check;
356 mci->ctl_page_to_phys = NULL;
357 debugf3("%s(): init pvt\n", __func__);
358 pvt = (struct i82875p_pvt *) mci->pvt_info;
359 pvt->ovrfl_pdev = ovrfl_pdev;
360 pvt->ovrfl_window = ovrfl_window;
363 * The dram row boundary (DRB) reg values are boundary address
364 * for each DRAM row with a granularity of 32 or 64MB (single/dual
365 * channel operation). DRB regs are cumulative; therefore DRB7 will
366 * contain the total memory contained in all eight rows.
368 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
371 struct csrow_info *csrow = &mci->csrows[index];
373 value = readb(ovrfl_window + I82875P_DRB + index);
374 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
375 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
378 if (cumul_size == last_cumul_size)
379 continue; /* not populated */
381 csrow->first_page = last_cumul_size;
382 csrow->last_page = cumul_size - 1;
383 csrow->nr_pages = cumul_size - last_cumul_size;
384 last_cumul_size = cumul_size;
385 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
386 csrow->mtype = MEM_DDR;
387 csrow->dtype = DEV_UNKNOWN;
388 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
391 i82875p_get_error_info(mci, &discard); /* clear counters */
393 if (edac_mc_add_mc(mci)) {
394 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
398 /* get this far and it's successful */
399 debugf3("%s(): success\n", __func__);
406 iounmap(ovrfl_window);
409 pci_release_regions(ovrfl_pdev);
414 pci_disable_device(ovrfl_pdev);
415 /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
419 /* returns count (>= 0), or negative on error */
420 static int __devinit i82875p_init_one(struct pci_dev *pdev,
421 const struct pci_device_id *ent)
425 debugf0("%s()\n", __func__);
426 i82875p_printk(KERN_INFO, "i82875p init one\n");
428 if (pci_enable_device(pdev) < 0)
431 rc = i82875p_probe1(pdev, ent->driver_data);
433 if (mci_pdev == NULL)
434 mci_pdev = pci_dev_get(pdev);
439 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
441 struct mem_ctl_info *mci;
442 struct i82875p_pvt *pvt = NULL;
444 debugf0("%s()\n", __func__);
446 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
449 pvt = (struct i82875p_pvt *) mci->pvt_info;
451 if (pvt->ovrfl_window)
452 iounmap(pvt->ovrfl_window);
454 if (pvt->ovrfl_pdev) {
456 pci_release_regions(pvt->ovrfl_pdev);
457 #endif /*CORRECT_BIOS */
458 pci_disable_device(pvt->ovrfl_pdev);
459 pci_dev_put(pvt->ovrfl_pdev);
465 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
467 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
472 } /* 0 terminated list. */
475 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
477 static struct pci_driver i82875p_driver = {
478 .name = EDAC_MOD_STR,
479 .probe = i82875p_init_one,
480 .remove = __devexit_p(i82875p_remove_one),
481 .id_table = i82875p_pci_tbl,
484 static int __init i82875p_init(void)
488 debugf3("%s()\n", __func__);
489 pci_rc = pci_register_driver(&i82875p_driver);
494 if (mci_pdev == NULL) {
495 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
496 PCI_DEVICE_ID_INTEL_82875_0, NULL);
499 debugf0("875p pci_get_device fail\n");
504 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
507 debugf0("875p init fail\n");
516 pci_unregister_driver(&i82875p_driver);
519 if (mci_pdev != NULL)
520 pci_dev_put(mci_pdev);
525 static void __exit i82875p_exit(void)
527 debugf3("%s()\n", __func__);
529 pci_unregister_driver(&i82875p_driver);
531 if (!i82875p_registered) {
532 i82875p_remove_one(mci_pdev);
533 pci_dev_put(mci_pdev);
537 module_init(i82875p_init);
538 module_exit(i82875p_exit);
540 MODULE_LICENSE("GPL");
541 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
542 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");