2 * Intel 82975X Memory Controller kernel module
3 * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
4 * (C) 2007 jetzbroadband (http://jetzbroadband.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
9 * Copied from i82875p_edac.c source:
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/edac.h>
17 #include "edac_core.h"
19 #define I82975X_REVISION " Ver: 1.0.0"
20 #define EDAC_MOD_STR "i82975x_edac"
22 #define i82975x_printk(level, fmt, arg...) \
23 edac_printk(level, "i82975x", fmt, ##arg)
25 #define i82975x_mc_printk(mci, level, fmt, arg...) \
26 edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)
28 #ifndef PCI_DEVICE_ID_INTEL_82975_0
29 #define PCI_DEVICE_ID_INTEL_82975_0 0x277c
30 #endif /* PCI_DEVICE_ID_INTEL_82975_0 */
32 #define I82975X_NR_DIMMS 8
33 #define I82975X_NR_CSROWS(nr_chans) (I82975X_NR_DIMMS / (nr_chans))
35 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
36 #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
38 * 31:7 128 byte cache-line address
43 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
45 * 7:0 DRAM ECC Syndrome
48 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
49 * 0h: Processor Memory Reads
51 * More - See Page 65 of Intel DocSheet.
54 #define I82975X_ERRSTS 0xc8 /* Error Status Register (16b)
57 * 11 Thermal Sensor Event
59 * 9 non-DRAM lock error (ndlock)
62 * 1 ECC UE (multibit DRAM error)
63 * 0 ECC CE (singlebit DRAM error)
66 /* Error Reporting is supported by 3 mechanisms:
67 1. DMI SERR generation ( ERRCMD )
68 2. SMI DMI generation ( SMICMD )
69 3. SCI DMI generation ( SCICMD )
70 NOTE: Only ONE of the three must be enabled
72 #define I82975X_ERRCMD 0xca /* Error Command (16b)
75 * 11 Thermal Sensor Event
77 * 9 non-DRAM lock error (ndlock)
80 * 1 ECC UE (multibit DRAM error)
81 * 0 ECC CE (singlebit DRAM error)
84 #define I82975X_SMICMD 0xcc /* Error Command (16b)
87 * 1 ECC UE (multibit DRAM error)
88 * 0 ECC CE (singlebit DRAM error)
91 #define I82975X_SCICMD 0xce /* Error Command (16b)
94 * 1 ECC UE (multibit DRAM error)
95 * 0 ECC CE (singlebit DRAM error)
98 #define I82975X_XEAP 0xfc /* Extended Dram Error Address Pointer (8b)
101 * 0 Bit32 of the Dram Error Address
104 #define I82975X_MCHBAR 0x44 /*
106 * 31:14 Base Addr of 16K memory-mapped
107 * configuration space
109 * 0 mem-mapped config space enable
112 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
113 /* Intel 82975x memory mapped register space */
115 #define I82975X_DRB_SHIFT 25 /* fixed 32MiB grain */
117 #define I82975X_DRB 0x100 /* DRAM Row Boundary (8b x 8)
119 * 7 set to 1 in highest DRB of
120 * channel if 4GB in ch.
121 * 6:2 upper boundary of rank in
125 #define I82975X_DRB_CH0R0 0x100
126 #define I82975X_DRB_CH0R1 0x101
127 #define I82975X_DRB_CH0R2 0x102
128 #define I82975X_DRB_CH0R3 0x103
129 #define I82975X_DRB_CH1R0 0x180
130 #define I82975X_DRB_CH1R1 0x181
131 #define I82975X_DRB_CH1R2 0x182
132 #define I82975X_DRB_CH1R3 0x183
135 #define I82975X_DRA 0x108 /* DRAM Row Attribute (4b x 8)
136 * defines the PAGE SIZE to be used
139 * 6:4 row attr of odd rank, i.e. 1
141 * 2:0 row attr of even rank, i.e. 0
150 #define I82975X_DRA_CH0R01 0x108
151 #define I82975X_DRA_CH0R23 0x109
152 #define I82975X_DRA_CH1R01 0x188
153 #define I82975X_DRA_CH1R23 0x189
156 #define I82975X_BNKARC 0x10e /* Type of device in each rank - Bank Arch (16b)
159 * 7:6 Rank 3 architecture
160 * 5:4 Rank 2 architecture
161 * 3:2 Rank 1 architecture
162 * 1:0 Rank 0 architecture
167 #define I82975X_C0BNKARC 0x10e
168 #define I82975X_C1BNKARC 0x18e
172 #define I82975X_DRC 0x120 /* DRAM Controller Mode0 (32b)
176 * 28:11 reserved, according to Intel
177 * 22:21 number of channels
179 * seems to be ECC mode
180 * bits in 82975 in Asus
182 * 19:18 Data Integ Mode
183 * 00=none 01=ECC in 82875
188 * 1:0 DRAM type 10=Second Revision
190 * 00, 01, 11 reserved
192 #define I82975X_DRC_CH0M0 0x120
193 #define I82975X_DRC_CH1M0 0x1A0
196 #define I82975X_DRC_M1 0x124 /* DRAM Controller Mode1 (32b)
197 * 31 0=Standard Address Map
198 * 1=Enhanced Address Map
202 #define I82975X_DRC_CH0M1 0x124
203 #define I82975X_DRC_CH1M1 0x1A4
210 void __iomem *mch_window;
213 struct i82975x_dev_info {
214 const char *ctl_name;
217 struct i82975x_error_info {
223 u8 chan; /* the channel is bit 0 of EAP */
224 u8 xeap; /* extended eap bit */
227 static const struct i82975x_dev_info i82975x_devs[] = {
229 .ctl_name = "i82975x"
233 static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
234 * already registered driver
237 static int i82975x_registered = 1;
239 static void i82975x_get_error_info(struct mem_ctl_info *mci,
240 struct i82975x_error_info *info)
242 struct pci_dev *pdev;
244 pdev = to_pci_dev(mci->pdev);
247 * This is a mess because there is no atomic way to read all the
248 * registers at once and the registers can transition from CE being
251 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts);
252 pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
253 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
254 pci_read_config_byte(pdev, I82975X_DES, &info->des);
255 pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn);
256 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2);
258 pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003);
261 * If the error is the same then we can for both reads then
262 * the first set of reads is valid. If there is a change then
263 * there is a CE no info and the second set of reads is valid
264 * and should be UE info.
266 if (!(info->errsts2 & 0x0003))
269 if ((info->errsts ^ info->errsts2) & 0x0003) {
270 pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
271 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
272 pci_read_config_byte(pdev, I82975X_DES, &info->des);
273 pci_read_config_byte(pdev, I82975X_DERRSYN,
278 static int i82975x_process_error_info(struct mem_ctl_info *mci,
279 struct i82975x_error_info *info, int handle_errors)
282 unsigned long offst, page;
284 if (!(info->errsts2 & 0x0003))
290 if ((info->errsts ^ info->errsts2) & 0x0003) {
291 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
292 -1, -1, -1, "UE overwrote CE", "");
293 info->errsts = info->errsts2;
296 page = (unsigned long) info->eap;
300 page >>= (PAGE_SHIFT - 1);
301 row = edac_mc_find_csrow_by_page(mci, page);
304 i82975x_mc_printk(mci, KERN_ERR, "error processing EAP:\n"
308 (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);
311 chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1;
313 & ((1 << PAGE_SHIFT) -
314 (1 << mci->csrows[row]->channels[chan]->dimm->grain));
316 if (info->errsts & 0x0002)
317 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
322 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
323 page, offst, info->derrsyn,
324 row, chan ? chan : 0, -1,
330 static void i82975x_check(struct mem_ctl_info *mci)
332 struct i82975x_error_info info;
334 edac_dbg(1, "MC%d\n", mci->mc_idx);
335 i82975x_get_error_info(mci, &info);
336 i82975x_process_error_info(mci, &info, 1);
339 /* Return 1 if dual channel mode is active. Else return 0. */
340 static int dual_channel_active(void __iomem *mch_window)
343 * We treat interleaved-symmetric configuration as dual-channel - EAP's
344 * bit-0 giving the channel of the error location.
346 * All other configurations are treated as single channel - the EAP's
347 * bit-0 will resolve ok in symmetric area of mixed
348 * (symmetric/asymmetric) configurations
354 for (dualch = 1, row = 0; dualch && (row < 4); row++) {
355 drb[row][0] = readb(mch_window + I82975X_DRB + row);
356 drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);
357 dualch = dualch && (drb[row][0] == drb[row][1]);
362 static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
365 * ECC is possible on i92975x ONLY with DEV_X8
370 static void i82975x_init_csrows(struct mem_ctl_info *mci,
371 struct pci_dev *pdev, void __iomem *mch_window)
373 static const char *labels[4] = {
374 "DIMM A1", "DIMM A2",
377 struct csrow_info *csrow;
378 unsigned long last_cumul_size;
380 u32 cumul_size, nr_pages;
382 struct dimm_info *dimm;
389 * The dram row boundary (DRB) reg values are boundary address
390 * for each DRAM row with a granularity of 32 or 64MB (single/dual
391 * channel operation). DRB regs are cumulative; therefore DRB7 will
392 * contain the total memory contained in all rows.
396 for (index = 0; index < mci->nr_csrows; index++) {
397 csrow = mci->csrows[index];
399 value = readb(mch_window + I82975X_DRB + index +
400 ((index >= 4) ? 0x80 : 0));
402 cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
404 * Adjust cumul_size w.r.t number of channels
407 if (csrow->nr_channels > 1)
409 edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
411 nr_pages = cumul_size - last_cumul_size;
416 * Initialise dram labels
418 * [0-7] for single-channel; i.e. csrow->nr_channels = 1
419 * [0-3] for dual-channel; i.e. csrow->nr_channels = 2
421 dtype = i82975x_dram_type(mch_window, index);
422 for (chan = 0; chan < csrow->nr_channels; chan++) {
423 dimm = mci->csrows[index]->channels[chan]->dimm;
425 dimm->nr_pages = nr_pages / csrow->nr_channels;
426 strncpy(csrow->channels[chan]->dimm->label,
427 labels[(index >> 1) + (chan * 2)],
429 dimm->grain = 1 << 7; /* 128Byte cache-line resolution */
430 dimm->dtype = i82975x_dram_type(mch_window, index);
431 dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
432 dimm->edac_mode = EDAC_SECDED; /* only supported */
435 csrow->first_page = last_cumul_size;
436 csrow->last_page = cumul_size - 1;
437 last_cumul_size = cumul_size;
441 /* #define i82975x_DEBUG_IOMEM */
443 #ifdef i82975x_DEBUG_IOMEM
444 static void i82975x_print_dram_timings(void __iomem *mch_window)
447 * The register meanings are from Intel specs;
448 * (shows 13-5-5-5 for 800-DDR2)
449 * Asus P5W Bios reports 15-5-4-4
450 * What's your religion?
452 static const int caslats[4] = { 5, 4, 3, 6 };
455 dtreg[0] = readl(mch_window + 0x114);
456 dtreg[1] = readl(mch_window + 0x194);
457 i82975x_printk(KERN_INFO, "DRAM Timings : Ch0 Ch1\n"
458 " RAS Active Min = %d %d\n"
459 " CAS latency = %d %d\n"
460 " RAS to CAS = %d %d\n"
461 " RAS precharge = %d %d\n",
462 (dtreg[0] >> 19 ) & 0x0f,
463 (dtreg[1] >> 19) & 0x0f,
464 caslats[(dtreg[0] >> 8) & 0x03],
465 caslats[(dtreg[1] >> 8) & 0x03],
466 ((dtreg[0] >> 4) & 0x07) + 2,
467 ((dtreg[1] >> 4) & 0x07) + 2,
468 (dtreg[0] & 0x07) + 2,
469 (dtreg[1] & 0x07) + 2
475 static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
478 struct mem_ctl_info *mci;
479 struct edac_mc_layer layers[2];
480 struct i82975x_pvt *pvt;
481 void __iomem *mch_window;
484 struct i82975x_error_info discard;
486 #ifdef i82975x_DEBUG_IOMEM
493 pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar);
495 edac_dbg(3, "failed, MCHBAR disabled!\n");
498 mchbar &= 0xffffc000; /* bits 31:14 used for 16K window */
499 mch_window = ioremap_nocache(mchbar, 0x1000);
501 #ifdef i82975x_DEBUG_IOMEM
502 i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n",
505 c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0);
506 c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1);
507 c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2);
508 c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3);
509 c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0);
510 c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1);
511 c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2);
512 c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3);
513 i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]);
514 i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]);
515 i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]);
516 i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]);
517 i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]);
518 i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]);
519 i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]);
520 i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]);
523 drc[0] = readl(mch_window + I82975X_DRC_CH0M0);
524 drc[1] = readl(mch_window + I82975X_DRC_CH1M0);
525 #ifdef i82975x_DEBUG_IOMEM
526 i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0],
527 ((drc[0] >> 21) & 3) == 1 ?
528 "ECC enabled" : "ECC disabled");
529 i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1],
530 ((drc[1] >> 21) & 3) == 1 ?
531 "ECC enabled" : "ECC disabled");
533 i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n",
534 readw(mch_window + I82975X_C0BNKARC));
535 i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n",
536 readw(mch_window + I82975X_C1BNKARC));
537 i82975x_print_dram_timings(mch_window);
540 if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) {
541 i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n");
545 chans = dual_channel_active(mch_window) + 1;
547 /* assuming only one controller, index thus is 0 */
548 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
549 layers[0].size = I82975X_NR_DIMMS;
550 layers[0].is_virt_csrow = true;
551 layers[1].type = EDAC_MC_LAYER_CHANNEL;
552 layers[1].size = I82975X_NR_CSROWS(chans);
553 layers[1].is_virt_csrow = false;
554 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
560 edac_dbg(3, "init mci\n");
561 mci->pdev = &pdev->dev;
562 mci->mtype_cap = MEM_FLAG_DDR2;
563 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
564 mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
565 mci->mod_name = EDAC_MOD_STR;
566 mci->mod_ver = I82975X_REVISION;
567 mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
568 mci->dev_name = pci_name(pdev);
569 mci->edac_check = i82975x_check;
570 mci->ctl_page_to_phys = NULL;
571 edac_dbg(3, "init pvt\n");
572 pvt = (struct i82975x_pvt *) mci->pvt_info;
573 pvt->mch_window = mch_window;
574 i82975x_init_csrows(mci, pdev, mch_window);
575 mci->scrub_mode = SCRUB_HW_SRC;
576 i82975x_get_error_info(mci, &discard); /* clear counters */
578 /* finalize this instance of memory controller with edac core */
579 if (edac_mc_add_mc(mci)) {
580 edac_dbg(3, "failed edac_mc_add_mc()\n");
584 /* get this far and it's successful */
585 edac_dbg(3, "success\n");
597 /* returns count (>= 0), or negative on error */
598 static int __devinit i82975x_init_one(struct pci_dev *pdev,
599 const struct pci_device_id *ent)
605 if (pci_enable_device(pdev) < 0)
608 rc = i82975x_probe1(pdev, ent->driver_data);
610 if (mci_pdev == NULL)
611 mci_pdev = pci_dev_get(pdev);
616 static void __devexit i82975x_remove_one(struct pci_dev *pdev)
618 struct mem_ctl_info *mci;
619 struct i82975x_pvt *pvt;
623 mci = edac_mc_del_mc(&pdev->dev);
629 iounmap( pvt->mch_window );
634 static DEFINE_PCI_DEVICE_TABLE(i82975x_pci_tbl) = {
636 PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
641 } /* 0 terminated list. */
644 MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl);
646 static struct pci_driver i82975x_driver = {
647 .name = EDAC_MOD_STR,
648 .probe = i82975x_init_one,
649 .remove = __devexit_p(i82975x_remove_one),
650 .id_table = i82975x_pci_tbl,
653 static int __init i82975x_init(void)
659 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
662 pci_rc = pci_register_driver(&i82975x_driver);
666 if (mci_pdev == NULL) {
667 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
668 PCI_DEVICE_ID_INTEL_82975_0, NULL);
671 edac_dbg(0, "i82975x pci_get_device fail\n");
676 pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl);
679 edac_dbg(0, "i82975x init fail\n");
688 pci_unregister_driver(&i82975x_driver);
691 if (mci_pdev != NULL)
692 pci_dev_put(mci_pdev);
697 static void __exit i82975x_exit(void)
701 pci_unregister_driver(&i82975x_driver);
703 if (!i82975x_registered) {
704 i82975x_remove_one(mci_pdev);
705 pci_dev_put(mci_pdev);
709 module_init(i82975x_init);
710 module_exit(i82975x_exit);
712 MODULE_LICENSE("GPL");
713 MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
714 MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");
716 module_param(edac_op_state, int, 0444);
717 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");