2 * Radisys 82600 Embedded chipset Memory Controller kernel module
3 * (C) 2005 EADS Astrium
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
8 * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
10 * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
12 * Written with reference to 82600 High Integration Dual PCI System
13 * Controller Data Book:
14 * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
15 * references to this document given in []
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <linux/pci_ids.h>
22 #include <linux/edac.h>
23 #include "edac_core.h"
25 #define R82600_REVISION " Ver: 2.0.2"
26 #define EDAC_MOD_STR "r82600_edac"
28 #define r82600_printk(level, fmt, arg...) \
29 edac_printk(level, "r82600", fmt, ##arg)
31 #define r82600_mc_printk(mci, level, fmt, arg...) \
32 edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
34 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
35 * supports up to four banks of memory. The four banks can support a mix of
36 * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
37 * each of which can be any size from 16MB to 512MB. Both registered (control
38 * signals buffered) and unbuffered DIMM types are supported. Mixing of
39 * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
40 * is not allowed. The 82600 SDRAM interface operates at the same frequency as
41 * the CPU bus, 66MHz, 100MHz or 133MHz."
44 #define R82600_NR_CSROWS 4
45 #define R82600_NR_CHANS 1
46 #define R82600_NR_DIMMS 4
48 #define R82600_BRIDGE_ID 0x8200
50 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
51 #define R82600_DRAMC 0x57 /* Various SDRAM related control bits
54 * 7 SDRAM ISA Hole Enable
55 * 6 Flash Page Mode Enable
56 * 5 ECC Enable: 1=ECC 0=noECC
57 * 4 DRAM DIMM Type: 1=
58 * 3 BIOS Alias Disable
59 * 2 SDRAM BIOS Flash Write Enable
60 * 1:0 SDRAM Refresh Rate: 00=Disabled
61 * 01=7.8usec (256Mbit SDRAMs)
62 * 10=15.6us 11=125usec
65 #define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
66 * More SDRAM related control bits
71 * 7:5 Special SDRAM Mode Select
75 * 1=Drive ECC bits to 0 during
76 * write cycles (i.e. ECC test mode)
78 * 0=Normal ECC functioning
80 * 3 Enhanced Paging Enable
82 * 2 CAS# Latency 0=3clks 1=2clks
84 * 1 RAS# to CAS# Delay 0=3 1=2
86 * 0 RAS# Precharge 0=3 1=2
89 #define R82600_EAP 0x80 /* ECC Error Address Pointer Register
91 * 31 Disable Hardware Scrubbing (RW)
92 * 0=Scrub on corrected read
93 * 1=Don't scrub on corrected read
95 * 30:12 Error Address Pointer (RO)
96 * Upper 19 bits of error address
98 * 11:4 Syndrome Bits (RO)
100 * 3 BSERR# on multibit error (RW)
103 * 2 NMI on Single Bit Eror (RW)
104 * 1=NMI triggered by SBE n.b. other
106 * 0=NMI not triggered
109 * read 1=MBE at EAP (see above)
110 * read 0=no MBE, or SBE occurred first
111 * write 1=Clear MBE status (must also
116 * read 1=SBE at EAP (see above)
117 * read 0=no SBE, or MBE occurred first
118 * write 1=Clear SBE status (must also
123 #define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address
126 * 7:0 Address lines 30:24 - upper limit of
130 struct r82600_error_info {
134 static bool disable_hardware_scrub;
136 static struct edac_pci_ctl_info *r82600_pci;
138 static void r82600_get_error_info(struct mem_ctl_info *mci,
139 struct r82600_error_info *info)
141 struct pci_dev *pdev;
143 pdev = to_pci_dev(mci->pdev);
144 pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
146 if (info->eapr & BIT(0))
147 /* Clear error to allow next error to be reported [p.62] */
148 pci_write_bits32(pdev, R82600_EAP,
149 ((u32) BIT(0) & (u32) BIT(1)),
150 ((u32) BIT(0) & (u32) BIT(1)));
152 if (info->eapr & BIT(1))
153 /* Clear error to allow next error to be reported [p.62] */
154 pci_write_bits32(pdev, R82600_EAP,
155 ((u32) BIT(0) & (u32) BIT(1)),
156 ((u32) BIT(0) & (u32) BIT(1)));
159 static int r82600_process_error_info(struct mem_ctl_info *mci,
160 struct r82600_error_info *info,
169 /* bits 30:12 store the upper 19 bits of the 32 bit error address */
170 eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
171 /* Syndrome in bits 11:4 [p.62] */
172 syndrome = (info->eapr >> 4) & 0xFF;
174 /* the R82600 reports at less than page *
175 * granularity (upper 19 bits only) */
176 page = eapaddr >> PAGE_SHIFT;
178 if (info->eapr & BIT(0)) { /* CE? */
182 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
184 edac_mc_find_csrow_by_page(mci, page),
189 if (info->eapr & BIT(1)) { /* UE? */
193 /* 82600 doesn't give enough info */
194 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
196 edac_mc_find_csrow_by_page(mci, page),
204 static void r82600_check(struct mem_ctl_info *mci)
206 struct r82600_error_info info;
208 edac_dbg(1, "MC%d\n", mci->mc_idx);
209 r82600_get_error_info(mci, &info);
210 r82600_process_error_info(mci, &info, 1);
213 static inline int ecc_enabled(u8 dramcr)
215 return dramcr & BIT(5);
218 static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
221 struct csrow_info *csrow;
222 struct dimm_info *dimm;
224 u8 drbar; /* SDRAM Row Boundary Address Register */
225 u32 row_high_limit, row_high_limit_last;
226 u32 reg_sdram, ecc_on, row_base;
228 ecc_on = ecc_enabled(dramcr);
229 reg_sdram = dramcr & BIT(4);
230 row_high_limit_last = 0;
232 for (index = 0; index < mci->nr_csrows; index++) {
233 csrow = mci->csrows[index];
234 dimm = csrow->channels[0]->dimm;
236 /* find the DRAM Chip Select Base address and mask */
237 pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
239 edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar);
241 row_high_limit = ((u32) drbar << 24);
242 /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
244 edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n",
245 index, row_high_limit, row_high_limit_last);
247 /* Empty row [p.57] */
248 if (row_high_limit == row_high_limit_last)
251 row_base = row_high_limit_last;
253 csrow->first_page = row_base >> PAGE_SHIFT;
254 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
256 dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
257 /* Error address is top 19 bits - so granularity is *
259 dimm->grain = 1 << 14;
260 dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
261 /* FIXME - check that this is unknowable with this chipset */
262 dimm->dtype = DEV_UNKNOWN;
264 /* Mode is global on 82600 */
265 dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
266 row_high_limit_last = row_high_limit;
270 static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
272 struct mem_ctl_info *mci;
273 struct edac_mc_layer layers[2];
277 u32 sdram_refresh_rate;
278 struct r82600_error_info discard;
281 pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
282 pci_read_config_dword(pdev, R82600_EAP, &eapr);
283 scrub_disabled = eapr & BIT(31);
284 sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
285 edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate);
286 edac_dbg(2, "DRAMC register = %#0x\n", dramcr);
287 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
288 layers[0].size = R82600_NR_CSROWS;
289 layers[0].is_virt_csrow = true;
290 layers[1].type = EDAC_MC_LAYER_CHANNEL;
291 layers[1].size = R82600_NR_CHANS;
292 layers[1].is_virt_csrow = false;
293 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
297 edac_dbg(0, "mci = %p\n", mci);
298 mci->pdev = &pdev->dev;
299 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
300 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
301 /* FIXME try to work out if the chip leads have been used for COM2
302 * instead on this board? [MA6?] MAYBE:
305 /* On the R82600, the pins for memory bits 72:65 - i.e. the *
306 * EC bits are shared with the pins for COM2 (!), so if COM2 *
307 * is enabled, we assume COM2 is wired up, and thus no EDAC *
309 mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
311 if (ecc_enabled(dramcr)) {
313 edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n",
316 mci->edac_cap = EDAC_FLAG_NONE;
318 mci->mod_name = EDAC_MOD_STR;
319 mci->mod_ver = R82600_REVISION;
320 mci->ctl_name = "R82600";
321 mci->dev_name = pci_name(pdev);
322 mci->edac_check = r82600_check;
323 mci->ctl_page_to_phys = NULL;
324 r82600_init_csrows(mci, pdev, dramcr);
325 r82600_get_error_info(mci, &discard); /* clear counters */
327 /* Here we assume that we will never see multiple instances of this
328 * type of memory controller. The ID is therefore hardcoded to 0.
330 if (edac_mc_add_mc(mci)) {
331 edac_dbg(3, "failed edac_mc_add_mc()\n");
335 /* get this far and it's successful */
337 if (disable_hardware_scrub) {
338 edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n");
339 pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
342 /* allocating generic PCI control info */
343 r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
346 "%s(): Unable to create PCI control\n",
349 "%s(): PCI error report via EDAC not setup\n",
353 edac_dbg(3, "success\n");
361 /* returns count (>= 0), or negative on error */
362 static int __devinit r82600_init_one(struct pci_dev *pdev,
363 const struct pci_device_id *ent)
367 /* don't need to call pci_enable_device() */
368 return r82600_probe1(pdev, ent->driver_data);
371 static void __devexit r82600_remove_one(struct pci_dev *pdev)
373 struct mem_ctl_info *mci;
378 edac_pci_release_generic_ctl(r82600_pci);
380 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
386 static DEFINE_PCI_DEVICE_TABLE(r82600_pci_tbl) = {
388 PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
392 } /* 0 terminated list. */
395 MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
397 static struct pci_driver r82600_driver = {
398 .name = EDAC_MOD_STR,
399 .probe = r82600_init_one,
400 .remove = __devexit_p(r82600_remove_one),
401 .id_table = r82600_pci_tbl,
404 static int __init r82600_init(void)
406 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
409 return pci_register_driver(&r82600_driver);
412 static void __exit r82600_exit(void)
414 pci_unregister_driver(&r82600_driver);
417 module_init(r82600_init);
418 module_exit(r82600_exit);
420 MODULE_LICENSE("GPL");
421 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
422 "on behalf of EADS Astrium");
423 MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
425 module_param(disable_hardware_scrub, bool, 0644);
426 MODULE_PARM_DESC(disable_hardware_scrub,
427 "If set, disable the chipset's automatic scrub for CEs");
429 module_param(edac_op_state, int, 0444);
430 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");