1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab <mchehab@redhat.com>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <asm/processor.h>
26 #include "edac_core.h"
29 static LIST_HEAD(sbridge_edac_list);
30 static DEFINE_MUTEX(sbridge_edac_lock);
34 * Alter this version for the module when modifications are made
36 #define SBRIDGE_REVISION " Ver: 1.0.0 "
37 #define EDAC_MOD_STR "sbridge_edac"
42 #define sbridge_printk(level, fmt, arg...) \
43 edac_printk(level, "sbridge", fmt, ##arg)
45 #define sbridge_mc_printk(mci, level, fmt, arg...) \
46 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
49 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 #define GET_BITFIELD(v, lo, hi) \
52 (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))
55 * sbridge Memory Controller Registers
59 * FIXME: For now, let's order by device function, as it makes
60 * easier for driver's development proccess. This table should be
61 * moved to pci_id.h when submitted upstream
63 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
64 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
65 #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
66 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
67 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
68 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
69 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
70 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
71 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
72 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
73 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
76 * Currently, unused, but will be needed in the future
77 * implementations, as they hold the error counters
79 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
80 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
81 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
82 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
84 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
85 static const u32 dram_rule[] = {
86 0x80, 0x88, 0x90, 0x98, 0xa0,
87 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
89 #define MAX_SAD ARRAY_SIZE(dram_rule)
91 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
92 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
93 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
94 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
96 static char *get_dram_attr(u32 reg)
98 switch(DRAM_ATTR(reg)) {
110 static const u32 interleave_list[] = {
111 0x84, 0x8c, 0x94, 0x9c, 0xa4,
112 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
114 #define MAX_INTERLEAVE ARRAY_SIZE(interleave_list)
116 #define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2)
117 #define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5)
118 #define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10)
119 #define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13)
120 #define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18)
121 #define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21)
122 #define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26)
123 #define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29)
125 static inline int sad_pkg(u32 reg, int interleave)
127 switch (interleave) {
129 return SAD_PKG0(reg);
131 return SAD_PKG1(reg);
133 return SAD_PKG2(reg);
135 return SAD_PKG3(reg);
137 return SAD_PKG4(reg);
139 return SAD_PKG5(reg);
141 return SAD_PKG6(reg);
143 return SAD_PKG7(reg);
149 /* Devices 12 Function 7 */
154 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
155 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
157 /* Device 13 Function 6 */
159 #define SAD_TARGET 0xf0
161 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
163 #define SAD_CONTROL 0xf4
165 #define NODE_ID(reg) GET_BITFIELD(reg, 0, 2)
167 /* Device 14 function 0 */
169 static const u32 tad_dram_rule[] = {
170 0x40, 0x44, 0x48, 0x4c,
171 0x50, 0x54, 0x58, 0x5c,
172 0x60, 0x64, 0x68, 0x6c,
174 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
176 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
177 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
178 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
179 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
180 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
181 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
182 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
184 /* Device 15, function 0 */
188 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
189 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
190 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
192 /* Device 15, function 1 */
194 #define RASENABLES 0xac
195 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
197 /* Device 15, functions 2-5 */
199 static const int mtr_regs[] = {
203 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
204 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
205 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
206 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
207 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
209 static const u32 tad_ch_nilv_offset[] = {
210 0x90, 0x94, 0x98, 0x9c,
211 0xa0, 0xa4, 0xa8, 0xac,
212 0xb0, 0xb4, 0xb8, 0xbc,
214 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
215 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
217 static const u32 rir_way_limit[] = {
218 0x108, 0x10c, 0x110, 0x114, 0x118,
220 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
222 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
223 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
224 #define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff)
226 #define MAX_RIR_WAY 8
228 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
229 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
230 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
231 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
232 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
233 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
236 #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
237 #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
239 /* Device 16, functions 2-7 */
242 * FIXME: Implement the error count reads directly
245 static const u32 correrrcnt[] = {
246 0x104, 0x108, 0x10c, 0x110,
249 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
250 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
251 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
252 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
254 static const u32 correrrthrsld[] = {
255 0x11c, 0x120, 0x124, 0x128,
258 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
259 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
262 /* Device 17, function 0 */
264 #define RANK_CFG_A 0x0328
266 #define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)
272 #define NUM_CHANNELS 4
273 #define MAX_DIMMS 3 /* Max DIMMS per channel */
275 struct sbridge_info {
279 struct sbridge_channel {
284 struct pci_id_descr {
291 struct pci_id_table {
292 const struct pci_id_descr *descr;
297 struct list_head list;
299 u8 node_id, source_id;
300 struct pci_dev **pdev;
302 struct mem_ctl_info *mci;
306 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
307 struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0;
308 struct pci_dev *pci_br;
309 struct pci_dev *pci_tad[NUM_CHANNELS];
311 struct sbridge_dev *sbridge_dev;
313 struct sbridge_info info;
314 struct sbridge_channel channel[NUM_CHANNELS];
316 int csrow_map[NUM_CHANNELS][MAX_DIMMS];
318 /* Memory type detection */
319 bool is_mirrored, is_lockstep, is_close_pg;
321 /* Fifo double buffers */
322 struct mce mce_entry[MCE_LOG_LEN];
323 struct mce mce_outentry[MCE_LOG_LEN];
325 /* Fifo in/out counters */
326 unsigned mce_in, mce_out;
328 /* Count indicator to show errors not got */
329 unsigned mce_overrun;
331 /* Memory description */
335 #define PCI_DESCR(device, function, device_id) \
337 .func = (function), \
338 .dev_id = (device_id)
340 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
341 /* Processor Home Agent */
342 { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0) },
344 /* Memory controller */
345 { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA) },
346 { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS) },
347 { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0) },
348 { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1) },
349 { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2) },
350 { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3) },
351 { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO) },
353 /* System Address Decoder */
354 { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0) },
355 { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1) },
357 /* Broadcast Registers */
358 { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR) },
361 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
362 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
363 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
364 {0,} /* 0 terminated list. */
368 * pci_device_id table for which devices we are looking for
370 static const struct pci_device_id sbridge_pci_tbl[] __devinitdata = {
371 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
372 {0,} /* 0 terminated list. */
376 /****************************************************************************
377 Anciliary status routines
378 ****************************************************************************/
380 static inline int numrank(u32 mtr)
382 int ranks = (1 << RANK_CNT_BITS(mtr));
385 debugf0("Invalid number of ranks: %d (max = 4) raw value = %x (%04x)",
386 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
393 static inline int numrow(u32 mtr)
395 int rows = (RANK_WIDTH_BITS(mtr) + 12);
397 if (rows < 13 || rows > 18) {
398 debugf0("Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)",
399 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
406 static inline int numcol(u32 mtr)
408 int cols = (COL_WIDTH_BITS(mtr) + 10);
411 debugf0("Invalid number of cols: %d (max = 4) raw value = %x (%04x)",
412 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
419 static struct sbridge_dev *get_sbridge_dev(u8 bus)
421 struct sbridge_dev *sbridge_dev;
423 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
424 if (sbridge_dev->bus == bus)
431 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
432 const struct pci_id_table *table)
434 struct sbridge_dev *sbridge_dev;
436 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
440 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
442 if (!sbridge_dev->pdev) {
447 sbridge_dev->bus = bus;
448 sbridge_dev->n_devs = table->n_devs;
449 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
454 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
456 list_del(&sbridge_dev->list);
457 kfree(sbridge_dev->pdev);
461 /****************************************************************************
462 Memory check routines
463 ****************************************************************************/
464 static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot,
467 struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus);
473 for (i = 0; i < sbridge_dev->n_devs; i++) {
474 if (!sbridge_dev->pdev[i])
477 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot &&
478 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) {
479 debugf1("Associated %02x.%02x.%d with %p\n",
480 bus, slot, func, sbridge_dev->pdev[i]);
481 return sbridge_dev->pdev[i];
489 * sbridge_get_active_channels() - gets the number of channels and csrows
491 * @channels: Number of channels that will be returned
492 * @csrows: Number of csrows found
494 * Since EDAC core needs to know in advance the number of available channels
495 * and csrows, in order to allocate memory for csrows/channels, it is needed
496 * to run two similar steps. At the first step, implemented on this function,
497 * it checks the number of csrows/channels present at one socket, identified
498 * by the associated PCI bus.
499 * this is used in order to properly allocate the size of mci components.
500 * Note: one csrow is one dimm.
502 static int sbridge_get_active_channels(const u8 bus, unsigned *channels,
505 struct pci_dev *pdev = NULL;
512 pdev = get_pdev_slot_func(bus, 15, 0);
514 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
520 pci_read_config_dword(pdev, MCMTR, &mcmtr);
521 if (!IS_ECC_ENABLED(mcmtr)) {
522 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
526 for (i = 0; i < NUM_CHANNELS; i++) {
529 /* Device 15 functions 2 - 5 */
530 pdev = get_pdev_slot_func(bus, 15, 2 + i);
532 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
539 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
540 pci_read_config_dword(pdev, mtr_regs[j], &mtr);
541 debugf1("Bus#%02x channel #%d MTR%d = %x\n", bus, i, j, mtr);
542 if (IS_DIMM_PRESENT(mtr))
547 debugf0("Number of active channels: %d, number of active dimms: %d\n",
553 static int get_dimm_config(const struct mem_ctl_info *mci)
555 struct sbridge_pvt *pvt = mci->pvt_info;
556 struct csrow_info *csr;
557 int i, j, banks, ranks, rows, cols, size, npages;
559 unsigned long last_page = 0;
563 pci_read_config_dword(pvt->pci_br, SAD_TARGET, ®);
564 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
566 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, ®);
567 pvt->sbridge_dev->node_id = NODE_ID(reg);
568 debugf0("mc#%d: Node ID: %d, source ID: %d\n",
569 pvt->sbridge_dev->mc,
570 pvt->sbridge_dev->node_id,
571 pvt->sbridge_dev->source_id);
573 pci_read_config_dword(pvt->pci_ras, RASENABLES, ®);
574 if (IS_MIRROR_ENABLED(reg)) {
575 debugf0("Memory mirror is enabled\n");
576 pvt->is_mirrored = true;
578 debugf0("Memory mirror is disabled\n");
579 pvt->is_mirrored = false;
582 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
583 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
584 debugf0("Lockstep is enabled\n");
585 mode = EDAC_S8ECD8ED;
586 pvt->is_lockstep = true;
588 debugf0("Lockstep is disabled\n");
589 mode = EDAC_S4ECD4ED;
590 pvt->is_lockstep = false;
592 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
593 debugf0("address map is on closed page mode\n");
594 pvt->is_close_pg = true;
596 debugf0("address map is on open page mode\n");
597 pvt->is_close_pg = false;
600 pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, ®);
601 if (IS_RDIMM_ENABLED(reg)) {
602 /* FIXME: Can also be LRDIMM */
603 debugf0("Memory is registered\n");
606 debugf0("Memory is unregistered\n");
610 /* On all supported DDR3 DIMM types, there are 8 banks available */
613 for (i = 0; i < NUM_CHANNELS; i++) {
616 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
617 pci_read_config_dword(pvt->pci_tad[i],
619 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr);
620 if (IS_DIMM_PRESENT(mtr)) {
621 pvt->channel[i].dimms++;
623 ranks = numrank(mtr);
627 /* DDR3 has 8 I/O banks */
628 size = (rows * cols * banks * ranks) >> (20 - 3);
629 npages = MiB_TO_PAGES(size);
631 debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
632 pvt->sbridge_dev->mc, i, j,
634 banks, ranks, rows, cols);
635 csr = &mci->csrows[csrow];
637 csr->first_page = last_page;
638 csr->last_page = last_page + npages - 1;
639 csr->page_mask = 0UL; /* Unused */
640 csr->nr_pages = npages;
642 csr->csrow_idx = csrow;
643 csr->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
647 csr->edac_mode = mode;
648 csr->nr_channels = 1;
649 csr->channels[0].chan_idx = i;
650 csr->channels[0].ce_count = 0;
651 pvt->csrow_map[i][j] = csrow;
652 snprintf(csr->channels[0].label,
653 sizeof(csr->channels[0].label),
654 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
655 pvt->sbridge_dev->source_id, i, j);
665 static void get_memory_layout(const struct mem_ctl_info *mci)
667 struct sbridge_pvt *pvt = mci->pvt_info;
668 int i, j, k, n_sads, n_tads, sad_interl;
675 * Step 1) Get TOLM/TOHM ranges
678 /* Address range is 32:28 */
679 pci_read_config_dword(pvt->pci_sad1, TOLM,
681 pvt->tolm = GET_TOLM(reg);
682 tmp_mb = (1 + pvt->tolm) >> 20;
684 debugf0("TOLM: %Lu.%03Lu GB (0x%016Lx)\n",
685 tmp_mb / 1000, tmp_mb % 1000, (u64)pvt->tolm);
687 /* Address range is already 45:25 */
688 pci_read_config_dword(pvt->pci_sad1, TOHM,
690 pvt->tohm = GET_TOHM(reg);
691 tmp_mb = (1 + pvt->tohm) >> 20;
693 debugf0("TOHM: %Lu.%03Lu GB (0x%016Lx)",
694 tmp_mb / 1000, tmp_mb % 1000, (u64)pvt->tohm);
697 * Step 2) Get SAD range and SAD Interleave list
698 * TAD registers contain the interleave wayness. However, it
699 * seems simpler to just discover it indirectly, with the
703 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
704 /* SAD_LIMIT Address range is 45:26 */
705 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
707 limit = SAD_LIMIT(reg);
709 if (!DRAM_RULE_ENABLE(reg))
715 tmp_mb = (limit + 1) >> 20;
716 debugf0("SAD#%d %s up to %Lu.%03Lu GB (0x%016Lx) %s reg=0x%08x\n",
719 tmp_mb / 1000, tmp_mb % 1000,
720 ((u64)tmp_mb) << 20L,
721 INTERLEAVE_MODE(reg) ? "Interleave: 8:6" : "Interleave: [8:6]XOR[18:16]",
725 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
727 sad_interl = sad_pkg(reg, 0);
728 for (j = 0; j < 8; j++) {
729 if (j > 0 && sad_interl == sad_pkg(reg, j))
732 debugf0("SAD#%d, interleave #%d: %d\n",
733 n_sads, j, sad_pkg(reg, j));
738 * Step 3) Get TAD range
741 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
742 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
744 limit = TAD_LIMIT(reg);
747 tmp_mb = (limit + 1) >> 20;
749 debugf0("TAD#%d: up to %Lu.%03Lu GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
750 n_tads, tmp_mb / 1000, tmp_mb % 1000,
751 ((u64)tmp_mb) << 20L,
763 * Step 4) Get TAD offsets, per each channel
765 for (i = 0; i < NUM_CHANNELS; i++) {
766 if (!pvt->channel[i].dimms)
768 for (j = 0; j < n_tads; j++) {
769 pci_read_config_dword(pvt->pci_tad[i],
770 tad_ch_nilv_offset[j],
772 tmp_mb = TAD_OFFSET(reg) >> 20;
773 debugf0("TAD CH#%d, offset #%d: %Lu.%03Lu GB (0x%016Lx), reg=0x%08x\n",
775 tmp_mb / 1000, tmp_mb % 1000,
776 ((u64)tmp_mb) << 20L,
782 * Step 6) Get RIR Wayness/Limit, per each channel
784 for (i = 0; i < NUM_CHANNELS; i++) {
785 if (!pvt->channel[i].dimms)
787 for (j = 0; j < MAX_RIR_RANGES; j++) {
788 pci_read_config_dword(pvt->pci_tad[i],
792 if (!IS_RIR_VALID(reg))
795 tmp_mb = RIR_LIMIT(reg) >> 20;
796 rir_way = 1 << RIR_WAY(reg);
797 debugf0("CH#%d RIR#%d, limit: %Lu.%03Lu GB (0x%016Lx), way: %d, reg=0x%08x\n",
799 tmp_mb / 1000, tmp_mb % 1000,
800 ((u64)tmp_mb) << 20L,
804 for (k = 0; k < rir_way; k++) {
805 pci_read_config_dword(pvt->pci_tad[i],
808 tmp_mb = RIR_OFFSET(reg) << 6;
810 debugf0("CH#%d RIR#%d INTL#%d, offset %Lu.%03Lu GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
812 tmp_mb / 1000, tmp_mb % 1000,
813 ((u64)tmp_mb) << 20L,
814 (u32)RIR_RNK_TGT(reg),
821 struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
823 struct sbridge_dev *sbridge_dev;
825 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
826 if (sbridge_dev->node_id == node_id)
827 return sbridge_dev->mci;
832 static int get_memory_error_data(struct mem_ctl_info *mci,
839 struct mem_ctl_info *new_mci;
840 struct sbridge_pvt *pvt = mci->pvt_info;
842 int n_rir, n_sads, n_tads, sad_way, sck_xch;
843 int sad_interl, idx, base_ch;
845 unsigned sad_interleave[MAX_INTERLEAVE];
850 u64 ch_addr, offset, limit, prv = 0;
854 * Step 0) Check if the address is at special memory ranges
855 * The check bellow is probably enough to fill all cases where
856 * the error is not inside a memory, except for the legacy
857 * range (e. g. VGA addresses). It is unlikely, however, that the
858 * memory controller would generate an error on that range.
860 if ((addr > (u64) pvt->tolm) && (addr < (1L << 32))) {
861 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
862 edac_mc_handle_ce_no_info(mci, msg);
865 if (addr >= (u64)pvt->tohm) {
866 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
867 edac_mc_handle_ce_no_info(mci, msg);
874 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
875 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
878 if (!DRAM_RULE_ENABLE(reg))
881 limit = SAD_LIMIT(reg);
883 sprintf(msg, "Can't discover the memory socket");
884 edac_mc_handle_ce_no_info(mci, msg);
891 if (n_sads == MAX_SAD) {
892 sprintf(msg, "Can't discover the memory socket");
893 edac_mc_handle_ce_no_info(mci, msg);
896 area_type = get_dram_attr(reg);
897 interleave_mode = INTERLEAVE_MODE(reg);
899 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
901 sad_interl = sad_pkg(reg, 0);
902 for (sad_way = 0; sad_way < 8; sad_way++) {
903 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way))
905 sad_interleave[sad_way] = sad_pkg(reg, sad_way);
906 debugf0("SAD interleave #%d: %d\n",
907 sad_way, sad_interleave[sad_way]);
909 debugf0("mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
910 pvt->sbridge_dev->mc,
915 INTERLEAVE_MODE(reg) ? "" : "XOR[18:16]");
917 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
919 idx = (addr >> 6) & 7;
933 sprintf(msg, "Can't discover socket interleave");
934 edac_mc_handle_ce_no_info(mci, msg);
937 *socket = sad_interleave[idx];
938 debugf0("SAD interleave index: %d (wayness %d) = CPU socket %d\n",
939 idx, sad_way, *socket);
942 * Move to the proper node structure, in order to access the
943 * right PCI registers
945 new_mci = get_mci_for_node_id(*socket);
947 sprintf(msg, "Struct for socket #%u wasn't initialized",
949 edac_mc_handle_ce_no_info(mci, msg);
956 * Step 2) Get memory channel
959 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
960 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
962 limit = TAD_LIMIT(reg);
964 sprintf(msg, "Can't discover the memory channel");
965 edac_mc_handle_ce_no_info(mci, msg);
972 ch_way = TAD_CH(reg) + 1;
973 sck_way = TAD_SOCK(reg) + 1;
975 * FIXME: Is it right to always use channel 0 for offsets?
977 pci_read_config_dword(pvt->pci_tad[0],
978 tad_ch_nilv_offset[n_tads],
984 idx = addr >> (6 + sck_way);
988 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
992 base_ch = TAD_TGT0(reg);
995 base_ch = TAD_TGT1(reg);
998 base_ch = TAD_TGT2(reg);
1001 base_ch = TAD_TGT3(reg);
1004 sprintf(msg, "Can't discover the TAD target");
1005 edac_mc_handle_ce_no_info(mci, msg);
1008 *channel_mask = 1 << base_ch;
1010 if (pvt->is_mirrored) {
1011 *channel_mask |= 1 << ((base_ch + 2) % 4);
1015 sck_xch = 1 << sck_way * (ch_way >> 1);
1018 sprintf(msg, "Invalid mirror set. Can't decode addr");
1019 edac_mc_handle_ce_no_info(mci, msg);
1023 sck_xch = (1 << sck_way) * ch_way;
1025 if (pvt->is_lockstep)
1026 *channel_mask |= 1 << ((base_ch + 1) % 4);
1028 offset = TAD_OFFSET(tad_offset);
1030 debugf0("TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1041 /* Calculate channel address */
1042 /* Remove the TAD offset */
1044 if (offset > addr) {
1045 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1047 edac_mc_handle_ce_no_info(mci, msg);
1051 /* Store the low bits [0:6] of the addr */
1052 ch_addr = addr & 0x7f;
1053 /* Remove socket wayness and remove 6 bits */
1057 /* Divide by channel way */
1058 addr = addr / ch_way;
1060 /* Recover the last 6 bits */
1061 ch_addr |= addr << 6;
1064 * Step 3) Decode rank
1066 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1067 pci_read_config_dword(pvt->pci_tad[base_ch],
1068 rir_way_limit[n_rir],
1071 if (!IS_RIR_VALID(reg))
1074 limit = RIR_LIMIT(reg);
1076 debugf0("RIR#%d, limit: %Lu.%03Lu GB (0x%016Lx), way: %d\n",
1078 (limit >> 20) / 1000, (limit >> 20) % 1000,
1081 if (ch_addr <= limit)
1084 if (n_rir == MAX_RIR_RANGES) {
1085 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1087 edac_mc_handle_ce_no_info(mci, msg);
1090 rir_way = RIR_WAY(reg);
1091 if (pvt->is_close_pg)
1092 idx = (ch_addr >> 6);
1094 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1095 idx %= 1 << rir_way;
1097 pci_read_config_dword(pvt->pci_tad[base_ch],
1098 rir_offset[n_rir][idx],
1100 *rank = RIR_RNK_TGT(reg);
1102 debugf0("RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1112 /****************************************************************************
1113 Device initialization routines: put/get, init/exit
1114 ****************************************************************************/
1117 * sbridge_put_all_devices 'put' all the devices that we have
1118 * reserved via 'get'
1120 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1124 debugf0(__FILE__ ": %s()\n", __func__);
1125 for (i = 0; i < sbridge_dev->n_devs; i++) {
1126 struct pci_dev *pdev = sbridge_dev->pdev[i];
1129 debugf0("Removing dev %02x:%02x.%d\n",
1131 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1136 static void sbridge_put_all_devices(void)
1138 struct sbridge_dev *sbridge_dev, *tmp;
1140 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1141 sbridge_put_devices(sbridge_dev);
1142 free_sbridge_dev(sbridge_dev);
1147 * sbridge_get_all_devices Find and perform 'get' operation on the MCH's
1148 * device/functions we want to reference for this driver
1150 * Need to 'get' device 16 func 1 and func 2
1152 static int sbridge_get_onedevice(struct pci_dev **prev,
1154 const struct pci_id_table *table,
1155 const unsigned devno)
1157 struct sbridge_dev *sbridge_dev;
1158 const struct pci_id_descr *dev_descr = &table->descr[devno];
1160 struct pci_dev *pdev = NULL;
1163 sbridge_printk(KERN_INFO,
1164 "Seeking for: dev %02x.%d PCI ID %04x:%04x\n",
1165 dev_descr->dev, dev_descr->func,
1166 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1168 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1169 dev_descr->dev_id, *prev);
1177 if (dev_descr->optional)
1183 sbridge_printk(KERN_INFO,
1184 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1185 dev_descr->dev, dev_descr->func,
1186 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1188 /* End of list, leave */
1191 bus = pdev->bus->number;
1193 sbridge_dev = get_sbridge_dev(bus);
1195 sbridge_dev = alloc_sbridge_dev(bus, table);
1203 if (sbridge_dev->pdev[devno]) {
1204 sbridge_printk(KERN_ERR,
1205 "Duplicated device for "
1206 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1207 bus, dev_descr->dev, dev_descr->func,
1208 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1213 sbridge_dev->pdev[devno] = pdev;
1216 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1217 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1218 sbridge_printk(KERN_ERR,
1219 "Device PCI ID %04x:%04x "
1220 "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n",
1221 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1222 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1223 bus, dev_descr->dev, dev_descr->func);
1227 /* Be sure that the device is enabled */
1228 if (unlikely(pci_enable_device(pdev) < 0)) {
1229 sbridge_printk(KERN_ERR,
1231 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1232 bus, dev_descr->dev, dev_descr->func,
1233 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1237 debugf0("Detected dev %02x:%d.%d PCI ID %04x:%04x\n",
1238 bus, dev_descr->dev,
1240 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1243 * As stated on drivers/pci/search.c, the reference count for
1244 * @from is always decremented if it is not %NULL. So, as we need
1245 * to get all devices up to null, we need to do a get for the device
1254 static int sbridge_get_all_devices(u8 *num_mc)
1257 struct pci_dev *pdev = NULL;
1258 const struct pci_id_table *table = pci_dev_descr_sbridge_table;
1260 while (table && table->descr) {
1261 for (i = 0; i < table->n_devs; i++) {
1264 rc = sbridge_get_onedevice(&pdev, num_mc,
1271 sbridge_put_all_devices();
1282 static int mci_bind_devs(struct mem_ctl_info *mci,
1283 struct sbridge_dev *sbridge_dev)
1285 struct sbridge_pvt *pvt = mci->pvt_info;
1286 struct pci_dev *pdev;
1289 for (i = 0; i < sbridge_dev->n_devs; i++) {
1290 pdev = sbridge_dev->pdev[i];
1293 slot = PCI_SLOT(pdev->devfn);
1294 func = PCI_FUNC(pdev->devfn);
1299 pvt->pci_sad0 = pdev;
1302 pvt->pci_sad1 = pdev;
1320 pvt->pci_ha0 = pdev;
1332 pvt->pci_ras = pdev;
1338 pvt->pci_tad[func - 2] = pdev;
1347 pvt->pci_ddrio = pdev;
1357 debugf0("Associated PCI %02x.%02d.%d with dev = %p\n",
1359 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1363 /* Check if everything were registered */
1364 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1365 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta ||
1369 for (i = 0; i < NUM_CHANNELS; i++) {
1370 if (!pvt->pci_tad[i])
1376 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1380 sbridge_printk(KERN_ERR, "Device %d, function %d "
1381 "is out of the expected range\n",
1386 /****************************************************************************
1387 Error check routines
1388 ****************************************************************************/
1391 * While Sandy Bridge has error count registers, SMI BIOS read values from
1392 * and resets the counters. So, they are not reliable for the OS to read
1393 * from them. So, we have no option but to just trust on whatever MCE is
1394 * telling us about the errors.
1396 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1397 const struct mce *m)
1399 struct mem_ctl_info *new_mci;
1400 struct sbridge_pvt *pvt = mci->pvt_info;
1401 char *type, *optype, *msg, *recoverable_msg;
1402 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1403 bool overflow = GET_BITFIELD(m->status, 62, 62);
1404 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1405 bool recoverable = GET_BITFIELD(m->status, 56, 56);
1406 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1407 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1408 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1409 u32 channel = GET_BITFIELD(m->status, 0, 3);
1410 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1411 long channel_mask, first_channel;
1413 int csrow, rc, dimm;
1414 char *area_type = "Unknown";
1422 * According with Table 15-9 of the Intel Archictecture spec vol 3A,
1423 * memory errors should fit in this mask:
1424 * 000f 0000 1mmm cccc (binary)
1426 * f = Correction Report Filtering Bit. If 1, subsequent errors
1430 * If the mask doesn't match, report an error to the parsing logic
1432 if (! ((errcode & 0xef80) == 0x80)) {
1433 optype = "Can't parse: it is not a mem";
1435 switch (optypenum) {
1437 optype = "generic undef request";
1440 optype = "memory read";
1443 optype = "memory write";
1446 optype = "addr/cmd";
1449 optype = "memory scrubbing";
1452 optype = "reserved";
1457 rc = get_memory_error_data(mci, m->addr, &socket,
1458 &channel_mask, &rank, area_type);
1461 new_mci = get_mci_for_node_id(socket);
1463 edac_mc_handle_ce_no_info(mci, "Error: socket got corrupted!");
1467 pvt = mci->pvt_info;
1469 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1478 csrow = pvt->csrow_map[first_channel][dimm];
1480 if (uncorrected_error && recoverable)
1481 recoverable_msg = " recoverable";
1483 recoverable_msg = "";
1486 * FIXME: What should we do with "channel" information on mcelog?
1487 * Probably, we can just discard it, as the channel information
1488 * comes from the get_memory_error_data() address decoding
1490 msg = kasprintf(GFP_ATOMIC,
1491 "%d %s error(s): %s on %s area %s%s: cpu=%d Err=%04x:%04x (ch=%d), "
1492 "addr = 0x%08llx => socket=%d, Channel=%ld(mask=%ld), rank=%d\n",
1498 overflow ? "OVERFLOW" : "",
1501 channel, /* 1111b means not specified */
1502 (long long) m->addr,
1504 first_channel, /* This is the real channel on SB */
1510 /* Call the helper to output message */
1511 if (uncorrected_error)
1512 edac_mc_handle_fbd_ue(mci, csrow, 0, 0, msg);
1514 edac_mc_handle_fbd_ce(mci, csrow, 0, msg);
1520 * sbridge_check_error Retrieve and process errors reported by the
1521 * hardware. Called by the Core module.
1523 static void sbridge_check_error(struct mem_ctl_info *mci)
1525 struct sbridge_pvt *pvt = mci->pvt_info;
1531 * MCE first step: Copy all mce errors into a temporary buffer
1532 * We use a double buffering here, to reduce the risk of
1536 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1541 m = pvt->mce_outentry;
1542 if (pvt->mce_in + count > MCE_LOG_LEN) {
1543 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1545 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1551 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1553 pvt->mce_in += count;
1556 if (pvt->mce_overrun) {
1557 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
1560 pvt->mce_overrun = 0;
1564 * MCE second step: parse errors and display
1566 for (i = 0; i < count; i++)
1567 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
1571 * sbridge_mce_check_error Replicates mcelog routine to get errors
1572 * This routine simply queues mcelog errors, and
1573 * return. The error itself should be handled later
1574 * by sbridge_check_error.
1575 * WARNING: As this routine should be called at NMI time, extra care should
1576 * be taken to avoid deadlocks, and to be as fast as possible.
1578 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
1581 struct mce *mce = (struct mce *)data;
1582 struct mem_ctl_info *mci;
1583 struct sbridge_pvt *pvt;
1585 mci = get_mci_for_node_id(mce->socketid);
1588 pvt = mci->pvt_info;
1591 * Just let mcelog handle it if the error is
1592 * outside the memory controller. A memory error
1593 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
1594 * bit 12 has an special meaning.
1596 if ((mce->status & 0xefff) >> 7 != 1)
1599 printk("sbridge: HANDLING MCE MEMORY ERROR\n");
1601 printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
1602 mce->extcpu, mce->mcgstatus, mce->bank, mce->status);
1603 printk("TSC %llx ", mce->tsc);
1604 printk("ADDR %llx ", mce->addr);
1605 printk("MISC %llx ", mce->misc);
1607 printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
1608 mce->cpuvendor, mce->cpuid, mce->time,
1609 mce->socketid, mce->apicid);
1612 /* Only handle if it is the right mc controller */
1613 if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc)
1618 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1624 /* Copy memory error at the ringbuffer */
1625 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1627 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1629 /* Handle fatal errors immediately */
1630 if (mce->mcgstatus & 1)
1631 sbridge_check_error(mci);
1633 /* Advice mcelog that the error were handled */
1637 static struct notifier_block sbridge_mce_dec = {
1638 .notifier_call = sbridge_mce_check_error,
1641 /****************************************************************************
1642 EDAC register/unregister logic
1643 ****************************************************************************/
1645 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1647 struct mem_ctl_info *mci = sbridge_dev->mci;
1648 struct sbridge_pvt *pvt;
1650 if (unlikely(!mci || !mci->pvt_info)) {
1651 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
1652 __func__, &sbridge_dev->pdev[0]->dev);
1654 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
1658 pvt = mci->pvt_info;
1660 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1661 __func__, mci, &sbridge_dev->pdev[0]->dev);
1663 atomic_notifier_chain_unregister(&x86_mce_decoder_chain,
1666 /* Remove MC sysfs nodes */
1667 edac_mc_del_mc(mci->dev);
1669 debugf1("%s: free mci struct\n", mci->ctl_name);
1670 kfree(mci->ctl_name);
1672 sbridge_dev->mci = NULL;
1675 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
1677 struct mem_ctl_info *mci;
1678 struct sbridge_pvt *pvt;
1679 int rc, channels, csrows;
1681 /* Check the number of active and not disabled channels */
1682 rc = sbridge_get_active_channels(sbridge_dev->bus, &channels, &csrows);
1683 if (unlikely(rc < 0))
1686 /* allocate a new MC control structure */
1687 mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, sbridge_dev->mc);
1691 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1692 __func__, mci, &sbridge_dev->pdev[0]->dev);
1694 pvt = mci->pvt_info;
1695 memset(pvt, 0, sizeof(*pvt));
1697 /* Associate sbridge_dev and mci for future usage */
1698 pvt->sbridge_dev = sbridge_dev;
1699 sbridge_dev->mci = mci;
1701 mci->mtype_cap = MEM_FLAG_DDR3;
1702 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1703 mci->edac_cap = EDAC_FLAG_NONE;
1704 mci->mod_name = "sbridge_edac.c";
1705 mci->mod_ver = SBRIDGE_REVISION;
1706 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
1707 mci->dev_name = pci_name(sbridge_dev->pdev[0]);
1708 mci->ctl_page_to_phys = NULL;
1710 /* Set the function pointer to an actual operation function */
1711 mci->edac_check = sbridge_check_error;
1713 /* Store pci devices at mci for faster access */
1714 rc = mci_bind_devs(mci, sbridge_dev);
1715 if (unlikely(rc < 0))
1718 /* Get dimm basic config and the memory layout */
1719 get_dimm_config(mci);
1720 get_memory_layout(mci);
1722 /* record ptr to the generic device */
1723 mci->dev = &sbridge_dev->pdev[0]->dev;
1725 /* add this new MC control structure to EDAC's list of MCs */
1726 if (unlikely(edac_mc_add_mc(mci))) {
1727 debugf0("MC: " __FILE__
1728 ": %s(): failed edac_mc_add_mc()\n", __func__);
1733 atomic_notifier_chain_register(&x86_mce_decoder_chain,
1738 kfree(mci->ctl_name);
1740 sbridge_dev->mci = NULL;
1745 * sbridge_probe Probe for ONE instance of device to see if it is
1748 * 0 for FOUND a device
1749 * < 0 for error code
1752 static int __devinit sbridge_probe(struct pci_dev *pdev,
1753 const struct pci_device_id *id)
1757 struct sbridge_dev *sbridge_dev;
1759 /* get the pci devices we want to reserve for our use */
1760 mutex_lock(&sbridge_edac_lock);
1763 * All memory controllers are allocated at the first pass.
1765 if (unlikely(probed >= 1)) {
1766 mutex_unlock(&sbridge_edac_lock);
1771 rc = sbridge_get_all_devices(&num_mc);
1772 if (unlikely(rc < 0))
1776 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1777 debugf0("Registering MC#%d (%d of %d)\n", mc, mc + 1, num_mc);
1778 sbridge_dev->mc = mc++;
1779 rc = sbridge_register_mci(sbridge_dev);
1780 if (unlikely(rc < 0))
1784 sbridge_printk(KERN_INFO, "Driver loaded.\n");
1786 mutex_unlock(&sbridge_edac_lock);
1790 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1791 sbridge_unregister_mci(sbridge_dev);
1793 sbridge_put_all_devices();
1795 mutex_unlock(&sbridge_edac_lock);
1800 * sbridge_remove destructor for one instance of device
1803 static void __devexit sbridge_remove(struct pci_dev *pdev)
1805 struct sbridge_dev *sbridge_dev;
1807 debugf0(__FILE__ ": %s()\n", __func__);
1810 * we have a trouble here: pdev value for removal will be wrong, since
1811 * it will point to the X58 register used to detect that the machine
1812 * is a Nehalem or upper design. However, due to the way several PCI
1813 * devices are grouped together to provide MC functionality, we need
1814 * to use a different method for releasing the devices
1817 mutex_lock(&sbridge_edac_lock);
1819 if (unlikely(!probed)) {
1820 mutex_unlock(&sbridge_edac_lock);
1824 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1825 sbridge_unregister_mci(sbridge_dev);
1827 /* Release PCI resources */
1828 sbridge_put_all_devices();
1832 mutex_unlock(&sbridge_edac_lock);
1835 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
1838 * sbridge_driver pci_driver structure for this module
1841 static struct pci_driver sbridge_driver = {
1842 .name = "sbridge_edac",
1843 .probe = sbridge_probe,
1844 .remove = __devexit_p(sbridge_remove),
1845 .id_table = sbridge_pci_tbl,
1849 * sbridge_init Module entry function
1850 * Try to initialize this module for its devices
1852 static int __init sbridge_init(void)
1856 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1858 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1861 pci_rc = pci_register_driver(&sbridge_driver);
1866 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
1873 * sbridge_exit() Module exit function
1874 * Unregister the driver
1876 static void __exit sbridge_exit(void)
1878 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1879 pci_unregister_driver(&sbridge_driver);
1882 module_init(sbridge_init);
1883 module_exit(sbridge_exit);
1885 module_param(edac_op_state, int, 0444);
1886 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1888 MODULE_LICENSE("GPL");
1889 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1890 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1891 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - "