1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab <mchehab@redhat.com>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <linux/math64.h>
24 #include <asm/processor.h>
27 #include "edac_core.h"
30 static LIST_HEAD(sbridge_edac_list);
31 static DEFINE_MUTEX(sbridge_edac_lock);
35 * Alter this version for the module when modifications are made
37 #define SBRIDGE_REVISION " Ver: 1.0.0 "
38 #define EDAC_MOD_STR "sbridge_edac"
43 #define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
46 #define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
52 #define GET_BITFIELD(v, lo, hi) \
53 (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))
56 * sbridge Memory Controller Registers
60 * FIXME: For now, let's order by device function, as it makes
61 * easier for driver's development proccess. This table should be
62 * moved to pci_id.h when submitted upstream
64 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
65 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
66 #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
67 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
68 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
69 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
70 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
71 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
72 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
73 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
74 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
77 * Currently, unused, but will be needed in the future
78 * implementations, as they hold the error counters
80 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
81 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
82 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
83 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
85 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
86 static const u32 dram_rule[] = {
87 0x80, 0x88, 0x90, 0x98, 0xa0,
88 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
90 #define MAX_SAD ARRAY_SIZE(dram_rule)
92 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
93 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
94 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
95 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
97 static char *get_dram_attr(u32 reg)
99 switch(DRAM_ATTR(reg)) {
111 static const u32 interleave_list[] = {
112 0x84, 0x8c, 0x94, 0x9c, 0xa4,
113 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
115 #define MAX_INTERLEAVE ARRAY_SIZE(interleave_list)
117 #define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2)
118 #define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5)
119 #define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10)
120 #define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13)
121 #define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18)
122 #define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21)
123 #define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26)
124 #define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29)
126 static inline int sad_pkg(u32 reg, int interleave)
128 switch (interleave) {
130 return SAD_PKG0(reg);
132 return SAD_PKG1(reg);
134 return SAD_PKG2(reg);
136 return SAD_PKG3(reg);
138 return SAD_PKG4(reg);
140 return SAD_PKG5(reg);
142 return SAD_PKG6(reg);
144 return SAD_PKG7(reg);
150 /* Devices 12 Function 7 */
155 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
156 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
158 /* Device 13 Function 6 */
160 #define SAD_TARGET 0xf0
162 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
164 #define SAD_CONTROL 0xf4
166 #define NODE_ID(reg) GET_BITFIELD(reg, 0, 2)
168 /* Device 14 function 0 */
170 static const u32 tad_dram_rule[] = {
171 0x40, 0x44, 0x48, 0x4c,
172 0x50, 0x54, 0x58, 0x5c,
173 0x60, 0x64, 0x68, 0x6c,
175 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
177 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
178 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
179 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
180 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
181 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
182 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
183 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
185 /* Device 15, function 0 */
189 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
190 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
191 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
193 /* Device 15, function 1 */
195 #define RASENABLES 0xac
196 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
198 /* Device 15, functions 2-5 */
200 static const int mtr_regs[] = {
204 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
205 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
206 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
207 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
208 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
210 static const u32 tad_ch_nilv_offset[] = {
211 0x90, 0x94, 0x98, 0x9c,
212 0xa0, 0xa4, 0xa8, 0xac,
213 0xb0, 0xb4, 0xb8, 0xbc,
215 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
216 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
218 static const u32 rir_way_limit[] = {
219 0x108, 0x10c, 0x110, 0x114, 0x118,
221 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
223 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
224 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
225 #define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff)
227 #define MAX_RIR_WAY 8
229 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
230 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
231 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
232 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
233 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
234 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
237 #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
238 #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
240 /* Device 16, functions 2-7 */
243 * FIXME: Implement the error count reads directly
246 static const u32 correrrcnt[] = {
247 0x104, 0x108, 0x10c, 0x110,
250 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
251 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
252 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
253 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
255 static const u32 correrrthrsld[] = {
256 0x11c, 0x120, 0x124, 0x128,
259 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
260 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
263 /* Device 17, function 0 */
265 #define RANK_CFG_A 0x0328
267 #define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)
273 #define NUM_CHANNELS 4
274 #define MAX_DIMMS 3 /* Max DIMMS per channel */
276 struct sbridge_info {
280 struct sbridge_channel {
285 struct pci_id_descr {
292 struct pci_id_table {
293 const struct pci_id_descr *descr;
298 struct list_head list;
300 u8 node_id, source_id;
301 struct pci_dev **pdev;
303 struct mem_ctl_info *mci;
307 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
308 struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0;
309 struct pci_dev *pci_br;
310 struct pci_dev *pci_tad[NUM_CHANNELS];
312 struct sbridge_dev *sbridge_dev;
314 struct sbridge_info info;
315 struct sbridge_channel channel[NUM_CHANNELS];
317 /* Memory type detection */
318 bool is_mirrored, is_lockstep, is_close_pg;
320 /* Fifo double buffers */
321 struct mce mce_entry[MCE_LOG_LEN];
322 struct mce mce_outentry[MCE_LOG_LEN];
324 /* Fifo in/out counters */
325 unsigned mce_in, mce_out;
327 /* Count indicator to show errors not got */
328 unsigned mce_overrun;
330 /* Memory description */
334 #define PCI_DESCR(device, function, device_id) \
336 .func = (function), \
337 .dev_id = (device_id)
339 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
340 /* Processor Home Agent */
341 { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0) },
343 /* Memory controller */
344 { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA) },
345 { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS) },
346 { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0) },
347 { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1) },
348 { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2) },
349 { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3) },
350 { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO) },
352 /* System Address Decoder */
353 { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0) },
354 { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1) },
356 /* Broadcast Registers */
357 { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR) },
360 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
361 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
362 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
363 {0,} /* 0 terminated list. */
367 * pci_device_id table for which devices we are looking for
369 static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = {
370 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
371 {0,} /* 0 terminated list. */
375 /****************************************************************************
376 Anciliary status routines
377 ****************************************************************************/
379 static inline int numrank(u32 mtr)
381 int ranks = (1 << RANK_CNT_BITS(mtr));
384 debugf0("Invalid number of ranks: %d (max = 4) raw value = %x (%04x)",
385 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
392 static inline int numrow(u32 mtr)
394 int rows = (RANK_WIDTH_BITS(mtr) + 12);
396 if (rows < 13 || rows > 18) {
397 debugf0("Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)",
398 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
405 static inline int numcol(u32 mtr)
407 int cols = (COL_WIDTH_BITS(mtr) + 10);
410 debugf0("Invalid number of cols: %d (max = 4) raw value = %x (%04x)",
411 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
418 static struct sbridge_dev *get_sbridge_dev(u8 bus)
420 struct sbridge_dev *sbridge_dev;
422 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
423 if (sbridge_dev->bus == bus)
430 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
431 const struct pci_id_table *table)
433 struct sbridge_dev *sbridge_dev;
435 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
439 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
441 if (!sbridge_dev->pdev) {
446 sbridge_dev->bus = bus;
447 sbridge_dev->n_devs = table->n_devs;
448 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
453 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
455 list_del(&sbridge_dev->list);
456 kfree(sbridge_dev->pdev);
460 /****************************************************************************
461 Memory check routines
462 ****************************************************************************/
463 static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot,
466 struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus);
472 for (i = 0; i < sbridge_dev->n_devs; i++) {
473 if (!sbridge_dev->pdev[i])
476 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot &&
477 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) {
478 debugf1("Associated %02x.%02x.%d with %p\n",
479 bus, slot, func, sbridge_dev->pdev[i]);
480 return sbridge_dev->pdev[i];
488 * check_if_ecc_is_active() - Checks if ECC is active
491 static int check_if_ecc_is_active(const u8 bus)
493 struct pci_dev *pdev = NULL;
496 pdev = get_pdev_slot_func(bus, 15, 0);
498 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
504 pci_read_config_dword(pdev, MCMTR, &mcmtr);
505 if (!IS_ECC_ENABLED(mcmtr)) {
506 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
512 static int get_dimm_config(struct mem_ctl_info *mci)
514 struct sbridge_pvt *pvt = mci->pvt_info;
515 struct dimm_info *dimm;
516 int i, j, banks, ranks, rows, cols, size, npages;
521 pci_read_config_dword(pvt->pci_br, SAD_TARGET, ®);
522 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
524 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, ®);
525 pvt->sbridge_dev->node_id = NODE_ID(reg);
526 debugf0("mc#%d: Node ID: %d, source ID: %d\n",
527 pvt->sbridge_dev->mc,
528 pvt->sbridge_dev->node_id,
529 pvt->sbridge_dev->source_id);
531 pci_read_config_dword(pvt->pci_ras, RASENABLES, ®);
532 if (IS_MIRROR_ENABLED(reg)) {
533 debugf0("Memory mirror is enabled\n");
534 pvt->is_mirrored = true;
536 debugf0("Memory mirror is disabled\n");
537 pvt->is_mirrored = false;
540 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
541 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
542 debugf0("Lockstep is enabled\n");
543 mode = EDAC_S8ECD8ED;
544 pvt->is_lockstep = true;
546 debugf0("Lockstep is disabled\n");
547 mode = EDAC_S4ECD4ED;
548 pvt->is_lockstep = false;
550 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
551 debugf0("address map is on closed page mode\n");
552 pvt->is_close_pg = true;
554 debugf0("address map is on open page mode\n");
555 pvt->is_close_pg = false;
558 pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, ®);
559 if (IS_RDIMM_ENABLED(reg)) {
560 /* FIXME: Can also be LRDIMM */
561 debugf0("Memory is registered\n");
564 debugf0("Memory is unregistered\n");
568 /* On all supported DDR3 DIMM types, there are 8 banks available */
571 for (i = 0; i < NUM_CHANNELS; i++) {
574 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
575 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
577 pci_read_config_dword(pvt->pci_tad[i],
579 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr);
580 if (IS_DIMM_PRESENT(mtr)) {
581 pvt->channel[i].dimms++;
583 ranks = numrank(mtr);
587 /* DDR3 has 8 I/O banks */
588 size = (rows * cols * banks * ranks) >> (20 - 3);
589 npages = MiB_TO_PAGES(size);
591 debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
592 pvt->sbridge_dev->mc, i, j,
594 banks, ranks, rows, cols);
596 dimm->nr_pages = npages;
598 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
600 dimm->edac_mode = mode;
601 snprintf(dimm->label, sizeof(dimm->label),
602 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
603 pvt->sbridge_dev->source_id, i, j);
611 static void get_memory_layout(const struct mem_ctl_info *mci)
613 struct sbridge_pvt *pvt = mci->pvt_info;
614 int i, j, k, n_sads, n_tads, sad_interl;
622 * Step 1) Get TOLM/TOHM ranges
625 /* Address range is 32:28 */
626 pci_read_config_dword(pvt->pci_sad1, TOLM,
628 pvt->tolm = GET_TOLM(reg);
629 tmp_mb = (1 + pvt->tolm) >> 20;
631 mb = div_u64_rem(tmp_mb, 1000, &kb);
632 debugf0("TOLM: %u.%03u GB (0x%016Lx)\n",
633 mb, kb, (u64)pvt->tolm);
635 /* Address range is already 45:25 */
636 pci_read_config_dword(pvt->pci_sad1, TOHM,
638 pvt->tohm = GET_TOHM(reg);
639 tmp_mb = (1 + pvt->tohm) >> 20;
641 mb = div_u64_rem(tmp_mb, 1000, &kb);
642 debugf0("TOHM: %u.%03u GB (0x%016Lx)",
643 mb, kb, (u64)pvt->tohm);
646 * Step 2) Get SAD range and SAD Interleave list
647 * TAD registers contain the interleave wayness. However, it
648 * seems simpler to just discover it indirectly, with the
652 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
653 /* SAD_LIMIT Address range is 45:26 */
654 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
656 limit = SAD_LIMIT(reg);
658 if (!DRAM_RULE_ENABLE(reg))
664 tmp_mb = (limit + 1) >> 20;
665 mb = div_u64_rem(tmp_mb, 1000, &kb);
666 debugf0("SAD#%d %s up to %u.%03u GB (0x%016Lx) %s reg=0x%08x\n",
670 ((u64)tmp_mb) << 20L,
671 INTERLEAVE_MODE(reg) ? "Interleave: 8:6" : "Interleave: [8:6]XOR[18:16]",
675 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
677 sad_interl = sad_pkg(reg, 0);
678 for (j = 0; j < 8; j++) {
679 if (j > 0 && sad_interl == sad_pkg(reg, j))
682 debugf0("SAD#%d, interleave #%d: %d\n",
683 n_sads, j, sad_pkg(reg, j));
688 * Step 3) Get TAD range
691 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
692 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
694 limit = TAD_LIMIT(reg);
697 tmp_mb = (limit + 1) >> 20;
699 mb = div_u64_rem(tmp_mb, 1000, &kb);
700 debugf0("TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
702 ((u64)tmp_mb) << 20L,
714 * Step 4) Get TAD offsets, per each channel
716 for (i = 0; i < NUM_CHANNELS; i++) {
717 if (!pvt->channel[i].dimms)
719 for (j = 0; j < n_tads; j++) {
720 pci_read_config_dword(pvt->pci_tad[i],
721 tad_ch_nilv_offset[j],
723 tmp_mb = TAD_OFFSET(reg) >> 20;
724 mb = div_u64_rem(tmp_mb, 1000, &kb);
725 debugf0("TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
728 ((u64)tmp_mb) << 20L,
734 * Step 6) Get RIR Wayness/Limit, per each channel
736 for (i = 0; i < NUM_CHANNELS; i++) {
737 if (!pvt->channel[i].dimms)
739 for (j = 0; j < MAX_RIR_RANGES; j++) {
740 pci_read_config_dword(pvt->pci_tad[i],
744 if (!IS_RIR_VALID(reg))
747 tmp_mb = RIR_LIMIT(reg) >> 20;
748 rir_way = 1 << RIR_WAY(reg);
749 mb = div_u64_rem(tmp_mb, 1000, &kb);
750 debugf0("CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
753 ((u64)tmp_mb) << 20L,
757 for (k = 0; k < rir_way; k++) {
758 pci_read_config_dword(pvt->pci_tad[i],
761 tmp_mb = RIR_OFFSET(reg) << 6;
763 mb = div_u64_rem(tmp_mb, 1000, &kb);
764 debugf0("CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
767 ((u64)tmp_mb) << 20L,
768 (u32)RIR_RNK_TGT(reg),
775 struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
777 struct sbridge_dev *sbridge_dev;
779 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
780 if (sbridge_dev->node_id == node_id)
781 return sbridge_dev->mci;
786 static int get_memory_error_data(struct mem_ctl_info *mci,
791 char **area_type, char *msg)
793 struct mem_ctl_info *new_mci;
794 struct sbridge_pvt *pvt = mci->pvt_info;
795 int n_rir, n_sads, n_tads, sad_way, sck_xch;
796 int sad_interl, idx, base_ch;
798 unsigned sad_interleave[MAX_INTERLEAVE];
804 u64 ch_addr, offset, limit, prv = 0;
808 * Step 0) Check if the address is at special memory ranges
809 * The check bellow is probably enough to fill all cases where
810 * the error is not inside a memory, except for the legacy
811 * range (e. g. VGA addresses). It is unlikely, however, that the
812 * memory controller would generate an error on that range.
814 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
815 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
818 if (addr >= (u64)pvt->tohm) {
819 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
826 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
827 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
830 if (!DRAM_RULE_ENABLE(reg))
833 limit = SAD_LIMIT(reg);
835 sprintf(msg, "Can't discover the memory socket");
842 if (n_sads == MAX_SAD) {
843 sprintf(msg, "Can't discover the memory socket");
846 *area_type = get_dram_attr(reg);
847 interleave_mode = INTERLEAVE_MODE(reg);
849 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
851 sad_interl = sad_pkg(reg, 0);
852 for (sad_way = 0; sad_way < 8; sad_way++) {
853 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way))
855 sad_interleave[sad_way] = sad_pkg(reg, sad_way);
856 debugf0("SAD interleave #%d: %d\n",
857 sad_way, sad_interleave[sad_way]);
859 debugf0("mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
860 pvt->sbridge_dev->mc,
865 interleave_mode ? "" : "XOR[18:16]");
867 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
869 idx = (addr >> 6) & 7;
883 sprintf(msg, "Can't discover socket interleave");
886 *socket = sad_interleave[idx];
887 debugf0("SAD interleave index: %d (wayness %d) = CPU socket %d\n",
888 idx, sad_way, *socket);
891 * Move to the proper node structure, in order to access the
892 * right PCI registers
894 new_mci = get_mci_for_node_id(*socket);
896 sprintf(msg, "Struct for socket #%u wasn't initialized",
904 * Step 2) Get memory channel
907 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
908 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
910 limit = TAD_LIMIT(reg);
912 sprintf(msg, "Can't discover the memory channel");
919 ch_way = TAD_CH(reg) + 1;
920 sck_way = TAD_SOCK(reg) + 1;
922 * FIXME: Is it right to always use channel 0 for offsets?
924 pci_read_config_dword(pvt->pci_tad[0],
925 tad_ch_nilv_offset[n_tads],
931 idx = addr >> (6 + sck_way);
935 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
939 base_ch = TAD_TGT0(reg);
942 base_ch = TAD_TGT1(reg);
945 base_ch = TAD_TGT2(reg);
948 base_ch = TAD_TGT3(reg);
951 sprintf(msg, "Can't discover the TAD target");
954 *channel_mask = 1 << base_ch;
956 if (pvt->is_mirrored) {
957 *channel_mask |= 1 << ((base_ch + 2) % 4);
961 sck_xch = 1 << sck_way * (ch_way >> 1);
964 sprintf(msg, "Invalid mirror set. Can't decode addr");
968 sck_xch = (1 << sck_way) * ch_way;
970 if (pvt->is_lockstep)
971 *channel_mask |= 1 << ((base_ch + 1) % 4);
973 offset = TAD_OFFSET(tad_offset);
975 debugf0("TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
986 /* Calculate channel address */
987 /* Remove the TAD offset */
990 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
995 /* Store the low bits [0:6] of the addr */
996 ch_addr = addr & 0x7f;
997 /* Remove socket wayness and remove 6 bits */
999 addr = div_u64(addr, sck_xch);
1001 /* Divide by channel way */
1002 addr = addr / ch_way;
1004 /* Recover the last 6 bits */
1005 ch_addr |= addr << 6;
1008 * Step 3) Decode rank
1010 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1011 pci_read_config_dword(pvt->pci_tad[base_ch],
1012 rir_way_limit[n_rir],
1015 if (!IS_RIR_VALID(reg))
1018 limit = RIR_LIMIT(reg);
1019 mb = div_u64_rem(limit >> 20, 1000, &kb);
1020 debugf0("RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1025 if (ch_addr <= limit)
1028 if (n_rir == MAX_RIR_RANGES) {
1029 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1033 rir_way = RIR_WAY(reg);
1034 if (pvt->is_close_pg)
1035 idx = (ch_addr >> 6);
1037 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1038 idx %= 1 << rir_way;
1040 pci_read_config_dword(pvt->pci_tad[base_ch],
1041 rir_offset[n_rir][idx],
1043 *rank = RIR_RNK_TGT(reg);
1045 debugf0("RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1055 /****************************************************************************
1056 Device initialization routines: put/get, init/exit
1057 ****************************************************************************/
1060 * sbridge_put_all_devices 'put' all the devices that we have
1061 * reserved via 'get'
1063 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1068 for (i = 0; i < sbridge_dev->n_devs; i++) {
1069 struct pci_dev *pdev = sbridge_dev->pdev[i];
1072 debugf0("Removing dev %02x:%02x.%d\n",
1074 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1079 static void sbridge_put_all_devices(void)
1081 struct sbridge_dev *sbridge_dev, *tmp;
1083 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1084 sbridge_put_devices(sbridge_dev);
1085 free_sbridge_dev(sbridge_dev);
1090 * sbridge_get_all_devices Find and perform 'get' operation on the MCH's
1091 * device/functions we want to reference for this driver
1093 * Need to 'get' device 16 func 1 and func 2
1095 static int sbridge_get_onedevice(struct pci_dev **prev,
1097 const struct pci_id_table *table,
1098 const unsigned devno)
1100 struct sbridge_dev *sbridge_dev;
1101 const struct pci_id_descr *dev_descr = &table->descr[devno];
1103 struct pci_dev *pdev = NULL;
1106 sbridge_printk(KERN_INFO,
1107 "Seeking for: dev %02x.%d PCI ID %04x:%04x\n",
1108 dev_descr->dev, dev_descr->func,
1109 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1111 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1112 dev_descr->dev_id, *prev);
1120 if (dev_descr->optional)
1126 sbridge_printk(KERN_INFO,
1127 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1128 dev_descr->dev, dev_descr->func,
1129 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1131 /* End of list, leave */
1134 bus = pdev->bus->number;
1136 sbridge_dev = get_sbridge_dev(bus);
1138 sbridge_dev = alloc_sbridge_dev(bus, table);
1146 if (sbridge_dev->pdev[devno]) {
1147 sbridge_printk(KERN_ERR,
1148 "Duplicated device for "
1149 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1150 bus, dev_descr->dev, dev_descr->func,
1151 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1156 sbridge_dev->pdev[devno] = pdev;
1159 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1160 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1161 sbridge_printk(KERN_ERR,
1162 "Device PCI ID %04x:%04x "
1163 "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n",
1164 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1165 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1166 bus, dev_descr->dev, dev_descr->func);
1170 /* Be sure that the device is enabled */
1171 if (unlikely(pci_enable_device(pdev) < 0)) {
1172 sbridge_printk(KERN_ERR,
1174 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1175 bus, dev_descr->dev, dev_descr->func,
1176 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1180 debugf0("Detected dev %02x:%d.%d PCI ID %04x:%04x\n",
1181 bus, dev_descr->dev,
1183 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1186 * As stated on drivers/pci/search.c, the reference count for
1187 * @from is always decremented if it is not %NULL. So, as we need
1188 * to get all devices up to null, we need to do a get for the device
1197 static int sbridge_get_all_devices(u8 *num_mc)
1200 struct pci_dev *pdev = NULL;
1201 const struct pci_id_table *table = pci_dev_descr_sbridge_table;
1203 while (table && table->descr) {
1204 for (i = 0; i < table->n_devs; i++) {
1207 rc = sbridge_get_onedevice(&pdev, num_mc,
1214 sbridge_put_all_devices();
1225 static int mci_bind_devs(struct mem_ctl_info *mci,
1226 struct sbridge_dev *sbridge_dev)
1228 struct sbridge_pvt *pvt = mci->pvt_info;
1229 struct pci_dev *pdev;
1232 for (i = 0; i < sbridge_dev->n_devs; i++) {
1233 pdev = sbridge_dev->pdev[i];
1236 slot = PCI_SLOT(pdev->devfn);
1237 func = PCI_FUNC(pdev->devfn);
1242 pvt->pci_sad0 = pdev;
1245 pvt->pci_sad1 = pdev;
1263 pvt->pci_ha0 = pdev;
1275 pvt->pci_ras = pdev;
1281 pvt->pci_tad[func - 2] = pdev;
1290 pvt->pci_ddrio = pdev;
1300 debugf0("Associated PCI %02x.%02d.%d with dev = %p\n",
1302 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1306 /* Check if everything were registered */
1307 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1308 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta ||
1312 for (i = 0; i < NUM_CHANNELS; i++) {
1313 if (!pvt->pci_tad[i])
1319 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1323 sbridge_printk(KERN_ERR, "Device %d, function %d "
1324 "is out of the expected range\n",
1329 /****************************************************************************
1330 Error check routines
1331 ****************************************************************************/
1334 * While Sandy Bridge has error count registers, SMI BIOS read values from
1335 * and resets the counters. So, they are not reliable for the OS to read
1336 * from them. So, we have no option but to just trust on whatever MCE is
1337 * telling us about the errors.
1339 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1340 const struct mce *m)
1342 struct mem_ctl_info *new_mci;
1343 struct sbridge_pvt *pvt = mci->pvt_info;
1344 enum hw_event_mc_err_type tp_event;
1345 char *type, *optype, msg[256];
1346 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1347 bool overflow = GET_BITFIELD(m->status, 62, 62);
1348 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1349 bool recoverable = GET_BITFIELD(m->status, 56, 56);
1350 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1351 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1352 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1353 u32 channel = GET_BITFIELD(m->status, 0, 3);
1354 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1355 long channel_mask, first_channel;
1358 char *area_type = NULL;
1360 if (uncorrected_error) {
1363 tp_event = HW_EVENT_ERR_FATAL;
1366 tp_event = HW_EVENT_ERR_UNCORRECTED;
1370 tp_event = HW_EVENT_ERR_CORRECTED;
1374 * According with Table 15-9 of the Intel Archictecture spec vol 3A,
1375 * memory errors should fit in this mask:
1376 * 000f 0000 1mmm cccc (binary)
1378 * f = Correction Report Filtering Bit. If 1, subsequent errors
1382 * If the mask doesn't match, report an error to the parsing logic
1384 if (! ((errcode & 0xef80) == 0x80)) {
1385 optype = "Can't parse: it is not a mem";
1387 switch (optypenum) {
1389 optype = "generic undef request error";
1392 optype = "memory read error";
1395 optype = "memory write error";
1398 optype = "addr/cmd error";
1401 optype = "memory scrubbing error";
1404 optype = "reserved";
1409 rc = get_memory_error_data(mci, m->addr, &socket,
1410 &channel_mask, &rank, &area_type, msg);
1413 new_mci = get_mci_for_node_id(socket);
1415 strcpy(msg, "Error: socket got corrupted!");
1419 pvt = mci->pvt_info;
1421 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1432 * FIXME: On some memory configurations (mirror, lockstep), the
1433 * Memory Controller can't point the error to a single DIMM. The
1434 * EDAC core should be handling the channel mask, in order to point
1435 * to the group of dimm's where the error may be happening.
1437 snprintf(msg, sizeof(msg),
1438 "count:%d%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d",
1440 overflow ? " OVERFLOW" : "",
1441 (uncorrected_error && recoverable) ? " recoverable" : "",
1450 /* FIXME: need support for channel mask */
1452 /* Call the helper to output message */
1453 edac_mc_handle_error(tp_event, mci,
1454 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
1459 edac_mc_handle_error(tp_event, mci, 0, 0, 0,
1466 * sbridge_check_error Retrieve and process errors reported by the
1467 * hardware. Called by the Core module.
1469 static void sbridge_check_error(struct mem_ctl_info *mci)
1471 struct sbridge_pvt *pvt = mci->pvt_info;
1477 * MCE first step: Copy all mce errors into a temporary buffer
1478 * We use a double buffering here, to reduce the risk of
1482 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1487 m = pvt->mce_outentry;
1488 if (pvt->mce_in + count > MCE_LOG_LEN) {
1489 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1491 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1497 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1499 pvt->mce_in += count;
1502 if (pvt->mce_overrun) {
1503 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
1506 pvt->mce_overrun = 0;
1510 * MCE second step: parse errors and display
1512 for (i = 0; i < count; i++)
1513 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
1517 * sbridge_mce_check_error Replicates mcelog routine to get errors
1518 * This routine simply queues mcelog errors, and
1519 * return. The error itself should be handled later
1520 * by sbridge_check_error.
1521 * WARNING: As this routine should be called at NMI time, extra care should
1522 * be taken to avoid deadlocks, and to be as fast as possible.
1524 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
1527 struct mce *mce = (struct mce *)data;
1528 struct mem_ctl_info *mci;
1529 struct sbridge_pvt *pvt;
1531 mci = get_mci_for_node_id(mce->socketid);
1534 pvt = mci->pvt_info;
1537 * Just let mcelog handle it if the error is
1538 * outside the memory controller. A memory error
1539 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
1540 * bit 12 has an special meaning.
1542 if ((mce->status & 0xefff) >> 7 != 1)
1545 printk("sbridge: HANDLING MCE MEMORY ERROR\n");
1547 printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
1548 mce->extcpu, mce->mcgstatus, mce->bank, mce->status);
1549 printk("TSC %llx ", mce->tsc);
1550 printk("ADDR %llx ", mce->addr);
1551 printk("MISC %llx ", mce->misc);
1553 printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
1554 mce->cpuvendor, mce->cpuid, mce->time,
1555 mce->socketid, mce->apicid);
1557 /* Only handle if it is the right mc controller */
1558 if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc)
1562 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1568 /* Copy memory error at the ringbuffer */
1569 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1571 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1573 /* Handle fatal errors immediately */
1574 if (mce->mcgstatus & 1)
1575 sbridge_check_error(mci);
1577 /* Advice mcelog that the error were handled */
1581 static struct notifier_block sbridge_mce_dec = {
1582 .notifier_call = sbridge_mce_check_error,
1585 /****************************************************************************
1586 EDAC register/unregister logic
1587 ****************************************************************************/
1589 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1591 struct mem_ctl_info *mci = sbridge_dev->mci;
1592 struct sbridge_pvt *pvt;
1594 if (unlikely(!mci || !mci->pvt_info)) {
1595 debugf0("MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
1597 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
1601 pvt = mci->pvt_info;
1603 debugf0("MC: mci = %p, dev = %p\n",
1604 mci, &sbridge_dev->pdev[0]->dev);
1606 mce_unregister_decode_chain(&sbridge_mce_dec);
1608 /* Remove MC sysfs nodes */
1609 edac_mc_del_mc(mci->pdev);
1611 debugf1("%s: free mci struct\n", mci->ctl_name);
1612 kfree(mci->ctl_name);
1614 sbridge_dev->mci = NULL;
1617 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
1619 struct mem_ctl_info *mci;
1620 struct edac_mc_layer layers[2];
1621 struct sbridge_pvt *pvt;
1624 /* Check the number of active and not disabled channels */
1625 rc = check_if_ecc_is_active(sbridge_dev->bus);
1626 if (unlikely(rc < 0))
1629 /* allocate a new MC control structure */
1630 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1631 layers[0].size = NUM_CHANNELS;
1632 layers[0].is_virt_csrow = false;
1633 layers[1].type = EDAC_MC_LAYER_SLOT;
1634 layers[1].size = MAX_DIMMS;
1635 layers[1].is_virt_csrow = true;
1636 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
1642 debugf0("MC: mci = %p, dev = %p\n",
1643 mci, &sbridge_dev->pdev[0]->dev);
1645 pvt = mci->pvt_info;
1646 memset(pvt, 0, sizeof(*pvt));
1648 /* Associate sbridge_dev and mci for future usage */
1649 pvt->sbridge_dev = sbridge_dev;
1650 sbridge_dev->mci = mci;
1652 mci->mtype_cap = MEM_FLAG_DDR3;
1653 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1654 mci->edac_cap = EDAC_FLAG_NONE;
1655 mci->mod_name = "sbridge_edac.c";
1656 mci->mod_ver = SBRIDGE_REVISION;
1657 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
1658 mci->dev_name = pci_name(sbridge_dev->pdev[0]);
1659 mci->ctl_page_to_phys = NULL;
1661 /* Set the function pointer to an actual operation function */
1662 mci->edac_check = sbridge_check_error;
1664 /* Store pci devices at mci for faster access */
1665 rc = mci_bind_devs(mci, sbridge_dev);
1666 if (unlikely(rc < 0))
1669 /* Get dimm basic config and the memory layout */
1670 get_dimm_config(mci);
1671 get_memory_layout(mci);
1673 /* record ptr to the generic device */
1674 mci->pdev = &sbridge_dev->pdev[0]->dev;
1676 /* add this new MC control structure to EDAC's list of MCs */
1677 if (unlikely(edac_mc_add_mc(mci))) {
1678 debugf0("MC: failed edac_mc_add_mc()\n");
1683 mce_register_decode_chain(&sbridge_mce_dec);
1687 kfree(mci->ctl_name);
1689 sbridge_dev->mci = NULL;
1694 * sbridge_probe Probe for ONE instance of device to see if it is
1697 * 0 for FOUND a device
1698 * < 0 for error code
1701 static int __devinit sbridge_probe(struct pci_dev *pdev,
1702 const struct pci_device_id *id)
1706 struct sbridge_dev *sbridge_dev;
1708 /* get the pci devices we want to reserve for our use */
1709 mutex_lock(&sbridge_edac_lock);
1712 * All memory controllers are allocated at the first pass.
1714 if (unlikely(probed >= 1)) {
1715 mutex_unlock(&sbridge_edac_lock);
1720 rc = sbridge_get_all_devices(&num_mc);
1721 if (unlikely(rc < 0))
1725 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1726 debugf0("Registering MC#%d (%d of %d)\n", mc, mc + 1, num_mc);
1727 sbridge_dev->mc = mc++;
1728 rc = sbridge_register_mci(sbridge_dev);
1729 if (unlikely(rc < 0))
1733 sbridge_printk(KERN_INFO, "Driver loaded.\n");
1735 mutex_unlock(&sbridge_edac_lock);
1739 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1740 sbridge_unregister_mci(sbridge_dev);
1742 sbridge_put_all_devices();
1744 mutex_unlock(&sbridge_edac_lock);
1749 * sbridge_remove destructor for one instance of device
1752 static void __devexit sbridge_remove(struct pci_dev *pdev)
1754 struct sbridge_dev *sbridge_dev;
1759 * we have a trouble here: pdev value for removal will be wrong, since
1760 * it will point to the X58 register used to detect that the machine
1761 * is a Nehalem or upper design. However, due to the way several PCI
1762 * devices are grouped together to provide MC functionality, we need
1763 * to use a different method for releasing the devices
1766 mutex_lock(&sbridge_edac_lock);
1768 if (unlikely(!probed)) {
1769 mutex_unlock(&sbridge_edac_lock);
1773 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1774 sbridge_unregister_mci(sbridge_dev);
1776 /* Release PCI resources */
1777 sbridge_put_all_devices();
1781 mutex_unlock(&sbridge_edac_lock);
1784 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
1787 * sbridge_driver pci_driver structure for this module
1790 static struct pci_driver sbridge_driver = {
1791 .name = "sbridge_edac",
1792 .probe = sbridge_probe,
1793 .remove = __devexit_p(sbridge_remove),
1794 .id_table = sbridge_pci_tbl,
1798 * sbridge_init Module entry function
1799 * Try to initialize this module for its devices
1801 static int __init sbridge_init(void)
1807 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1810 pci_rc = pci_register_driver(&sbridge_driver);
1815 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
1822 * sbridge_exit() Module exit function
1823 * Unregister the driver
1825 static void __exit sbridge_exit(void)
1828 pci_unregister_driver(&sbridge_driver);
1831 module_init(sbridge_init);
1832 module_exit(sbridge_exit);
1834 module_param(edac_op_state, int, 0444);
1835 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1837 MODULE_LICENSE("GPL");
1838 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1839 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1840 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - "