2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
41 #include <asm/byteorder.h>
43 #include <asm/system.h>
45 #ifdef CONFIG_PPC_PMAC
46 #include <asm/pmac_feature.h>
52 #define DESCRIPTOR_OUTPUT_MORE 0
53 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
54 #define DESCRIPTOR_INPUT_MORE (2 << 12)
55 #define DESCRIPTOR_INPUT_LAST (3 << 12)
56 #define DESCRIPTOR_STATUS (1 << 11)
57 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
58 #define DESCRIPTOR_PING (1 << 7)
59 #define DESCRIPTOR_YY (1 << 6)
60 #define DESCRIPTOR_NO_IRQ (0 << 4)
61 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
62 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
63 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
64 #define DESCRIPTOR_WAIT (3 << 0)
70 __le32 branch_address;
72 __le16 transfer_status;
73 } __attribute__((aligned(16)));
75 #define CONTROL_SET(regs) (regs)
76 #define CONTROL_CLEAR(regs) ((regs) + 4)
77 #define COMMAND_PTR(regs) ((regs) + 12)
78 #define CONTEXT_MATCH(regs) ((regs) + 16)
81 struct descriptor descriptor;
82 struct ar_buffer *next;
88 struct ar_buffer *current_buffer;
89 struct ar_buffer *last_buffer;
92 struct tasklet_struct tasklet;
97 typedef int (*descriptor_callback_t)(struct context *ctx,
99 struct descriptor *last);
102 * A buffer that contains a block of DMA-able coherent memory used for
103 * storing a portion of a DMA descriptor program.
105 struct descriptor_buffer {
106 struct list_head list;
107 dma_addr_t buffer_bus;
110 struct descriptor buffer[0];
114 struct fw_ohci *ohci;
116 int total_allocation;
119 * List of page-sized buffers for storing DMA descriptors.
120 * Head of list contains buffers in use and tail of list contains
123 struct list_head buffer_list;
126 * Pointer to a buffer inside buffer_list that contains the tail
127 * end of the current DMA program.
129 struct descriptor_buffer *buffer_tail;
132 * The descriptor containing the branch address of the first
133 * descriptor that has not yet been filled by the device.
135 struct descriptor *last;
138 * The last descriptor in the DMA program. It contains the branch
139 * address that must be updated upon appending a new descriptor.
141 struct descriptor *prev;
143 descriptor_callback_t callback;
145 struct tasklet_struct tasklet;
148 #define IT_HEADER_SY(v) ((v) << 0)
149 #define IT_HEADER_TCODE(v) ((v) << 4)
150 #define IT_HEADER_CHANNEL(v) ((v) << 8)
151 #define IT_HEADER_TAG(v) ((v) << 14)
152 #define IT_HEADER_SPEED(v) ((v) << 16)
153 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
156 struct fw_iso_context base;
157 struct context context;
160 size_t header_length;
163 #define CONFIG_ROM_SIZE 1024
168 __iomem char *registers;
171 int request_generation; /* for timestamping incoming requests */
175 * Spinlock for accessing fw_ohci data. Never call out of
176 * this driver with this lock held.
180 struct ar_context ar_request_ctx;
181 struct ar_context ar_response_ctx;
182 struct context at_request_ctx;
183 struct context at_response_ctx;
186 struct iso_context *it_context_list;
187 u64 ir_context_channels;
189 struct iso_context *ir_context_list;
192 dma_addr_t config_rom_bus;
193 __be32 *next_config_rom;
194 dma_addr_t next_config_rom_bus;
198 dma_addr_t self_id_bus;
199 struct tasklet_struct bus_reset_tasklet;
201 u32 self_id_buffer[512];
204 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
206 return container_of(card, struct fw_ohci, card);
209 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
210 #define IR_CONTEXT_BUFFER_FILL 0x80000000
211 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
212 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
213 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
214 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
216 #define CONTEXT_RUN 0x8000
217 #define CONTEXT_WAKE 0x1000
218 #define CONTEXT_DEAD 0x0800
219 #define CONTEXT_ACTIVE 0x0400
221 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
222 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
223 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
225 #define OHCI1394_REGISTER_SIZE 0x800
226 #define OHCI_LOOP_COUNT 500
227 #define OHCI1394_PCI_HCI_Control 0x40
228 #define SELF_ID_BUF_SIZE 0x800
229 #define OHCI_TCODE_PHY_PACKET 0x0e
230 #define OHCI_VERSION_1_1 0x010010
232 static char ohci_driver_name[] = KBUILD_MODNAME;
234 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
236 #define QUIRK_CYCLE_TIMER 1
237 #define QUIRK_RESET_PACKET 2
238 #define QUIRK_BE_HEADERS 4
239 #define QUIRK_NO_1394A 8
241 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
242 static const struct {
243 unsigned short vendor, device, flags;
245 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
248 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
249 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
250 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
251 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
252 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
255 /* This overrides anything that was found in ohci_quirks[]. */
256 static int param_quirks;
257 module_param_named(quirks, param_quirks, int, 0644);
258 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
259 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
260 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
261 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
262 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
265 #define OHCI_PARAM_DEBUG_AT_AR 1
266 #define OHCI_PARAM_DEBUG_SELFIDS 2
267 #define OHCI_PARAM_DEBUG_IRQS 4
268 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
270 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
272 static int param_debug;
273 module_param_named(debug, param_debug, int, 0644);
274 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
275 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
276 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
277 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
278 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
279 ", or a combination, or all = -1)");
281 static void log_irqs(u32 evt)
283 if (likely(!(param_debug &
284 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
287 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
288 !(evt & OHCI1394_busReset))
291 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
292 evt & OHCI1394_selfIDComplete ? " selfID" : "",
293 evt & OHCI1394_RQPkt ? " AR_req" : "",
294 evt & OHCI1394_RSPkt ? " AR_resp" : "",
295 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
296 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
297 evt & OHCI1394_isochRx ? " IR" : "",
298 evt & OHCI1394_isochTx ? " IT" : "",
299 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
300 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
301 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
302 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
303 evt & OHCI1394_busReset ? " busReset" : "",
304 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
305 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
306 OHCI1394_respTxComplete | OHCI1394_isochRx |
307 OHCI1394_isochTx | OHCI1394_postedWriteErr |
308 OHCI1394_cycleTooLong | OHCI1394_cycleInconsistent |
309 OHCI1394_regAccessFail | OHCI1394_busReset)
313 static const char *speed[] = {
314 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
316 static const char *power[] = {
317 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
318 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
320 static const char port[] = { '.', '-', 'p', 'c', };
322 static char _p(u32 *s, int shift)
324 return port[*s >> shift & 3];
327 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
329 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
332 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
333 self_id_count, generation, node_id);
335 for (; self_id_count--; ++s)
336 if ((*s & 1 << 23) == 0)
337 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
338 "%s gc=%d %s %s%s%s\n",
339 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
340 speed[*s >> 14 & 3], *s >> 16 & 63,
341 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
342 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
344 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
346 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
347 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
350 static const char *evts[] = {
351 [0x00] = "evt_no_status", [0x01] = "-reserved-",
352 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
353 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
354 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
355 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
356 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
357 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
358 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
359 [0x10] = "-reserved-", [0x11] = "ack_complete",
360 [0x12] = "ack_pending ", [0x13] = "-reserved-",
361 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
362 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
363 [0x18] = "-reserved-", [0x19] = "-reserved-",
364 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
365 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
366 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
367 [0x20] = "pending/cancelled",
369 static const char *tcodes[] = {
370 [0x0] = "QW req", [0x1] = "BW req",
371 [0x2] = "W resp", [0x3] = "-reserved-",
372 [0x4] = "QR req", [0x5] = "BR req",
373 [0x6] = "QR resp", [0x7] = "BR resp",
374 [0x8] = "cycle start", [0x9] = "Lk req",
375 [0xa] = "async stream packet", [0xb] = "Lk resp",
376 [0xc] = "-reserved-", [0xd] = "-reserved-",
377 [0xe] = "link internal", [0xf] = "-reserved-",
379 static const char *phys[] = {
380 [0x0] = "phy config packet", [0x1] = "link-on packet",
381 [0x2] = "self-id packet", [0x3] = "-reserved-",
384 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
386 int tcode = header[0] >> 4 & 0xf;
389 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
392 if (unlikely(evt >= ARRAY_SIZE(evts)))
395 if (evt == OHCI1394_evt_bus_reset) {
396 fw_notify("A%c evt_bus_reset, generation %d\n",
397 dir, (header[2] >> 16) & 0xff);
401 if (header[0] == ~header[1]) {
402 fw_notify("A%c %s, %s, %08x\n",
403 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
408 case 0x0: case 0x6: case 0x8:
409 snprintf(specific, sizeof(specific), " = %08x",
410 be32_to_cpu((__force __be32)header[3]));
412 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
413 snprintf(specific, sizeof(specific), " %x,%x",
414 header[3] >> 16, header[3] & 0xffff);
422 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
424 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
425 fw_notify("A%c spd %x tl %02x, "
428 dir, speed, header[0] >> 10 & 0x3f,
429 header[1] >> 16, header[0] >> 16, evts[evt],
430 tcodes[tcode], header[1] & 0xffff, header[2], specific);
433 fw_notify("A%c spd %x tl %02x, "
436 dir, speed, header[0] >> 10 & 0x3f,
437 header[1] >> 16, header[0] >> 16, evts[evt],
438 tcodes[tcode], specific);
444 #define param_debug 0
445 static inline void log_irqs(u32 evt) {}
446 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
447 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
449 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
451 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
453 writel(data, ohci->registers + offset);
456 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
458 return readl(ohci->registers + offset);
461 static inline void flush_writes(const struct fw_ohci *ohci)
463 /* Do a dummy read to flush writes. */
464 reg_read(ohci, OHCI1394_Version);
467 static int read_phy_reg(struct fw_ohci *ohci, int addr)
472 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
473 for (i = 0; i < 10; i++) {
474 val = reg_read(ohci, OHCI1394_PhyControl);
475 if (val & OHCI1394_PhyControl_ReadDone)
476 return OHCI1394_PhyControl_ReadData(val);
480 fw_error("failed to read phy reg\n");
485 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
489 reg_write(ohci, OHCI1394_PhyControl,
490 OHCI1394_PhyControl_Write(addr, val));
491 for (i = 0; i < 100; i++) {
492 val = reg_read(ohci, OHCI1394_PhyControl);
493 if (!(val & OHCI1394_PhyControl_WritePending))
498 fw_error("failed to write phy reg\n");
503 static int ohci_update_phy_reg(struct fw_card *card, int addr,
504 int clear_bits, int set_bits)
506 struct fw_ohci *ohci = fw_ohci(card);
509 ret = read_phy_reg(ohci, addr);
514 * The interrupt status bits are cleared by writing a one bit.
515 * Avoid clearing them unless explicitly requested in set_bits.
518 clear_bits |= PHY_INT_STATUS_BITS;
520 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
523 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
527 ret = ohci_update_phy_reg(&ohci->card, 7, PHY_PAGE_SELECT, page << 5);
531 return read_phy_reg(ohci, addr);
534 static int ar_context_add_page(struct ar_context *ctx)
536 struct device *dev = ctx->ohci->card.device;
537 struct ar_buffer *ab;
538 dma_addr_t uninitialized_var(ab_bus);
541 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
546 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
547 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
549 DESCRIPTOR_BRANCH_ALWAYS);
550 offset = offsetof(struct ar_buffer, data);
551 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
552 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
553 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
554 ab->descriptor.branch_address = 0;
556 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
557 ctx->last_buffer->next = ab;
558 ctx->last_buffer = ab;
560 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
561 flush_writes(ctx->ohci);
566 static void ar_context_release(struct ar_context *ctx)
568 struct ar_buffer *ab, *ab_next;
572 for (ab = ctx->current_buffer; ab; ab = ab_next) {
574 offset = offsetof(struct ar_buffer, data);
575 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
576 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
581 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
582 #define cond_le32_to_cpu(v) \
583 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
585 #define cond_le32_to_cpu(v) le32_to_cpu(v)
588 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
590 struct fw_ohci *ohci = ctx->ohci;
592 u32 status, length, tcode;
595 p.header[0] = cond_le32_to_cpu(buffer[0]);
596 p.header[1] = cond_le32_to_cpu(buffer[1]);
597 p.header[2] = cond_le32_to_cpu(buffer[2]);
599 tcode = (p.header[0] >> 4) & 0x0f;
601 case TCODE_WRITE_QUADLET_REQUEST:
602 case TCODE_READ_QUADLET_RESPONSE:
603 p.header[3] = (__force __u32) buffer[3];
604 p.header_length = 16;
605 p.payload_length = 0;
608 case TCODE_READ_BLOCK_REQUEST :
609 p.header[3] = cond_le32_to_cpu(buffer[3]);
610 p.header_length = 16;
611 p.payload_length = 0;
614 case TCODE_WRITE_BLOCK_REQUEST:
615 case TCODE_READ_BLOCK_RESPONSE:
616 case TCODE_LOCK_REQUEST:
617 case TCODE_LOCK_RESPONSE:
618 p.header[3] = cond_le32_to_cpu(buffer[3]);
619 p.header_length = 16;
620 p.payload_length = p.header[3] >> 16;
623 case TCODE_WRITE_RESPONSE:
624 case TCODE_READ_QUADLET_REQUEST:
625 case OHCI_TCODE_PHY_PACKET:
626 p.header_length = 12;
627 p.payload_length = 0;
631 /* FIXME: Stop context, discard everything, and restart? */
633 p.payload_length = 0;
636 p.payload = (void *) buffer + p.header_length;
638 /* FIXME: What to do about evt_* errors? */
639 length = (p.header_length + p.payload_length + 3) / 4;
640 status = cond_le32_to_cpu(buffer[length]);
641 evt = (status >> 16) & 0x1f;
644 p.speed = (status >> 21) & 0x7;
645 p.timestamp = status & 0xffff;
646 p.generation = ohci->request_generation;
648 log_ar_at_event('R', p.speed, p.header, evt);
651 * The OHCI bus reset handler synthesizes a phy packet with
652 * the new generation number when a bus reset happens (see
653 * section 8.4.2.3). This helps us determine when a request
654 * was received and make sure we send the response in the same
655 * generation. We only need this for requests; for responses
656 * we use the unique tlabel for finding the matching
659 * Alas some chips sometimes emit bus reset packets with a
660 * wrong generation. We set the correct generation for these
661 * at a slightly incorrect time (in bus_reset_tasklet).
663 if (evt == OHCI1394_evt_bus_reset) {
664 if (!(ohci->quirks & QUIRK_RESET_PACKET))
665 ohci->request_generation = (p.header[2] >> 16) & 0xff;
666 } else if (ctx == &ohci->ar_request_ctx) {
667 fw_core_handle_request(&ohci->card, &p);
669 fw_core_handle_response(&ohci->card, &p);
672 return buffer + length + 1;
675 static void ar_context_tasklet(unsigned long data)
677 struct ar_context *ctx = (struct ar_context *)data;
678 struct fw_ohci *ohci = ctx->ohci;
679 struct ar_buffer *ab;
680 struct descriptor *d;
683 ab = ctx->current_buffer;
686 if (d->res_count == 0) {
687 size_t size, rest, offset;
688 dma_addr_t start_bus;
692 * This descriptor is finished and we may have a
693 * packet split across this and the next buffer. We
694 * reuse the page for reassembling the split packet.
697 offset = offsetof(struct ar_buffer, data);
699 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
703 size = buffer + PAGE_SIZE - ctx->pointer;
704 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
705 memmove(buffer, ctx->pointer, size);
706 memcpy(buffer + size, ab->data, rest);
707 ctx->current_buffer = ab;
708 ctx->pointer = (void *) ab->data + rest;
709 end = buffer + size + rest;
712 buffer = handle_ar_packet(ctx, buffer);
714 dma_free_coherent(ohci->card.device, PAGE_SIZE,
716 ar_context_add_page(ctx);
718 buffer = ctx->pointer;
720 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
723 buffer = handle_ar_packet(ctx, buffer);
727 static int ar_context_init(struct ar_context *ctx,
728 struct fw_ohci *ohci, u32 regs)
734 ctx->last_buffer = &ab;
735 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
737 ar_context_add_page(ctx);
738 ar_context_add_page(ctx);
739 ctx->current_buffer = ab.next;
740 ctx->pointer = ctx->current_buffer->data;
745 static void ar_context_run(struct ar_context *ctx)
747 struct ar_buffer *ab = ctx->current_buffer;
751 offset = offsetof(struct ar_buffer, data);
752 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
754 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
755 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
756 flush_writes(ctx->ohci);
759 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
763 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
764 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
766 /* figure out which descriptor the branch address goes in */
767 if (z == 2 && (b == 3 || key == 2))
773 static void context_tasklet(unsigned long data)
775 struct context *ctx = (struct context *) data;
776 struct descriptor *d, *last;
779 struct descriptor_buffer *desc;
781 desc = list_entry(ctx->buffer_list.next,
782 struct descriptor_buffer, list);
784 while (last->branch_address != 0) {
785 struct descriptor_buffer *old_desc = desc;
786 address = le32_to_cpu(last->branch_address);
790 /* If the branch address points to a buffer outside of the
791 * current buffer, advance to the next buffer. */
792 if (address < desc->buffer_bus ||
793 address >= desc->buffer_bus + desc->used)
794 desc = list_entry(desc->list.next,
795 struct descriptor_buffer, list);
796 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
797 last = find_branch_descriptor(d, z);
799 if (!ctx->callback(ctx, d, last))
802 if (old_desc != desc) {
803 /* If we've advanced to the next buffer, move the
804 * previous buffer to the free list. */
807 spin_lock_irqsave(&ctx->ohci->lock, flags);
808 list_move_tail(&old_desc->list, &ctx->buffer_list);
809 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
816 * Allocate a new buffer and add it to the list of free buffers for this
817 * context. Must be called with ohci->lock held.
819 static int context_add_buffer(struct context *ctx)
821 struct descriptor_buffer *desc;
822 dma_addr_t uninitialized_var(bus_addr);
826 * 16MB of descriptors should be far more than enough for any DMA
827 * program. This will catch run-away userspace or DoS attacks.
829 if (ctx->total_allocation >= 16*1024*1024)
832 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
833 &bus_addr, GFP_ATOMIC);
837 offset = (void *)&desc->buffer - (void *)desc;
838 desc->buffer_size = PAGE_SIZE - offset;
839 desc->buffer_bus = bus_addr + offset;
842 list_add_tail(&desc->list, &ctx->buffer_list);
843 ctx->total_allocation += PAGE_SIZE;
848 static int context_init(struct context *ctx, struct fw_ohci *ohci,
849 u32 regs, descriptor_callback_t callback)
853 ctx->total_allocation = 0;
855 INIT_LIST_HEAD(&ctx->buffer_list);
856 if (context_add_buffer(ctx) < 0)
859 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
860 struct descriptor_buffer, list);
862 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
863 ctx->callback = callback;
866 * We put a dummy descriptor in the buffer that has a NULL
867 * branch address and looks like it's been sent. That way we
868 * have a descriptor to append DMA programs to.
870 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
871 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
872 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
873 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
874 ctx->last = ctx->buffer_tail->buffer;
875 ctx->prev = ctx->buffer_tail->buffer;
880 static void context_release(struct context *ctx)
882 struct fw_card *card = &ctx->ohci->card;
883 struct descriptor_buffer *desc, *tmp;
885 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
886 dma_free_coherent(card->device, PAGE_SIZE, desc,
888 ((void *)&desc->buffer - (void *)desc));
891 /* Must be called with ohci->lock held */
892 static struct descriptor *context_get_descriptors(struct context *ctx,
893 int z, dma_addr_t *d_bus)
895 struct descriptor *d = NULL;
896 struct descriptor_buffer *desc = ctx->buffer_tail;
898 if (z * sizeof(*d) > desc->buffer_size)
901 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
902 /* No room for the descriptor in this buffer, so advance to the
905 if (desc->list.next == &ctx->buffer_list) {
906 /* If there is no free buffer next in the list,
908 if (context_add_buffer(ctx) < 0)
911 desc = list_entry(desc->list.next,
912 struct descriptor_buffer, list);
913 ctx->buffer_tail = desc;
916 d = desc->buffer + desc->used / sizeof(*d);
917 memset(d, 0, z * sizeof(*d));
918 *d_bus = desc->buffer_bus + desc->used;
923 static void context_run(struct context *ctx, u32 extra)
925 struct fw_ohci *ohci = ctx->ohci;
927 reg_write(ohci, COMMAND_PTR(ctx->regs),
928 le32_to_cpu(ctx->last->branch_address));
929 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
930 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
934 static void context_append(struct context *ctx,
935 struct descriptor *d, int z, int extra)
938 struct descriptor_buffer *desc = ctx->buffer_tail;
940 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
942 desc->used += (z + extra) * sizeof(*d);
943 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
944 ctx->prev = find_branch_descriptor(d, z);
946 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
947 flush_writes(ctx->ohci);
950 static void context_stop(struct context *ctx)
955 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
956 flush_writes(ctx->ohci);
958 for (i = 0; i < 10; i++) {
959 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
960 if ((reg & CONTEXT_ACTIVE) == 0)
965 fw_error("Error: DMA context still active (0x%08x)\n", reg);
969 struct fw_packet *packet;
973 * This function apppends a packet to the DMA queue for transmission.
974 * Must always be called with the ochi->lock held to ensure proper
975 * generation handling and locking around packet queue manipulation.
977 static int at_context_queue_packet(struct context *ctx,
978 struct fw_packet *packet)
980 struct fw_ohci *ohci = ctx->ohci;
981 dma_addr_t d_bus, uninitialized_var(payload_bus);
982 struct driver_data *driver_data;
983 struct descriptor *d, *last;
988 d = context_get_descriptors(ctx, 4, &d_bus);
990 packet->ack = RCODE_SEND_ERROR;
994 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
995 d[0].res_count = cpu_to_le16(packet->timestamp);
998 * The DMA format for asyncronous link packets is different
999 * from the IEEE1394 layout, so shift the fields around
1000 * accordingly. If header_length is 8, it's a PHY packet, to
1001 * which we need to prepend an extra quadlet.
1004 header = (__le32 *) &d[1];
1005 switch (packet->header_length) {
1008 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1009 (packet->speed << 16));
1010 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1011 (packet->header[0] & 0xffff0000));
1012 header[2] = cpu_to_le32(packet->header[2]);
1014 tcode = (packet->header[0] >> 4) & 0x0f;
1015 if (TCODE_IS_BLOCK_PACKET(tcode))
1016 header[3] = cpu_to_le32(packet->header[3]);
1018 header[3] = (__force __le32) packet->header[3];
1020 d[0].req_count = cpu_to_le16(packet->header_length);
1024 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1025 (packet->speed << 16));
1026 header[1] = cpu_to_le32(packet->header[0]);
1027 header[2] = cpu_to_le32(packet->header[1]);
1028 d[0].req_count = cpu_to_le16(12);
1032 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1033 (packet->speed << 16));
1034 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1035 d[0].req_count = cpu_to_le16(8);
1040 packet->ack = RCODE_SEND_ERROR;
1044 driver_data = (struct driver_data *) &d[3];
1045 driver_data->packet = packet;
1046 packet->driver_data = driver_data;
1048 if (packet->payload_length > 0) {
1050 dma_map_single(ohci->card.device, packet->payload,
1051 packet->payload_length, DMA_TO_DEVICE);
1052 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1053 packet->ack = RCODE_SEND_ERROR;
1056 packet->payload_bus = payload_bus;
1057 packet->payload_mapped = true;
1059 d[2].req_count = cpu_to_le16(packet->payload_length);
1060 d[2].data_address = cpu_to_le32(payload_bus);
1068 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1069 DESCRIPTOR_IRQ_ALWAYS |
1070 DESCRIPTOR_BRANCH_ALWAYS);
1073 * If the controller and packet generations don't match, we need to
1074 * bail out and try again. If IntEvent.busReset is set, the AT context
1075 * is halted, so appending to the context and trying to run it is
1076 * futile. Most controllers do the right thing and just flush the AT
1077 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1078 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1079 * up stalling out. So we just bail out in software and try again
1080 * later, and everyone is happy.
1081 * FIXME: Document how the locking works.
1083 if (ohci->generation != packet->generation ||
1084 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1085 if (packet->payload_mapped)
1086 dma_unmap_single(ohci->card.device, payload_bus,
1087 packet->payload_length, DMA_TO_DEVICE);
1088 packet->ack = RCODE_GENERATION;
1092 context_append(ctx, d, z, 4 - z);
1094 /* If the context isn't already running, start it up. */
1095 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1096 if ((reg & CONTEXT_RUN) == 0)
1097 context_run(ctx, 0);
1102 static int handle_at_packet(struct context *context,
1103 struct descriptor *d,
1104 struct descriptor *last)
1106 struct driver_data *driver_data;
1107 struct fw_packet *packet;
1108 struct fw_ohci *ohci = context->ohci;
1111 if (last->transfer_status == 0)
1112 /* This descriptor isn't done yet, stop iteration. */
1115 driver_data = (struct driver_data *) &d[3];
1116 packet = driver_data->packet;
1118 /* This packet was cancelled, just continue. */
1121 if (packet->payload_mapped)
1122 dma_unmap_single(ohci->card.device, packet->payload_bus,
1123 packet->payload_length, DMA_TO_DEVICE);
1125 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1126 packet->timestamp = le16_to_cpu(last->res_count);
1128 log_ar_at_event('T', packet->speed, packet->header, evt);
1131 case OHCI1394_evt_timeout:
1132 /* Async response transmit timed out. */
1133 packet->ack = RCODE_CANCELLED;
1136 case OHCI1394_evt_flushed:
1138 * The packet was flushed should give same error as
1139 * when we try to use a stale generation count.
1141 packet->ack = RCODE_GENERATION;
1144 case OHCI1394_evt_missing_ack:
1146 * Using a valid (current) generation count, but the
1147 * node is not on the bus or not sending acks.
1149 packet->ack = RCODE_NO_ACK;
1152 case ACK_COMPLETE + 0x10:
1153 case ACK_PENDING + 0x10:
1154 case ACK_BUSY_X + 0x10:
1155 case ACK_BUSY_A + 0x10:
1156 case ACK_BUSY_B + 0x10:
1157 case ACK_DATA_ERROR + 0x10:
1158 case ACK_TYPE_ERROR + 0x10:
1159 packet->ack = evt - 0x10;
1163 packet->ack = RCODE_SEND_ERROR;
1167 packet->callback(packet, &ohci->card, packet->ack);
1172 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1173 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1174 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1175 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1176 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1178 static void handle_local_rom(struct fw_ohci *ohci,
1179 struct fw_packet *packet, u32 csr)
1181 struct fw_packet response;
1182 int tcode, length, i;
1184 tcode = HEADER_GET_TCODE(packet->header[0]);
1185 if (TCODE_IS_BLOCK_PACKET(tcode))
1186 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1190 i = csr - CSR_CONFIG_ROM;
1191 if (i + length > CONFIG_ROM_SIZE) {
1192 fw_fill_response(&response, packet->header,
1193 RCODE_ADDRESS_ERROR, NULL, 0);
1194 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1195 fw_fill_response(&response, packet->header,
1196 RCODE_TYPE_ERROR, NULL, 0);
1198 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1199 (void *) ohci->config_rom + i, length);
1202 fw_core_handle_response(&ohci->card, &response);
1205 static void handle_local_lock(struct fw_ohci *ohci,
1206 struct fw_packet *packet, u32 csr)
1208 struct fw_packet response;
1209 int tcode, length, ext_tcode, sel;
1210 __be32 *payload, lock_old;
1211 u32 lock_arg, lock_data;
1213 tcode = HEADER_GET_TCODE(packet->header[0]);
1214 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1215 payload = packet->payload;
1216 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1218 if (tcode == TCODE_LOCK_REQUEST &&
1219 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1220 lock_arg = be32_to_cpu(payload[0]);
1221 lock_data = be32_to_cpu(payload[1]);
1222 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1226 fw_fill_response(&response, packet->header,
1227 RCODE_TYPE_ERROR, NULL, 0);
1231 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1232 reg_write(ohci, OHCI1394_CSRData, lock_data);
1233 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1234 reg_write(ohci, OHCI1394_CSRControl, sel);
1236 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1237 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1239 fw_notify("swap not done yet\n");
1241 fw_fill_response(&response, packet->header,
1242 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1244 fw_core_handle_response(&ohci->card, &response);
1247 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1252 if (ctx == &ctx->ohci->at_request_ctx) {
1253 packet->ack = ACK_PENDING;
1254 packet->callback(packet, &ctx->ohci->card, packet->ack);
1258 ((unsigned long long)
1259 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1261 csr = offset - CSR_REGISTER_BASE;
1263 /* Handle config rom reads. */
1264 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1265 handle_local_rom(ctx->ohci, packet, csr);
1267 case CSR_BUS_MANAGER_ID:
1268 case CSR_BANDWIDTH_AVAILABLE:
1269 case CSR_CHANNELS_AVAILABLE_HI:
1270 case CSR_CHANNELS_AVAILABLE_LO:
1271 handle_local_lock(ctx->ohci, packet, csr);
1274 if (ctx == &ctx->ohci->at_request_ctx)
1275 fw_core_handle_request(&ctx->ohci->card, packet);
1277 fw_core_handle_response(&ctx->ohci->card, packet);
1281 if (ctx == &ctx->ohci->at_response_ctx) {
1282 packet->ack = ACK_COMPLETE;
1283 packet->callback(packet, &ctx->ohci->card, packet->ack);
1287 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1289 unsigned long flags;
1292 spin_lock_irqsave(&ctx->ohci->lock, flags);
1294 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1295 ctx->ohci->generation == packet->generation) {
1296 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1297 handle_local_request(ctx, packet);
1301 ret = at_context_queue_packet(ctx, packet);
1302 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1305 packet->callback(packet, &ctx->ohci->card, packet->ack);
1309 static void bus_reset_tasklet(unsigned long data)
1311 struct fw_ohci *ohci = (struct fw_ohci *)data;
1312 int self_id_count, i, j, reg;
1313 int generation, new_generation;
1314 unsigned long flags;
1315 void *free_rom = NULL;
1316 dma_addr_t free_rom_bus = 0;
1318 reg = reg_read(ohci, OHCI1394_NodeID);
1319 if (!(reg & OHCI1394_NodeID_idValid)) {
1320 fw_notify("node ID not valid, new bus reset in progress\n");
1323 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1324 fw_notify("malconfigured bus\n");
1327 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1328 OHCI1394_NodeID_nodeNumber);
1330 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1331 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1332 fw_notify("inconsistent self IDs\n");
1336 * The count in the SelfIDCount register is the number of
1337 * bytes in the self ID receive buffer. Since we also receive
1338 * the inverted quadlets and a header quadlet, we shift one
1339 * bit extra to get the actual number of self IDs.
1341 self_id_count = (reg >> 3) & 0xff;
1342 if (self_id_count == 0 || self_id_count > 252) {
1343 fw_notify("inconsistent self IDs\n");
1346 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1349 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1350 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1351 fw_notify("inconsistent self IDs\n");
1354 ohci->self_id_buffer[j] =
1355 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1360 * Check the consistency of the self IDs we just read. The
1361 * problem we face is that a new bus reset can start while we
1362 * read out the self IDs from the DMA buffer. If this happens,
1363 * the DMA buffer will be overwritten with new self IDs and we
1364 * will read out inconsistent data. The OHCI specification
1365 * (section 11.2) recommends a technique similar to
1366 * linux/seqlock.h, where we remember the generation of the
1367 * self IDs in the buffer before reading them out and compare
1368 * it to the current generation after reading them out. If
1369 * the two generations match we know we have a consistent set
1373 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1374 if (new_generation != generation) {
1375 fw_notify("recursive bus reset detected, "
1376 "discarding self ids\n");
1380 /* FIXME: Document how the locking works. */
1381 spin_lock_irqsave(&ohci->lock, flags);
1383 ohci->generation = generation;
1384 context_stop(&ohci->at_request_ctx);
1385 context_stop(&ohci->at_response_ctx);
1386 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1388 if (ohci->quirks & QUIRK_RESET_PACKET)
1389 ohci->request_generation = generation;
1392 * This next bit is unrelated to the AT context stuff but we
1393 * have to do it under the spinlock also. If a new config rom
1394 * was set up before this reset, the old one is now no longer
1395 * in use and we can free it. Update the config rom pointers
1396 * to point to the current config rom and clear the
1397 * next_config_rom pointer so a new udpate can take place.
1400 if (ohci->next_config_rom != NULL) {
1401 if (ohci->next_config_rom != ohci->config_rom) {
1402 free_rom = ohci->config_rom;
1403 free_rom_bus = ohci->config_rom_bus;
1405 ohci->config_rom = ohci->next_config_rom;
1406 ohci->config_rom_bus = ohci->next_config_rom_bus;
1407 ohci->next_config_rom = NULL;
1410 * Restore config_rom image and manually update
1411 * config_rom registers. Writing the header quadlet
1412 * will indicate that the config rom is ready, so we
1415 reg_write(ohci, OHCI1394_BusOptions,
1416 be32_to_cpu(ohci->config_rom[2]));
1417 ohci->config_rom[0] = ohci->next_header;
1418 reg_write(ohci, OHCI1394_ConfigROMhdr,
1419 be32_to_cpu(ohci->next_header));
1422 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1423 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1424 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1427 spin_unlock_irqrestore(&ohci->lock, flags);
1430 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1431 free_rom, free_rom_bus);
1433 log_selfids(ohci->node_id, generation,
1434 self_id_count, ohci->self_id_buffer);
1436 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1437 self_id_count, ohci->self_id_buffer);
1440 static irqreturn_t irq_handler(int irq, void *data)
1442 struct fw_ohci *ohci = data;
1443 u32 event, iso_event;
1446 event = reg_read(ohci, OHCI1394_IntEventClear);
1448 if (!event || !~event)
1451 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1452 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1455 if (event & OHCI1394_selfIDComplete)
1456 tasklet_schedule(&ohci->bus_reset_tasklet);
1458 if (event & OHCI1394_RQPkt)
1459 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1461 if (event & OHCI1394_RSPkt)
1462 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1464 if (event & OHCI1394_reqTxComplete)
1465 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1467 if (event & OHCI1394_respTxComplete)
1468 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1470 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1471 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1474 i = ffs(iso_event) - 1;
1475 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1476 iso_event &= ~(1 << i);
1479 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1480 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1483 i = ffs(iso_event) - 1;
1484 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1485 iso_event &= ~(1 << i);
1488 if (unlikely(event & OHCI1394_regAccessFail))
1489 fw_error("Register access failure - "
1490 "please notify linux1394-devel@lists.sf.net\n");
1492 if (unlikely(event & OHCI1394_postedWriteErr))
1493 fw_error("PCI posted write error\n");
1495 if (unlikely(event & OHCI1394_cycleTooLong)) {
1496 if (printk_ratelimit())
1497 fw_notify("isochronous cycle too long\n");
1498 reg_write(ohci, OHCI1394_LinkControlSet,
1499 OHCI1394_LinkControl_cycleMaster);
1502 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1504 * We need to clear this event bit in order to make
1505 * cycleMatch isochronous I/O work. In theory we should
1506 * stop active cycleMatch iso contexts now and restart
1507 * them at least two cycles later. (FIXME?)
1509 if (printk_ratelimit())
1510 fw_notify("isochronous cycle inconsistent\n");
1516 static int software_reset(struct fw_ohci *ohci)
1520 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1522 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1523 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1524 OHCI1394_HCControl_softReset) == 0)
1532 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1534 size_t size = length * 4;
1536 memcpy(dest, src, size);
1537 if (size < CONFIG_ROM_SIZE)
1538 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1541 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1544 int ret, clear, set, offset;
1546 /* Check if the driver should configure link and PHY. */
1547 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1548 OHCI1394_HCControl_programPhyEnable))
1551 /* Paranoia: check whether the PHY supports 1394a, too. */
1552 enable_1394a = false;
1553 ret = read_phy_reg(ohci, 2);
1556 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1557 ret = read_paged_phy_reg(ohci, 1, 8);
1561 enable_1394a = true;
1564 if (ohci->quirks & QUIRK_NO_1394A)
1565 enable_1394a = false;
1567 /* Configure PHY and link consistently. */
1570 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1572 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1575 ret = ohci_update_phy_reg(&ohci->card, 5, clear, set);
1580 offset = OHCI1394_HCControlSet;
1582 offset = OHCI1394_HCControlClear;
1583 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1585 /* Clean up: configuration has been taken care of. */
1586 reg_write(ohci, OHCI1394_HCControlClear,
1587 OHCI1394_HCControl_programPhyEnable);
1592 static int ohci_enable(struct fw_card *card,
1593 const __be32 *config_rom, size_t length)
1595 struct fw_ohci *ohci = fw_ohci(card);
1596 struct pci_dev *dev = to_pci_dev(card->device);
1600 if (software_reset(ohci)) {
1601 fw_error("Failed to reset ohci card.\n");
1606 * Now enable LPS, which we need in order to start accessing
1607 * most of the registers. In fact, on some cards (ALI M5251),
1608 * accessing registers in the SClk domain without LPS enabled
1609 * will lock up the machine. Wait 50msec to make sure we have
1610 * full link enabled. However, with some cards (well, at least
1611 * a JMicron PCIe card), we have to try again sometimes.
1613 reg_write(ohci, OHCI1394_HCControlSet,
1614 OHCI1394_HCControl_LPS |
1615 OHCI1394_HCControl_postedWriteEnable);
1618 for (lps = 0, i = 0; !lps && i < 3; i++) {
1620 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1621 OHCI1394_HCControl_LPS;
1625 fw_error("Failed to set Link Power Status\n");
1629 reg_write(ohci, OHCI1394_HCControlClear,
1630 OHCI1394_HCControl_noByteSwapData);
1632 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1633 reg_write(ohci, OHCI1394_LinkControlClear,
1634 OHCI1394_LinkControl_rcvPhyPkt);
1635 reg_write(ohci, OHCI1394_LinkControlSet,
1636 OHCI1394_LinkControl_rcvSelfID |
1637 OHCI1394_LinkControl_cycleTimerEnable |
1638 OHCI1394_LinkControl_cycleMaster);
1640 reg_write(ohci, OHCI1394_ATRetries,
1641 OHCI1394_MAX_AT_REQ_RETRIES |
1642 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1643 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1645 ar_context_run(&ohci->ar_request_ctx);
1646 ar_context_run(&ohci->ar_response_ctx);
1648 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1649 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1650 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1651 reg_write(ohci, OHCI1394_IntMaskSet,
1652 OHCI1394_selfIDComplete |
1653 OHCI1394_RQPkt | OHCI1394_RSPkt |
1654 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1655 OHCI1394_isochRx | OHCI1394_isochTx |
1656 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1657 OHCI1394_cycleInconsistent | OHCI1394_regAccessFail |
1658 OHCI1394_masterIntEnable);
1659 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1660 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1662 ret = configure_1394a_enhancements(ohci);
1666 /* Activate link_on bit and contender bit in our self ID packets.*/
1667 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1672 * When the link is not yet enabled, the atomic config rom
1673 * update mechanism described below in ohci_set_config_rom()
1674 * is not active. We have to update ConfigRomHeader and
1675 * BusOptions manually, and the write to ConfigROMmap takes
1676 * effect immediately. We tie this to the enabling of the
1677 * link, so we have a valid config rom before enabling - the
1678 * OHCI requires that ConfigROMhdr and BusOptions have valid
1679 * values before enabling.
1681 * However, when the ConfigROMmap is written, some controllers
1682 * always read back quadlets 0 and 2 from the config rom to
1683 * the ConfigRomHeader and BusOptions registers on bus reset.
1684 * They shouldn't do that in this initial case where the link
1685 * isn't enabled. This means we have to use the same
1686 * workaround here, setting the bus header to 0 and then write
1687 * the right values in the bus reset tasklet.
1691 ohci->next_config_rom =
1692 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1693 &ohci->next_config_rom_bus,
1695 if (ohci->next_config_rom == NULL)
1698 copy_config_rom(ohci->next_config_rom, config_rom, length);
1701 * In the suspend case, config_rom is NULL, which
1702 * means that we just reuse the old config rom.
1704 ohci->next_config_rom = ohci->config_rom;
1705 ohci->next_config_rom_bus = ohci->config_rom_bus;
1708 ohci->next_header = ohci->next_config_rom[0];
1709 ohci->next_config_rom[0] = 0;
1710 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1711 reg_write(ohci, OHCI1394_BusOptions,
1712 be32_to_cpu(ohci->next_config_rom[2]));
1713 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1715 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1717 if (request_irq(dev->irq, irq_handler,
1718 IRQF_SHARED, ohci_driver_name, ohci)) {
1719 fw_error("Failed to allocate shared interrupt %d.\n",
1721 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1722 ohci->config_rom, ohci->config_rom_bus);
1726 reg_write(ohci, OHCI1394_HCControlSet,
1727 OHCI1394_HCControl_linkEnable |
1728 OHCI1394_HCControl_BIBimageValid);
1732 * We are ready to go, initiate bus reset to finish the
1736 fw_core_initiate_bus_reset(&ohci->card, 1);
1741 static int ohci_set_config_rom(struct fw_card *card,
1742 const __be32 *config_rom, size_t length)
1744 struct fw_ohci *ohci;
1745 unsigned long flags;
1747 __be32 *next_config_rom;
1748 dma_addr_t uninitialized_var(next_config_rom_bus);
1750 ohci = fw_ohci(card);
1753 * When the OHCI controller is enabled, the config rom update
1754 * mechanism is a bit tricky, but easy enough to use. See
1755 * section 5.5.6 in the OHCI specification.
1757 * The OHCI controller caches the new config rom address in a
1758 * shadow register (ConfigROMmapNext) and needs a bus reset
1759 * for the changes to take place. When the bus reset is
1760 * detected, the controller loads the new values for the
1761 * ConfigRomHeader and BusOptions registers from the specified
1762 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1763 * shadow register. All automatically and atomically.
1765 * Now, there's a twist to this story. The automatic load of
1766 * ConfigRomHeader and BusOptions doesn't honor the
1767 * noByteSwapData bit, so with a be32 config rom, the
1768 * controller will load be32 values in to these registers
1769 * during the atomic update, even on litte endian
1770 * architectures. The workaround we use is to put a 0 in the
1771 * header quadlet; 0 is endian agnostic and means that the
1772 * config rom isn't ready yet. In the bus reset tasklet we
1773 * then set up the real values for the two registers.
1775 * We use ohci->lock to avoid racing with the code that sets
1776 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1780 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1781 &next_config_rom_bus, GFP_KERNEL);
1782 if (next_config_rom == NULL)
1785 spin_lock_irqsave(&ohci->lock, flags);
1787 if (ohci->next_config_rom == NULL) {
1788 ohci->next_config_rom = next_config_rom;
1789 ohci->next_config_rom_bus = next_config_rom_bus;
1791 copy_config_rom(ohci->next_config_rom, config_rom, length);
1793 ohci->next_header = config_rom[0];
1794 ohci->next_config_rom[0] = 0;
1796 reg_write(ohci, OHCI1394_ConfigROMmap,
1797 ohci->next_config_rom_bus);
1801 spin_unlock_irqrestore(&ohci->lock, flags);
1804 * Now initiate a bus reset to have the changes take
1805 * effect. We clean up the old config rom memory and DMA
1806 * mappings in the bus reset tasklet, since the OHCI
1807 * controller could need to access it before the bus reset
1811 fw_core_initiate_bus_reset(&ohci->card, 1);
1813 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1814 next_config_rom, next_config_rom_bus);
1819 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1821 struct fw_ohci *ohci = fw_ohci(card);
1823 at_context_transmit(&ohci->at_request_ctx, packet);
1826 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1828 struct fw_ohci *ohci = fw_ohci(card);
1830 at_context_transmit(&ohci->at_response_ctx, packet);
1833 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1835 struct fw_ohci *ohci = fw_ohci(card);
1836 struct context *ctx = &ohci->at_request_ctx;
1837 struct driver_data *driver_data = packet->driver_data;
1840 tasklet_disable(&ctx->tasklet);
1842 if (packet->ack != 0)
1845 if (packet->payload_mapped)
1846 dma_unmap_single(ohci->card.device, packet->payload_bus,
1847 packet->payload_length, DMA_TO_DEVICE);
1849 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1850 driver_data->packet = NULL;
1851 packet->ack = RCODE_CANCELLED;
1852 packet->callback(packet, &ohci->card, packet->ack);
1855 tasklet_enable(&ctx->tasklet);
1860 static int ohci_enable_phys_dma(struct fw_card *card,
1861 int node_id, int generation)
1863 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1866 struct fw_ohci *ohci = fw_ohci(card);
1867 unsigned long flags;
1871 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1872 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1875 spin_lock_irqsave(&ohci->lock, flags);
1877 if (ohci->generation != generation) {
1883 * Note, if the node ID contains a non-local bus ID, physical DMA is
1884 * enabled for _all_ nodes on remote buses.
1887 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1889 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1891 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1895 spin_unlock_irqrestore(&ohci->lock, flags);
1898 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1901 static u32 cycle_timer_ticks(u32 cycle_timer)
1905 ticks = cycle_timer & 0xfff;
1906 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1907 ticks += (3072 * 8000) * (cycle_timer >> 25);
1913 * Some controllers exhibit one or more of the following bugs when updating the
1914 * iso cycle timer register:
1915 * - When the lowest six bits are wrapping around to zero, a read that happens
1916 * at the same time will return garbage in the lowest ten bits.
1917 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1918 * not incremented for about 60 ns.
1919 * - Occasionally, the entire register reads zero.
1921 * To catch these, we read the register three times and ensure that the
1922 * difference between each two consecutive reads is approximately the same, i.e.
1923 * less than twice the other. Furthermore, any negative difference indicates an
1924 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1925 * execute, so we have enough precision to compute the ratio of the differences.)
1927 static u32 ohci_get_cycle_time(struct fw_card *card)
1929 struct fw_ohci *ohci = fw_ohci(card);
1935 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1937 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1940 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1944 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1945 t0 = cycle_timer_ticks(c0);
1946 t1 = cycle_timer_ticks(c1);
1947 t2 = cycle_timer_ticks(c2);
1950 } while ((diff01 <= 0 || diff12 <= 0 ||
1951 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1958 static void copy_iso_headers(struct iso_context *ctx, void *p)
1960 int i = ctx->header_length;
1962 if (i + ctx->base.header_size > PAGE_SIZE)
1966 * The iso header is byteswapped to little endian by
1967 * the controller, but the remaining header quadlets
1968 * are big endian. We want to present all the headers
1969 * as big endian, so we have to swap the first quadlet.
1971 if (ctx->base.header_size > 0)
1972 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1973 if (ctx->base.header_size > 4)
1974 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1975 if (ctx->base.header_size > 8)
1976 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1977 ctx->header_length += ctx->base.header_size;
1980 static int handle_ir_packet_per_buffer(struct context *context,
1981 struct descriptor *d,
1982 struct descriptor *last)
1984 struct iso_context *ctx =
1985 container_of(context, struct iso_context, context);
1986 struct descriptor *pd;
1990 for (pd = d; pd <= last; pd++) {
1991 if (pd->transfer_status)
1995 /* Descriptor(s) not done yet, stop iteration */
1999 copy_iso_headers(ctx, p);
2001 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2002 ir_header = (__le32 *) p;
2003 ctx->base.callback(&ctx->base,
2004 le32_to_cpu(ir_header[0]) & 0xffff,
2005 ctx->header_length, ctx->header,
2006 ctx->base.callback_data);
2007 ctx->header_length = 0;
2013 static int handle_it_packet(struct context *context,
2014 struct descriptor *d,
2015 struct descriptor *last)
2017 struct iso_context *ctx =
2018 container_of(context, struct iso_context, context);
2020 struct descriptor *pd;
2022 for (pd = d; pd <= last; pd++)
2023 if (pd->transfer_status)
2026 /* Descriptor(s) not done yet, stop iteration */
2029 i = ctx->header_length;
2030 if (i + 4 < PAGE_SIZE) {
2031 /* Present this value as big-endian to match the receive code */
2032 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2033 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2034 le16_to_cpu(pd->res_count));
2035 ctx->header_length += 4;
2037 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2038 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
2039 ctx->header_length, ctx->header,
2040 ctx->base.callback_data);
2041 ctx->header_length = 0;
2046 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2047 int type, int channel, size_t header_size)
2049 struct fw_ohci *ohci = fw_ohci(card);
2050 struct iso_context *ctx, *list;
2051 descriptor_callback_t callback;
2052 u64 *channels, dont_care = ~0ULL;
2054 unsigned long flags;
2055 int index, ret = -ENOMEM;
2057 if (type == FW_ISO_CONTEXT_TRANSMIT) {
2058 channels = &dont_care;
2059 mask = &ohci->it_context_mask;
2060 list = ohci->it_context_list;
2061 callback = handle_it_packet;
2063 channels = &ohci->ir_context_channels;
2064 mask = &ohci->ir_context_mask;
2065 list = ohci->ir_context_list;
2066 callback = handle_ir_packet_per_buffer;
2069 spin_lock_irqsave(&ohci->lock, flags);
2070 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2072 *channels &= ~(1ULL << channel);
2073 *mask &= ~(1 << index);
2075 spin_unlock_irqrestore(&ohci->lock, flags);
2078 return ERR_PTR(-EBUSY);
2080 if (type == FW_ISO_CONTEXT_TRANSMIT)
2081 regs = OHCI1394_IsoXmitContextBase(index);
2083 regs = OHCI1394_IsoRcvContextBase(index);
2086 memset(ctx, 0, sizeof(*ctx));
2087 ctx->header_length = 0;
2088 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2089 if (ctx->header == NULL)
2092 ret = context_init(&ctx->context, ohci, regs, callback);
2094 goto out_with_header;
2099 free_page((unsigned long)ctx->header);
2101 spin_lock_irqsave(&ohci->lock, flags);
2102 *mask |= 1 << index;
2103 spin_unlock_irqrestore(&ohci->lock, flags);
2105 return ERR_PTR(ret);
2108 static int ohci_start_iso(struct fw_iso_context *base,
2109 s32 cycle, u32 sync, u32 tags)
2111 struct iso_context *ctx = container_of(base, struct iso_context, base);
2112 struct fw_ohci *ohci = ctx->context.ohci;
2116 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2117 index = ctx - ohci->it_context_list;
2120 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2121 (cycle & 0x7fff) << 16;
2123 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2124 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2125 context_run(&ctx->context, match);
2127 index = ctx - ohci->ir_context_list;
2128 control = IR_CONTEXT_ISOCH_HEADER;
2129 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2131 match |= (cycle & 0x07fff) << 12;
2132 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2135 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2136 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2137 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2138 context_run(&ctx->context, control);
2144 static int ohci_stop_iso(struct fw_iso_context *base)
2146 struct fw_ohci *ohci = fw_ohci(base->card);
2147 struct iso_context *ctx = container_of(base, struct iso_context, base);
2150 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2151 index = ctx - ohci->it_context_list;
2152 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2154 index = ctx - ohci->ir_context_list;
2155 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2158 context_stop(&ctx->context);
2163 static void ohci_free_iso_context(struct fw_iso_context *base)
2165 struct fw_ohci *ohci = fw_ohci(base->card);
2166 struct iso_context *ctx = container_of(base, struct iso_context, base);
2167 unsigned long flags;
2170 ohci_stop_iso(base);
2171 context_release(&ctx->context);
2172 free_page((unsigned long)ctx->header);
2174 spin_lock_irqsave(&ohci->lock, flags);
2176 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2177 index = ctx - ohci->it_context_list;
2178 ohci->it_context_mask |= 1 << index;
2180 index = ctx - ohci->ir_context_list;
2181 ohci->ir_context_mask |= 1 << index;
2182 ohci->ir_context_channels |= 1ULL << base->channel;
2185 spin_unlock_irqrestore(&ohci->lock, flags);
2188 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2189 struct fw_iso_packet *packet,
2190 struct fw_iso_buffer *buffer,
2191 unsigned long payload)
2193 struct iso_context *ctx = container_of(base, struct iso_context, base);
2194 struct descriptor *d, *last, *pd;
2195 struct fw_iso_packet *p;
2197 dma_addr_t d_bus, page_bus;
2198 u32 z, header_z, payload_z, irq;
2199 u32 payload_index, payload_end_index, next_page_index;
2200 int page, end_page, i, length, offset;
2203 payload_index = payload;
2209 if (p->header_length > 0)
2212 /* Determine the first page the payload isn't contained in. */
2213 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2214 if (p->payload_length > 0)
2215 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2221 /* Get header size in number of descriptors. */
2222 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2224 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2229 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2230 d[0].req_count = cpu_to_le16(8);
2232 * Link the skip address to this descriptor itself. This causes
2233 * a context to skip a cycle whenever lost cycles or FIFO
2234 * overruns occur, without dropping the data. The application
2235 * should then decide whether this is an error condition or not.
2236 * FIXME: Make the context's cycle-lost behaviour configurable?
2238 d[0].branch_address = cpu_to_le32(d_bus | z);
2240 header = (__le32 *) &d[1];
2241 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2242 IT_HEADER_TAG(p->tag) |
2243 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2244 IT_HEADER_CHANNEL(ctx->base.channel) |
2245 IT_HEADER_SPEED(ctx->base.speed));
2247 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2248 p->payload_length));
2251 if (p->header_length > 0) {
2252 d[2].req_count = cpu_to_le16(p->header_length);
2253 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2254 memcpy(&d[z], p->header, p->header_length);
2257 pd = d + z - payload_z;
2258 payload_end_index = payload_index + p->payload_length;
2259 for (i = 0; i < payload_z; i++) {
2260 page = payload_index >> PAGE_SHIFT;
2261 offset = payload_index & ~PAGE_MASK;
2262 next_page_index = (page + 1) << PAGE_SHIFT;
2264 min(next_page_index, payload_end_index) - payload_index;
2265 pd[i].req_count = cpu_to_le16(length);
2267 page_bus = page_private(buffer->pages[page]);
2268 pd[i].data_address = cpu_to_le32(page_bus + offset);
2270 payload_index += length;
2274 irq = DESCRIPTOR_IRQ_ALWAYS;
2276 irq = DESCRIPTOR_NO_IRQ;
2278 last = z == 2 ? d : d + z - 1;
2279 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2281 DESCRIPTOR_BRANCH_ALWAYS |
2284 context_append(&ctx->context, d, z, header_z);
2289 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2290 struct fw_iso_packet *packet,
2291 struct fw_iso_buffer *buffer,
2292 unsigned long payload)
2294 struct iso_context *ctx = container_of(base, struct iso_context, base);
2295 struct descriptor *d, *pd;
2296 struct fw_iso_packet *p = packet;
2297 dma_addr_t d_bus, page_bus;
2298 u32 z, header_z, rest;
2300 int page, offset, packet_count, header_size, payload_per_buffer;
2303 * The OHCI controller puts the isochronous header and trailer in the
2304 * buffer, so we need at least 8 bytes.
2306 packet_count = p->header_length / ctx->base.header_size;
2307 header_size = max(ctx->base.header_size, (size_t)8);
2309 /* Get header size in number of descriptors. */
2310 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2311 page = payload >> PAGE_SHIFT;
2312 offset = payload & ~PAGE_MASK;
2313 payload_per_buffer = p->payload_length / packet_count;
2315 for (i = 0; i < packet_count; i++) {
2316 /* d points to the header descriptor */
2317 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2318 d = context_get_descriptors(&ctx->context,
2319 z + header_z, &d_bus);
2323 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2324 DESCRIPTOR_INPUT_MORE);
2325 if (p->skip && i == 0)
2326 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2327 d->req_count = cpu_to_le16(header_size);
2328 d->res_count = d->req_count;
2329 d->transfer_status = 0;
2330 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2332 rest = payload_per_buffer;
2334 for (j = 1; j < z; j++) {
2336 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2337 DESCRIPTOR_INPUT_MORE);
2339 if (offset + rest < PAGE_SIZE)
2342 length = PAGE_SIZE - offset;
2343 pd->req_count = cpu_to_le16(length);
2344 pd->res_count = pd->req_count;
2345 pd->transfer_status = 0;
2347 page_bus = page_private(buffer->pages[page]);
2348 pd->data_address = cpu_to_le32(page_bus + offset);
2350 offset = (offset + length) & ~PAGE_MASK;
2355 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2356 DESCRIPTOR_INPUT_LAST |
2357 DESCRIPTOR_BRANCH_ALWAYS);
2358 if (p->interrupt && i == packet_count - 1)
2359 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2361 context_append(&ctx->context, d, z, header_z);
2367 static int ohci_queue_iso(struct fw_iso_context *base,
2368 struct fw_iso_packet *packet,
2369 struct fw_iso_buffer *buffer,
2370 unsigned long payload)
2372 struct iso_context *ctx = container_of(base, struct iso_context, base);
2373 unsigned long flags;
2376 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2377 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2378 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2380 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2382 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2387 static const struct fw_card_driver ohci_driver = {
2388 .enable = ohci_enable,
2389 .update_phy_reg = ohci_update_phy_reg,
2390 .set_config_rom = ohci_set_config_rom,
2391 .send_request = ohci_send_request,
2392 .send_response = ohci_send_response,
2393 .cancel_packet = ohci_cancel_packet,
2394 .enable_phys_dma = ohci_enable_phys_dma,
2395 .get_cycle_time = ohci_get_cycle_time,
2397 .allocate_iso_context = ohci_allocate_iso_context,
2398 .free_iso_context = ohci_free_iso_context,
2399 .queue_iso = ohci_queue_iso,
2400 .start_iso = ohci_start_iso,
2401 .stop_iso = ohci_stop_iso,
2404 #ifdef CONFIG_PPC_PMAC
2405 static void pmac_ohci_on(struct pci_dev *dev)
2407 if (machine_is(powermac)) {
2408 struct device_node *ofn = pci_device_to_OF_node(dev);
2411 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2412 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2417 static void pmac_ohci_off(struct pci_dev *dev)
2419 if (machine_is(powermac)) {
2420 struct device_node *ofn = pci_device_to_OF_node(dev);
2423 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2424 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2429 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2430 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2431 #endif /* CONFIG_PPC_PMAC */
2433 static int __devinit pci_probe(struct pci_dev *dev,
2434 const struct pci_device_id *ent)
2436 struct fw_ohci *ohci;
2437 u32 bus_options, max_receive, link_speed, version, link_enh;
2439 int i, err, n_ir, n_it;
2442 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2448 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2452 err = pci_enable_device(dev);
2454 fw_error("Failed to enable OHCI hardware\n");
2458 pci_set_master(dev);
2459 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2460 pci_set_drvdata(dev, ohci);
2462 spin_lock_init(&ohci->lock);
2464 tasklet_init(&ohci->bus_reset_tasklet,
2465 bus_reset_tasklet, (unsigned long)ohci);
2467 err = pci_request_region(dev, 0, ohci_driver_name);
2469 fw_error("MMIO resource unavailable\n");
2473 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2474 if (ohci->registers == NULL) {
2475 fw_error("Failed to remap registers\n");
2480 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2481 if (ohci_quirks[i].vendor == dev->vendor &&
2482 (ohci_quirks[i].device == dev->device ||
2483 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2484 ohci->quirks = ohci_quirks[i].flags;
2488 ohci->quirks = param_quirks;
2490 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2491 if (dev->vendor == PCI_VENDOR_ID_TI) {
2492 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2494 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2495 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2496 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2498 /* use priority arbitration for asynchronous responses */
2499 link_enh |= TI_LinkEnh_enab_unfair;
2501 /* required for aPhyEnhanceEnable to work */
2502 link_enh |= TI_LinkEnh_enab_accel;
2504 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2507 ar_context_init(&ohci->ar_request_ctx, ohci,
2508 OHCI1394_AsReqRcvContextControlSet);
2510 ar_context_init(&ohci->ar_response_ctx, ohci,
2511 OHCI1394_AsRspRcvContextControlSet);
2513 context_init(&ohci->at_request_ctx, ohci,
2514 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2516 context_init(&ohci->at_response_ctx, ohci,
2517 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2519 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2520 ohci->ir_context_channels = ~0ULL;
2521 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2522 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2523 n_ir = hweight32(ohci->ir_context_mask);
2524 size = sizeof(struct iso_context) * n_ir;
2525 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2527 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2528 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2529 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2530 n_it = hweight32(ohci->it_context_mask);
2531 size = sizeof(struct iso_context) * n_it;
2532 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2534 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2539 /* self-id dma buffer allocation */
2540 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2544 if (ohci->self_id_cpu == NULL) {
2549 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2550 max_receive = (bus_options >> 12) & 0xf;
2551 link_speed = bus_options & 0x7;
2552 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2553 reg_read(ohci, OHCI1394_GUIDLo);
2555 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2559 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2560 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2561 "%d IR + %d IT contexts, quirks 0x%x\n",
2562 dev_name(&dev->dev), version >> 16, version & 0xff,
2563 n_ir, n_it, ohci->quirks);
2568 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2569 ohci->self_id_cpu, ohci->self_id_bus);
2571 kfree(ohci->ir_context_list);
2572 kfree(ohci->it_context_list);
2573 context_release(&ohci->at_response_ctx);
2574 context_release(&ohci->at_request_ctx);
2575 ar_context_release(&ohci->ar_response_ctx);
2576 ar_context_release(&ohci->ar_request_ctx);
2577 pci_iounmap(dev, ohci->registers);
2579 pci_release_region(dev, 0);
2581 pci_disable_device(dev);
2587 fw_error("Out of memory\n");
2592 static void pci_remove(struct pci_dev *dev)
2594 struct fw_ohci *ohci;
2596 ohci = pci_get_drvdata(dev);
2597 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2599 fw_core_remove_card(&ohci->card);
2602 * FIXME: Fail all pending packets here, now that the upper
2603 * layers can't queue any more.
2606 software_reset(ohci);
2607 free_irq(dev->irq, ohci);
2609 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2610 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2611 ohci->next_config_rom, ohci->next_config_rom_bus);
2612 if (ohci->config_rom)
2613 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2614 ohci->config_rom, ohci->config_rom_bus);
2615 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2616 ohci->self_id_cpu, ohci->self_id_bus);
2617 ar_context_release(&ohci->ar_request_ctx);
2618 ar_context_release(&ohci->ar_response_ctx);
2619 context_release(&ohci->at_request_ctx);
2620 context_release(&ohci->at_response_ctx);
2621 kfree(ohci->it_context_list);
2622 kfree(ohci->ir_context_list);
2623 pci_iounmap(dev, ohci->registers);
2624 pci_release_region(dev, 0);
2625 pci_disable_device(dev);
2629 fw_notify("Removed fw-ohci device.\n");
2633 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2635 struct fw_ohci *ohci = pci_get_drvdata(dev);
2638 software_reset(ohci);
2639 free_irq(dev->irq, ohci);
2640 err = pci_save_state(dev);
2642 fw_error("pci_save_state failed\n");
2645 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2647 fw_error("pci_set_power_state failed with %d\n", err);
2653 static int pci_resume(struct pci_dev *dev)
2655 struct fw_ohci *ohci = pci_get_drvdata(dev);
2659 pci_set_power_state(dev, PCI_D0);
2660 pci_restore_state(dev);
2661 err = pci_enable_device(dev);
2663 fw_error("pci_enable_device failed\n");
2667 return ohci_enable(&ohci->card, NULL, 0);
2671 static const struct pci_device_id pci_table[] = {
2672 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2676 MODULE_DEVICE_TABLE(pci, pci_table);
2678 static struct pci_driver fw_ohci_pci_driver = {
2679 .name = ohci_driver_name,
2680 .id_table = pci_table,
2682 .remove = pci_remove,
2684 .resume = pci_resume,
2685 .suspend = pci_suspend,
2689 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2690 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2691 MODULE_LICENSE("GPL");
2693 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2694 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2695 MODULE_ALIAS("ohci1394");
2698 static int __init fw_ohci_init(void)
2700 return pci_register_driver(&fw_ohci_pci_driver);
2703 static void __exit fw_ohci_cleanup(void)
2705 pci_unregister_driver(&fw_ohci_pci_driver);
2708 module_init(fw_ohci_init);
2709 module_exit(fw_ohci_cleanup);