2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/bug.h>
22 #include <linux/compiler.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/firewire.h>
27 #include <linux/firewire-constants.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/mutex.h>
37 #include <linux/pci.h>
38 #include <linux/pci_ids.h>
39 #include <linux/slab.h>
40 #include <linux/spinlock.h>
41 #include <linux/string.h>
42 #include <linux/time.h>
44 #include <asm/byteorder.h>
46 #include <asm/system.h>
48 #ifdef CONFIG_PPC_PMAC
49 #include <asm/pmac_feature.h>
55 #define DESCRIPTOR_OUTPUT_MORE 0
56 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
57 #define DESCRIPTOR_INPUT_MORE (2 << 12)
58 #define DESCRIPTOR_INPUT_LAST (3 << 12)
59 #define DESCRIPTOR_STATUS (1 << 11)
60 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
61 #define DESCRIPTOR_PING (1 << 7)
62 #define DESCRIPTOR_YY (1 << 6)
63 #define DESCRIPTOR_NO_IRQ (0 << 4)
64 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
65 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
66 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
67 #define DESCRIPTOR_WAIT (3 << 0)
73 __le32 branch_address;
75 __le16 transfer_status;
76 } __attribute__((aligned(16)));
78 #define CONTROL_SET(regs) (regs)
79 #define CONTROL_CLEAR(regs) ((regs) + 4)
80 #define COMMAND_PTR(regs) ((regs) + 12)
81 #define CONTEXT_MATCH(regs) ((regs) + 16)
84 struct descriptor descriptor;
85 struct ar_buffer *next;
91 struct ar_buffer *current_buffer;
92 struct ar_buffer *last_buffer;
95 struct tasklet_struct tasklet;
100 typedef int (*descriptor_callback_t)(struct context *ctx,
101 struct descriptor *d,
102 struct descriptor *last);
105 * A buffer that contains a block of DMA-able coherent memory used for
106 * storing a portion of a DMA descriptor program.
108 struct descriptor_buffer {
109 struct list_head list;
110 dma_addr_t buffer_bus;
113 struct descriptor buffer[0];
117 struct fw_ohci *ohci;
119 int total_allocation;
122 * List of page-sized buffers for storing DMA descriptors.
123 * Head of list contains buffers in use and tail of list contains
126 struct list_head buffer_list;
129 * Pointer to a buffer inside buffer_list that contains the tail
130 * end of the current DMA program.
132 struct descriptor_buffer *buffer_tail;
135 * The descriptor containing the branch address of the first
136 * descriptor that has not yet been filled by the device.
138 struct descriptor *last;
141 * The last descriptor in the DMA program. It contains the branch
142 * address that must be updated upon appending a new descriptor.
144 struct descriptor *prev;
146 descriptor_callback_t callback;
148 struct tasklet_struct tasklet;
151 #define IT_HEADER_SY(v) ((v) << 0)
152 #define IT_HEADER_TCODE(v) ((v) << 4)
153 #define IT_HEADER_CHANNEL(v) ((v) << 8)
154 #define IT_HEADER_TAG(v) ((v) << 14)
155 #define IT_HEADER_SPEED(v) ((v) << 16)
156 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
159 struct fw_iso_context base;
160 struct context context;
163 size_t header_length;
166 #define CONFIG_ROM_SIZE 1024
171 __iomem char *registers;
174 int request_generation; /* for timestamping incoming requests */
176 unsigned int pri_req_max;
179 bool csr_state_setclear_abdicate;
182 * Spinlock for accessing fw_ohci data. Never call out of
183 * this driver with this lock held.
187 struct mutex phy_reg_mutex;
189 struct ar_context ar_request_ctx;
190 struct ar_context ar_response_ctx;
191 struct context at_request_ctx;
192 struct context at_response_ctx;
194 u32 it_context_mask; /* unoccupied IT contexts */
195 struct iso_context *it_context_list;
196 u64 ir_context_channels; /* unoccupied channels */
197 u32 ir_context_mask; /* unoccupied IR contexts */
198 struct iso_context *ir_context_list;
199 u64 mc_channels; /* channels in use by the multichannel IR context */
203 dma_addr_t config_rom_bus;
204 __be32 *next_config_rom;
205 dma_addr_t next_config_rom_bus;
209 dma_addr_t self_id_bus;
210 struct tasklet_struct bus_reset_tasklet;
212 u32 self_id_buffer[512];
215 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
217 return container_of(card, struct fw_ohci, card);
220 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
221 #define IR_CONTEXT_BUFFER_FILL 0x80000000
222 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
223 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
224 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
225 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
227 #define CONTEXT_RUN 0x8000
228 #define CONTEXT_WAKE 0x1000
229 #define CONTEXT_DEAD 0x0800
230 #define CONTEXT_ACTIVE 0x0400
232 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
233 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
234 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
236 #define OHCI1394_REGISTER_SIZE 0x800
237 #define OHCI_LOOP_COUNT 500
238 #define OHCI1394_PCI_HCI_Control 0x40
239 #define SELF_ID_BUF_SIZE 0x800
240 #define OHCI_TCODE_PHY_PACKET 0x0e
241 #define OHCI_VERSION_1_1 0x010010
243 static char ohci_driver_name[] = KBUILD_MODNAME;
245 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
246 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
248 #define QUIRK_CYCLE_TIMER 1
249 #define QUIRK_RESET_PACKET 2
250 #define QUIRK_BE_HEADERS 4
251 #define QUIRK_NO_1394A 8
252 #define QUIRK_NO_MSI 16
254 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
255 static const struct {
256 unsigned short vendor, device, flags;
258 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
261 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
262 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
263 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
264 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
265 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
266 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
267 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
270 /* This overrides anything that was found in ohci_quirks[]. */
271 static int param_quirks;
272 module_param_named(quirks, param_quirks, int, 0644);
273 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
274 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
275 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
276 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
277 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
278 ", disable MSI = " __stringify(QUIRK_NO_MSI)
281 #define OHCI_PARAM_DEBUG_AT_AR 1
282 #define OHCI_PARAM_DEBUG_SELFIDS 2
283 #define OHCI_PARAM_DEBUG_IRQS 4
284 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
286 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
288 static int param_debug;
289 module_param_named(debug, param_debug, int, 0644);
290 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
291 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
292 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
293 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
294 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
295 ", or a combination, or all = -1)");
297 static void log_irqs(u32 evt)
299 if (likely(!(param_debug &
300 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
303 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
304 !(evt & OHCI1394_busReset))
307 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
308 evt & OHCI1394_selfIDComplete ? " selfID" : "",
309 evt & OHCI1394_RQPkt ? " AR_req" : "",
310 evt & OHCI1394_RSPkt ? " AR_resp" : "",
311 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
312 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
313 evt & OHCI1394_isochRx ? " IR" : "",
314 evt & OHCI1394_isochTx ? " IT" : "",
315 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
316 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
317 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
318 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
319 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
320 evt & OHCI1394_busReset ? " busReset" : "",
321 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
322 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
323 OHCI1394_respTxComplete | OHCI1394_isochRx |
324 OHCI1394_isochTx | OHCI1394_postedWriteErr |
325 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
326 OHCI1394_cycleInconsistent |
327 OHCI1394_regAccessFail | OHCI1394_busReset)
331 static const char *speed[] = {
332 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
334 static const char *power[] = {
335 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
336 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
338 static const char port[] = { '.', '-', 'p', 'c', };
340 static char _p(u32 *s, int shift)
342 return port[*s >> shift & 3];
345 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
347 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
350 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
351 self_id_count, generation, node_id);
353 for (; self_id_count--; ++s)
354 if ((*s & 1 << 23) == 0)
355 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
356 "%s gc=%d %s %s%s%s\n",
357 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
358 speed[*s >> 14 & 3], *s >> 16 & 63,
359 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
360 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
362 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
364 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
365 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
368 static const char *evts[] = {
369 [0x00] = "evt_no_status", [0x01] = "-reserved-",
370 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
371 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
372 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
373 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
374 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
375 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
376 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
377 [0x10] = "-reserved-", [0x11] = "ack_complete",
378 [0x12] = "ack_pending ", [0x13] = "-reserved-",
379 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
380 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
381 [0x18] = "-reserved-", [0x19] = "-reserved-",
382 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
383 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
384 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
385 [0x20] = "pending/cancelled",
387 static const char *tcodes[] = {
388 [0x0] = "QW req", [0x1] = "BW req",
389 [0x2] = "W resp", [0x3] = "-reserved-",
390 [0x4] = "QR req", [0x5] = "BR req",
391 [0x6] = "QR resp", [0x7] = "BR resp",
392 [0x8] = "cycle start", [0x9] = "Lk req",
393 [0xa] = "async stream packet", [0xb] = "Lk resp",
394 [0xc] = "-reserved-", [0xd] = "-reserved-",
395 [0xe] = "link internal", [0xf] = "-reserved-",
397 static const char *phys[] = {
398 [0x0] = "phy config packet", [0x1] = "link-on packet",
399 [0x2] = "self-id packet", [0x3] = "-reserved-",
402 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
404 int tcode = header[0] >> 4 & 0xf;
407 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
410 if (unlikely(evt >= ARRAY_SIZE(evts)))
413 if (evt == OHCI1394_evt_bus_reset) {
414 fw_notify("A%c evt_bus_reset, generation %d\n",
415 dir, (header[2] >> 16) & 0xff);
419 if (header[0] == ~header[1]) {
420 fw_notify("A%c %s, %s, %08x\n",
421 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
426 case 0x0: case 0x6: case 0x8:
427 snprintf(specific, sizeof(specific), " = %08x",
428 be32_to_cpu((__force __be32)header[3]));
430 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
431 snprintf(specific, sizeof(specific), " %x,%x",
432 header[3] >> 16, header[3] & 0xffff);
440 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
442 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
443 fw_notify("A%c spd %x tl %02x, "
446 dir, speed, header[0] >> 10 & 0x3f,
447 header[1] >> 16, header[0] >> 16, evts[evt],
448 tcodes[tcode], header[1] & 0xffff, header[2], specific);
451 fw_notify("A%c spd %x tl %02x, "
454 dir, speed, header[0] >> 10 & 0x3f,
455 header[1] >> 16, header[0] >> 16, evts[evt],
456 tcodes[tcode], specific);
462 #define param_debug 0
463 static inline void log_irqs(u32 evt) {}
464 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
465 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
467 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
469 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
471 writel(data, ohci->registers + offset);
474 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
476 return readl(ohci->registers + offset);
479 static inline void flush_writes(const struct fw_ohci *ohci)
481 /* Do a dummy read to flush writes. */
482 reg_read(ohci, OHCI1394_Version);
485 static int read_phy_reg(struct fw_ohci *ohci, int addr)
490 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
491 for (i = 0; i < 3 + 100; i++) {
492 val = reg_read(ohci, OHCI1394_PhyControl);
493 if (val & OHCI1394_PhyControl_ReadDone)
494 return OHCI1394_PhyControl_ReadData(val);
497 * Try a few times without waiting. Sleeping is necessary
498 * only when the link/PHY interface is busy.
503 fw_error("failed to read phy reg\n");
508 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
512 reg_write(ohci, OHCI1394_PhyControl,
513 OHCI1394_PhyControl_Write(addr, val));
514 for (i = 0; i < 3 + 100; i++) {
515 val = reg_read(ohci, OHCI1394_PhyControl);
516 if (!(val & OHCI1394_PhyControl_WritePending))
522 fw_error("failed to write phy reg\n");
527 static int update_phy_reg(struct fw_ohci *ohci, int addr,
528 int clear_bits, int set_bits)
530 int ret = read_phy_reg(ohci, addr);
535 * The interrupt status bits are cleared by writing a one bit.
536 * Avoid clearing them unless explicitly requested in set_bits.
539 clear_bits |= PHY_INT_STATUS_BITS;
541 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
544 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
548 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
552 return read_phy_reg(ohci, addr);
555 static int ohci_read_phy_reg(struct fw_card *card, int addr)
557 struct fw_ohci *ohci = fw_ohci(card);
560 mutex_lock(&ohci->phy_reg_mutex);
561 ret = read_phy_reg(ohci, addr);
562 mutex_unlock(&ohci->phy_reg_mutex);
567 static int ohci_update_phy_reg(struct fw_card *card, int addr,
568 int clear_bits, int set_bits)
570 struct fw_ohci *ohci = fw_ohci(card);
573 mutex_lock(&ohci->phy_reg_mutex);
574 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
575 mutex_unlock(&ohci->phy_reg_mutex);
580 static int ar_context_add_page(struct ar_context *ctx)
582 struct device *dev = ctx->ohci->card.device;
583 struct ar_buffer *ab;
584 dma_addr_t uninitialized_var(ab_bus);
587 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
592 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
593 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
595 DESCRIPTOR_BRANCH_ALWAYS);
596 offset = offsetof(struct ar_buffer, data);
597 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
598 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
599 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
600 ab->descriptor.branch_address = 0;
602 wmb(); /* finish init of new descriptors before branch_address update */
603 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
604 ctx->last_buffer->next = ab;
605 ctx->last_buffer = ab;
607 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
608 flush_writes(ctx->ohci);
613 static void ar_context_release(struct ar_context *ctx)
615 struct ar_buffer *ab, *ab_next;
619 for (ab = ctx->current_buffer; ab; ab = ab_next) {
621 offset = offsetof(struct ar_buffer, data);
622 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
623 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
628 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
629 #define cond_le32_to_cpu(v) \
630 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
632 #define cond_le32_to_cpu(v) le32_to_cpu(v)
635 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
637 struct fw_ohci *ohci = ctx->ohci;
639 u32 status, length, tcode;
642 p.header[0] = cond_le32_to_cpu(buffer[0]);
643 p.header[1] = cond_le32_to_cpu(buffer[1]);
644 p.header[2] = cond_le32_to_cpu(buffer[2]);
646 tcode = (p.header[0] >> 4) & 0x0f;
648 case TCODE_WRITE_QUADLET_REQUEST:
649 case TCODE_READ_QUADLET_RESPONSE:
650 p.header[3] = (__force __u32) buffer[3];
651 p.header_length = 16;
652 p.payload_length = 0;
655 case TCODE_READ_BLOCK_REQUEST :
656 p.header[3] = cond_le32_to_cpu(buffer[3]);
657 p.header_length = 16;
658 p.payload_length = 0;
661 case TCODE_WRITE_BLOCK_REQUEST:
662 case TCODE_READ_BLOCK_RESPONSE:
663 case TCODE_LOCK_REQUEST:
664 case TCODE_LOCK_RESPONSE:
665 p.header[3] = cond_le32_to_cpu(buffer[3]);
666 p.header_length = 16;
667 p.payload_length = p.header[3] >> 16;
670 case TCODE_WRITE_RESPONSE:
671 case TCODE_READ_QUADLET_REQUEST:
672 case OHCI_TCODE_PHY_PACKET:
673 p.header_length = 12;
674 p.payload_length = 0;
678 /* FIXME: Stop context, discard everything, and restart? */
680 p.payload_length = 0;
683 p.payload = (void *) buffer + p.header_length;
685 /* FIXME: What to do about evt_* errors? */
686 length = (p.header_length + p.payload_length + 3) / 4;
687 status = cond_le32_to_cpu(buffer[length]);
688 evt = (status >> 16) & 0x1f;
691 p.speed = (status >> 21) & 0x7;
692 p.timestamp = status & 0xffff;
693 p.generation = ohci->request_generation;
695 log_ar_at_event('R', p.speed, p.header, evt);
698 * Several controllers, notably from NEC and VIA, forget to
699 * write ack_complete status at PHY packet reception.
701 if (evt == OHCI1394_evt_no_status &&
702 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
703 p.ack = ACK_COMPLETE;
706 * The OHCI bus reset handler synthesizes a PHY packet with
707 * the new generation number when a bus reset happens (see
708 * section 8.4.2.3). This helps us determine when a request
709 * was received and make sure we send the response in the same
710 * generation. We only need this for requests; for responses
711 * we use the unique tlabel for finding the matching
714 * Alas some chips sometimes emit bus reset packets with a
715 * wrong generation. We set the correct generation for these
716 * at a slightly incorrect time (in bus_reset_tasklet).
718 if (evt == OHCI1394_evt_bus_reset) {
719 if (!(ohci->quirks & QUIRK_RESET_PACKET))
720 ohci->request_generation = (p.header[2] >> 16) & 0xff;
721 } else if (ctx == &ohci->ar_request_ctx) {
722 fw_core_handle_request(&ohci->card, &p);
724 fw_core_handle_response(&ohci->card, &p);
727 return buffer + length + 1;
730 static void ar_context_tasklet(unsigned long data)
732 struct ar_context *ctx = (struct ar_context *)data;
733 struct fw_ohci *ohci = ctx->ohci;
734 struct ar_buffer *ab;
735 struct descriptor *d;
738 ab = ctx->current_buffer;
741 if (d->res_count == 0) {
742 size_t size, size2, rest, pktsize, size3, offset;
743 dma_addr_t start_bus;
747 * This descriptor is finished and we may have a
748 * packet split across this and the next buffer. We
749 * reuse the page for reassembling the split packet.
752 offset = offsetof(struct ar_buffer, data);
754 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
759 size = start + PAGE_SIZE - ctx->pointer;
760 /* valid buffer data in the next page */
761 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
762 /* what actually fits in this page */
763 size2 = min(rest, (size_t)PAGE_SIZE - offset - size);
764 memmove(buffer, ctx->pointer, size);
765 memcpy(buffer + size, ab->data, size2);
768 void *next = handle_ar_packet(ctx, buffer);
769 pktsize = next - buffer;
770 if (pktsize >= size) {
772 * We have handled all the data that was
773 * originally in this page, so we can now
774 * continue in the next page.
779 /* move the next packet to the start of the buffer */
780 memmove(buffer, next, size + size2 - pktsize);
782 /* fill up this page again */
783 size3 = min(rest - size2,
784 (size_t)PAGE_SIZE - offset - size - size2);
785 memcpy(buffer + size + size2,
786 (void *) ab->data + size2, size3);
791 /* handle the packets that are fully in the next page */
792 buffer = (void *) ab->data +
793 (buffer - (start + offset + size));
794 end = (void *) ab->data + rest;
797 buffer = handle_ar_packet(ctx, buffer);
799 ctx->current_buffer = ab;
802 dma_free_coherent(ohci->card.device, PAGE_SIZE,
804 ar_context_add_page(ctx);
806 ctx->pointer = start + PAGE_SIZE;
809 buffer = ctx->pointer;
811 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
814 buffer = handle_ar_packet(ctx, buffer);
818 static int ar_context_init(struct ar_context *ctx,
819 struct fw_ohci *ohci, u32 regs)
825 ctx->last_buffer = &ab;
826 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
828 ar_context_add_page(ctx);
829 ar_context_add_page(ctx);
830 ctx->current_buffer = ab.next;
831 ctx->pointer = ctx->current_buffer->data;
836 static void ar_context_run(struct ar_context *ctx)
838 struct ar_buffer *ab = ctx->current_buffer;
842 offset = offsetof(struct ar_buffer, data);
843 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
845 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
846 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
847 flush_writes(ctx->ohci);
850 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
854 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
855 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
857 /* figure out which descriptor the branch address goes in */
858 if (z == 2 && (b == 3 || key == 2))
864 static void context_tasklet(unsigned long data)
866 struct context *ctx = (struct context *) data;
867 struct descriptor *d, *last;
870 struct descriptor_buffer *desc;
872 desc = list_entry(ctx->buffer_list.next,
873 struct descriptor_buffer, list);
875 while (last->branch_address != 0) {
876 struct descriptor_buffer *old_desc = desc;
877 address = le32_to_cpu(last->branch_address);
881 /* If the branch address points to a buffer outside of the
882 * current buffer, advance to the next buffer. */
883 if (address < desc->buffer_bus ||
884 address >= desc->buffer_bus + desc->used)
885 desc = list_entry(desc->list.next,
886 struct descriptor_buffer, list);
887 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
888 last = find_branch_descriptor(d, z);
890 if (!ctx->callback(ctx, d, last))
893 if (old_desc != desc) {
894 /* If we've advanced to the next buffer, move the
895 * previous buffer to the free list. */
898 spin_lock_irqsave(&ctx->ohci->lock, flags);
899 list_move_tail(&old_desc->list, &ctx->buffer_list);
900 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
907 * Allocate a new buffer and add it to the list of free buffers for this
908 * context. Must be called with ohci->lock held.
910 static int context_add_buffer(struct context *ctx)
912 struct descriptor_buffer *desc;
913 dma_addr_t uninitialized_var(bus_addr);
917 * 16MB of descriptors should be far more than enough for any DMA
918 * program. This will catch run-away userspace or DoS attacks.
920 if (ctx->total_allocation >= 16*1024*1024)
923 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
924 &bus_addr, GFP_ATOMIC);
928 offset = (void *)&desc->buffer - (void *)desc;
929 desc->buffer_size = PAGE_SIZE - offset;
930 desc->buffer_bus = bus_addr + offset;
933 list_add_tail(&desc->list, &ctx->buffer_list);
934 ctx->total_allocation += PAGE_SIZE;
939 static int context_init(struct context *ctx, struct fw_ohci *ohci,
940 u32 regs, descriptor_callback_t callback)
944 ctx->total_allocation = 0;
946 INIT_LIST_HEAD(&ctx->buffer_list);
947 if (context_add_buffer(ctx) < 0)
950 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
951 struct descriptor_buffer, list);
953 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
954 ctx->callback = callback;
957 * We put a dummy descriptor in the buffer that has a NULL
958 * branch address and looks like it's been sent. That way we
959 * have a descriptor to append DMA programs to.
961 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
962 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
963 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
964 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
965 ctx->last = ctx->buffer_tail->buffer;
966 ctx->prev = ctx->buffer_tail->buffer;
971 static void context_release(struct context *ctx)
973 struct fw_card *card = &ctx->ohci->card;
974 struct descriptor_buffer *desc, *tmp;
976 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
977 dma_free_coherent(card->device, PAGE_SIZE, desc,
979 ((void *)&desc->buffer - (void *)desc));
982 /* Must be called with ohci->lock held */
983 static struct descriptor *context_get_descriptors(struct context *ctx,
984 int z, dma_addr_t *d_bus)
986 struct descriptor *d = NULL;
987 struct descriptor_buffer *desc = ctx->buffer_tail;
989 if (z * sizeof(*d) > desc->buffer_size)
992 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
993 /* No room for the descriptor in this buffer, so advance to the
996 if (desc->list.next == &ctx->buffer_list) {
997 /* If there is no free buffer next in the list,
999 if (context_add_buffer(ctx) < 0)
1002 desc = list_entry(desc->list.next,
1003 struct descriptor_buffer, list);
1004 ctx->buffer_tail = desc;
1007 d = desc->buffer + desc->used / sizeof(*d);
1008 memset(d, 0, z * sizeof(*d));
1009 *d_bus = desc->buffer_bus + desc->used;
1014 static void context_run(struct context *ctx, u32 extra)
1016 struct fw_ohci *ohci = ctx->ohci;
1018 reg_write(ohci, COMMAND_PTR(ctx->regs),
1019 le32_to_cpu(ctx->last->branch_address));
1020 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1021 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1025 static void context_append(struct context *ctx,
1026 struct descriptor *d, int z, int extra)
1029 struct descriptor_buffer *desc = ctx->buffer_tail;
1031 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1033 desc->used += (z + extra) * sizeof(*d);
1035 wmb(); /* finish init of new descriptors before branch_address update */
1036 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1037 ctx->prev = find_branch_descriptor(d, z);
1039 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1040 flush_writes(ctx->ohci);
1043 static void context_stop(struct context *ctx)
1048 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1049 flush_writes(ctx->ohci);
1051 for (i = 0; i < 10; i++) {
1052 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1053 if ((reg & CONTEXT_ACTIVE) == 0)
1058 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1061 struct driver_data {
1062 struct fw_packet *packet;
1066 * This function apppends a packet to the DMA queue for transmission.
1067 * Must always be called with the ochi->lock held to ensure proper
1068 * generation handling and locking around packet queue manipulation.
1070 static int at_context_queue_packet(struct context *ctx,
1071 struct fw_packet *packet)
1073 struct fw_ohci *ohci = ctx->ohci;
1074 dma_addr_t d_bus, uninitialized_var(payload_bus);
1075 struct driver_data *driver_data;
1076 struct descriptor *d, *last;
1081 d = context_get_descriptors(ctx, 4, &d_bus);
1083 packet->ack = RCODE_SEND_ERROR;
1087 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1088 d[0].res_count = cpu_to_le16(packet->timestamp);
1091 * The DMA format for asyncronous link packets is different
1092 * from the IEEE1394 layout, so shift the fields around
1093 * accordingly. If header_length is 8, it's a PHY packet, to
1094 * which we need to prepend an extra quadlet.
1097 header = (__le32 *) &d[1];
1098 switch (packet->header_length) {
1101 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1102 (packet->speed << 16));
1103 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1104 (packet->header[0] & 0xffff0000));
1105 header[2] = cpu_to_le32(packet->header[2]);
1107 tcode = (packet->header[0] >> 4) & 0x0f;
1108 if (TCODE_IS_BLOCK_PACKET(tcode))
1109 header[3] = cpu_to_le32(packet->header[3]);
1111 header[3] = (__force __le32) packet->header[3];
1113 d[0].req_count = cpu_to_le16(packet->header_length);
1117 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1118 (packet->speed << 16));
1119 header[1] = cpu_to_le32(packet->header[0]);
1120 header[2] = cpu_to_le32(packet->header[1]);
1121 d[0].req_count = cpu_to_le16(12);
1123 if (is_ping_packet(packet->header))
1124 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1128 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1129 (packet->speed << 16));
1130 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1131 d[0].req_count = cpu_to_le16(8);
1136 packet->ack = RCODE_SEND_ERROR;
1140 driver_data = (struct driver_data *) &d[3];
1141 driver_data->packet = packet;
1142 packet->driver_data = driver_data;
1144 if (packet->payload_length > 0) {
1146 dma_map_single(ohci->card.device, packet->payload,
1147 packet->payload_length, DMA_TO_DEVICE);
1148 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1149 packet->ack = RCODE_SEND_ERROR;
1152 packet->payload_bus = payload_bus;
1153 packet->payload_mapped = true;
1155 d[2].req_count = cpu_to_le16(packet->payload_length);
1156 d[2].data_address = cpu_to_le32(payload_bus);
1164 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1165 DESCRIPTOR_IRQ_ALWAYS |
1166 DESCRIPTOR_BRANCH_ALWAYS);
1169 * If the controller and packet generations don't match, we need to
1170 * bail out and try again. If IntEvent.busReset is set, the AT context
1171 * is halted, so appending to the context and trying to run it is
1172 * futile. Most controllers do the right thing and just flush the AT
1173 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1174 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1175 * up stalling out. So we just bail out in software and try again
1176 * later, and everyone is happy.
1177 * FIXME: Document how the locking works.
1179 if (ohci->generation != packet->generation ||
1180 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1181 if (packet->payload_mapped)
1182 dma_unmap_single(ohci->card.device, payload_bus,
1183 packet->payload_length, DMA_TO_DEVICE);
1184 packet->ack = RCODE_GENERATION;
1188 context_append(ctx, d, z, 4 - z);
1190 /* If the context isn't already running, start it up. */
1191 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1192 if ((reg & CONTEXT_RUN) == 0)
1193 context_run(ctx, 0);
1198 static int handle_at_packet(struct context *context,
1199 struct descriptor *d,
1200 struct descriptor *last)
1202 struct driver_data *driver_data;
1203 struct fw_packet *packet;
1204 struct fw_ohci *ohci = context->ohci;
1207 if (last->transfer_status == 0)
1208 /* This descriptor isn't done yet, stop iteration. */
1211 driver_data = (struct driver_data *) &d[3];
1212 packet = driver_data->packet;
1214 /* This packet was cancelled, just continue. */
1217 if (packet->payload_mapped)
1218 dma_unmap_single(ohci->card.device, packet->payload_bus,
1219 packet->payload_length, DMA_TO_DEVICE);
1221 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1222 packet->timestamp = le16_to_cpu(last->res_count);
1224 log_ar_at_event('T', packet->speed, packet->header, evt);
1227 case OHCI1394_evt_timeout:
1228 /* Async response transmit timed out. */
1229 packet->ack = RCODE_CANCELLED;
1232 case OHCI1394_evt_flushed:
1234 * The packet was flushed should give same error as
1235 * when we try to use a stale generation count.
1237 packet->ack = RCODE_GENERATION;
1240 case OHCI1394_evt_missing_ack:
1242 * Using a valid (current) generation count, but the
1243 * node is not on the bus or not sending acks.
1245 packet->ack = RCODE_NO_ACK;
1248 case ACK_COMPLETE + 0x10:
1249 case ACK_PENDING + 0x10:
1250 case ACK_BUSY_X + 0x10:
1251 case ACK_BUSY_A + 0x10:
1252 case ACK_BUSY_B + 0x10:
1253 case ACK_DATA_ERROR + 0x10:
1254 case ACK_TYPE_ERROR + 0x10:
1255 packet->ack = evt - 0x10;
1259 packet->ack = RCODE_SEND_ERROR;
1263 packet->callback(packet, &ohci->card, packet->ack);
1268 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1269 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1270 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1271 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1272 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1274 static void handle_local_rom(struct fw_ohci *ohci,
1275 struct fw_packet *packet, u32 csr)
1277 struct fw_packet response;
1278 int tcode, length, i;
1280 tcode = HEADER_GET_TCODE(packet->header[0]);
1281 if (TCODE_IS_BLOCK_PACKET(tcode))
1282 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1286 i = csr - CSR_CONFIG_ROM;
1287 if (i + length > CONFIG_ROM_SIZE) {
1288 fw_fill_response(&response, packet->header,
1289 RCODE_ADDRESS_ERROR, NULL, 0);
1290 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1291 fw_fill_response(&response, packet->header,
1292 RCODE_TYPE_ERROR, NULL, 0);
1294 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1295 (void *) ohci->config_rom + i, length);
1298 fw_core_handle_response(&ohci->card, &response);
1301 static void handle_local_lock(struct fw_ohci *ohci,
1302 struct fw_packet *packet, u32 csr)
1304 struct fw_packet response;
1305 int tcode, length, ext_tcode, sel, try;
1306 __be32 *payload, lock_old;
1307 u32 lock_arg, lock_data;
1309 tcode = HEADER_GET_TCODE(packet->header[0]);
1310 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1311 payload = packet->payload;
1312 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1314 if (tcode == TCODE_LOCK_REQUEST &&
1315 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1316 lock_arg = be32_to_cpu(payload[0]);
1317 lock_data = be32_to_cpu(payload[1]);
1318 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1322 fw_fill_response(&response, packet->header,
1323 RCODE_TYPE_ERROR, NULL, 0);
1327 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1328 reg_write(ohci, OHCI1394_CSRData, lock_data);
1329 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1330 reg_write(ohci, OHCI1394_CSRControl, sel);
1332 for (try = 0; try < 20; try++)
1333 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1334 lock_old = cpu_to_be32(reg_read(ohci,
1336 fw_fill_response(&response, packet->header,
1338 &lock_old, sizeof(lock_old));
1342 fw_error("swap not done (CSR lock timeout)\n");
1343 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1346 fw_core_handle_response(&ohci->card, &response);
1349 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1353 if (ctx == &ctx->ohci->at_request_ctx) {
1354 packet->ack = ACK_PENDING;
1355 packet->callback(packet, &ctx->ohci->card, packet->ack);
1359 ((unsigned long long)
1360 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1362 csr = offset - CSR_REGISTER_BASE;
1364 /* Handle config rom reads. */
1365 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1366 handle_local_rom(ctx->ohci, packet, csr);
1368 case CSR_BUS_MANAGER_ID:
1369 case CSR_BANDWIDTH_AVAILABLE:
1370 case CSR_CHANNELS_AVAILABLE_HI:
1371 case CSR_CHANNELS_AVAILABLE_LO:
1372 handle_local_lock(ctx->ohci, packet, csr);
1375 if (ctx == &ctx->ohci->at_request_ctx)
1376 fw_core_handle_request(&ctx->ohci->card, packet);
1378 fw_core_handle_response(&ctx->ohci->card, packet);
1382 if (ctx == &ctx->ohci->at_response_ctx) {
1383 packet->ack = ACK_COMPLETE;
1384 packet->callback(packet, &ctx->ohci->card, packet->ack);
1388 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1390 unsigned long flags;
1393 spin_lock_irqsave(&ctx->ohci->lock, flags);
1395 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1396 ctx->ohci->generation == packet->generation) {
1397 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1398 handle_local_request(ctx, packet);
1402 ret = at_context_queue_packet(ctx, packet);
1403 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1406 packet->callback(packet, &ctx->ohci->card, packet->ack);
1410 static u32 cycle_timer_ticks(u32 cycle_timer)
1414 ticks = cycle_timer & 0xfff;
1415 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1416 ticks += (3072 * 8000) * (cycle_timer >> 25);
1422 * Some controllers exhibit one or more of the following bugs when updating the
1423 * iso cycle timer register:
1424 * - When the lowest six bits are wrapping around to zero, a read that happens
1425 * at the same time will return garbage in the lowest ten bits.
1426 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1427 * not incremented for about 60 ns.
1428 * - Occasionally, the entire register reads zero.
1430 * To catch these, we read the register three times and ensure that the
1431 * difference between each two consecutive reads is approximately the same, i.e.
1432 * less than twice the other. Furthermore, any negative difference indicates an
1433 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1434 * execute, so we have enough precision to compute the ratio of the differences.)
1436 static u32 get_cycle_time(struct fw_ohci *ohci)
1443 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1445 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1448 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1452 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1453 t0 = cycle_timer_ticks(c0);
1454 t1 = cycle_timer_ticks(c1);
1455 t2 = cycle_timer_ticks(c2);
1458 } while ((diff01 <= 0 || diff12 <= 0 ||
1459 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1467 * This function has to be called at least every 64 seconds. The bus_time
1468 * field stores not only the upper 25 bits of the BUS_TIME register but also
1469 * the most significant bit of the cycle timer in bit 6 so that we can detect
1470 * changes in this bit.
1472 static u32 update_bus_time(struct fw_ohci *ohci)
1474 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1476 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1477 ohci->bus_time += 0x40;
1479 return ohci->bus_time | cycle_time_seconds;
1482 static void bus_reset_tasklet(unsigned long data)
1484 struct fw_ohci *ohci = (struct fw_ohci *)data;
1485 int self_id_count, i, j, reg;
1486 int generation, new_generation;
1487 unsigned long flags;
1488 void *free_rom = NULL;
1489 dma_addr_t free_rom_bus = 0;
1492 reg = reg_read(ohci, OHCI1394_NodeID);
1493 if (!(reg & OHCI1394_NodeID_idValid)) {
1494 fw_notify("node ID not valid, new bus reset in progress\n");
1497 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1498 fw_notify("malconfigured bus\n");
1501 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1502 OHCI1394_NodeID_nodeNumber);
1504 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1505 if (!(ohci->is_root && is_new_root))
1506 reg_write(ohci, OHCI1394_LinkControlSet,
1507 OHCI1394_LinkControl_cycleMaster);
1508 ohci->is_root = is_new_root;
1510 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1511 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1512 fw_notify("inconsistent self IDs\n");
1516 * The count in the SelfIDCount register is the number of
1517 * bytes in the self ID receive buffer. Since we also receive
1518 * the inverted quadlets and a header quadlet, we shift one
1519 * bit extra to get the actual number of self IDs.
1521 self_id_count = (reg >> 3) & 0xff;
1522 if (self_id_count == 0 || self_id_count > 252) {
1523 fw_notify("inconsistent self IDs\n");
1526 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1529 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1530 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1531 fw_notify("inconsistent self IDs\n");
1534 ohci->self_id_buffer[j] =
1535 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1540 * Check the consistency of the self IDs we just read. The
1541 * problem we face is that a new bus reset can start while we
1542 * read out the self IDs from the DMA buffer. If this happens,
1543 * the DMA buffer will be overwritten with new self IDs and we
1544 * will read out inconsistent data. The OHCI specification
1545 * (section 11.2) recommends a technique similar to
1546 * linux/seqlock.h, where we remember the generation of the
1547 * self IDs in the buffer before reading them out and compare
1548 * it to the current generation after reading them out. If
1549 * the two generations match we know we have a consistent set
1553 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1554 if (new_generation != generation) {
1555 fw_notify("recursive bus reset detected, "
1556 "discarding self ids\n");
1560 /* FIXME: Document how the locking works. */
1561 spin_lock_irqsave(&ohci->lock, flags);
1563 ohci->generation = generation;
1564 context_stop(&ohci->at_request_ctx);
1565 context_stop(&ohci->at_response_ctx);
1566 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1568 if (ohci->quirks & QUIRK_RESET_PACKET)
1569 ohci->request_generation = generation;
1572 * This next bit is unrelated to the AT context stuff but we
1573 * have to do it under the spinlock also. If a new config rom
1574 * was set up before this reset, the old one is now no longer
1575 * in use and we can free it. Update the config rom pointers
1576 * to point to the current config rom and clear the
1577 * next_config_rom pointer so a new update can take place.
1580 if (ohci->next_config_rom != NULL) {
1581 if (ohci->next_config_rom != ohci->config_rom) {
1582 free_rom = ohci->config_rom;
1583 free_rom_bus = ohci->config_rom_bus;
1585 ohci->config_rom = ohci->next_config_rom;
1586 ohci->config_rom_bus = ohci->next_config_rom_bus;
1587 ohci->next_config_rom = NULL;
1590 * Restore config_rom image and manually update
1591 * config_rom registers. Writing the header quadlet
1592 * will indicate that the config rom is ready, so we
1595 reg_write(ohci, OHCI1394_BusOptions,
1596 be32_to_cpu(ohci->config_rom[2]));
1597 ohci->config_rom[0] = ohci->next_header;
1598 reg_write(ohci, OHCI1394_ConfigROMhdr,
1599 be32_to_cpu(ohci->next_header));
1602 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1603 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1604 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1607 spin_unlock_irqrestore(&ohci->lock, flags);
1610 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1611 free_rom, free_rom_bus);
1613 log_selfids(ohci->node_id, generation,
1614 self_id_count, ohci->self_id_buffer);
1616 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1617 self_id_count, ohci->self_id_buffer,
1618 ohci->csr_state_setclear_abdicate);
1619 ohci->csr_state_setclear_abdicate = false;
1622 static irqreturn_t irq_handler(int irq, void *data)
1624 struct fw_ohci *ohci = data;
1625 u32 event, iso_event;
1628 event = reg_read(ohci, OHCI1394_IntEventClear);
1630 if (!event || !~event)
1633 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1634 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1637 if (event & OHCI1394_selfIDComplete)
1638 tasklet_schedule(&ohci->bus_reset_tasklet);
1640 if (event & OHCI1394_RQPkt)
1641 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1643 if (event & OHCI1394_RSPkt)
1644 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1646 if (event & OHCI1394_reqTxComplete)
1647 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1649 if (event & OHCI1394_respTxComplete)
1650 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1652 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1653 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1656 i = ffs(iso_event) - 1;
1657 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1658 iso_event &= ~(1 << i);
1661 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1662 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1665 i = ffs(iso_event) - 1;
1666 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1667 iso_event &= ~(1 << i);
1670 if (unlikely(event & OHCI1394_regAccessFail))
1671 fw_error("Register access failure - "
1672 "please notify linux1394-devel@lists.sf.net\n");
1674 if (unlikely(event & OHCI1394_postedWriteErr))
1675 fw_error("PCI posted write error\n");
1677 if (unlikely(event & OHCI1394_cycleTooLong)) {
1678 if (printk_ratelimit())
1679 fw_notify("isochronous cycle too long\n");
1680 reg_write(ohci, OHCI1394_LinkControlSet,
1681 OHCI1394_LinkControl_cycleMaster);
1684 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1686 * We need to clear this event bit in order to make
1687 * cycleMatch isochronous I/O work. In theory we should
1688 * stop active cycleMatch iso contexts now and restart
1689 * them at least two cycles later. (FIXME?)
1691 if (printk_ratelimit())
1692 fw_notify("isochronous cycle inconsistent\n");
1695 if (event & OHCI1394_cycle64Seconds) {
1696 spin_lock(&ohci->lock);
1697 update_bus_time(ohci);
1698 spin_unlock(&ohci->lock);
1704 static int software_reset(struct fw_ohci *ohci)
1708 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1710 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1711 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1712 OHCI1394_HCControl_softReset) == 0)
1720 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1722 size_t size = length * 4;
1724 memcpy(dest, src, size);
1725 if (size < CONFIG_ROM_SIZE)
1726 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1729 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1732 int ret, clear, set, offset;
1734 /* Check if the driver should configure link and PHY. */
1735 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1736 OHCI1394_HCControl_programPhyEnable))
1739 /* Paranoia: check whether the PHY supports 1394a, too. */
1740 enable_1394a = false;
1741 ret = read_phy_reg(ohci, 2);
1744 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1745 ret = read_paged_phy_reg(ohci, 1, 8);
1749 enable_1394a = true;
1752 if (ohci->quirks & QUIRK_NO_1394A)
1753 enable_1394a = false;
1755 /* Configure PHY and link consistently. */
1758 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1760 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1763 ret = update_phy_reg(ohci, 5, clear, set);
1768 offset = OHCI1394_HCControlSet;
1770 offset = OHCI1394_HCControlClear;
1771 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1773 /* Clean up: configuration has been taken care of. */
1774 reg_write(ohci, OHCI1394_HCControlClear,
1775 OHCI1394_HCControl_programPhyEnable);
1780 static int ohci_enable(struct fw_card *card,
1781 const __be32 *config_rom, size_t length)
1783 struct fw_ohci *ohci = fw_ohci(card);
1784 struct pci_dev *dev = to_pci_dev(card->device);
1785 u32 lps, seconds, version, irqs;
1788 if (software_reset(ohci)) {
1789 fw_error("Failed to reset ohci card.\n");
1794 * Now enable LPS, which we need in order to start accessing
1795 * most of the registers. In fact, on some cards (ALI M5251),
1796 * accessing registers in the SClk domain without LPS enabled
1797 * will lock up the machine. Wait 50msec to make sure we have
1798 * full link enabled. However, with some cards (well, at least
1799 * a JMicron PCIe card), we have to try again sometimes.
1801 reg_write(ohci, OHCI1394_HCControlSet,
1802 OHCI1394_HCControl_LPS |
1803 OHCI1394_HCControl_postedWriteEnable);
1806 for (lps = 0, i = 0; !lps && i < 3; i++) {
1808 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1809 OHCI1394_HCControl_LPS;
1813 fw_error("Failed to set Link Power Status\n");
1817 reg_write(ohci, OHCI1394_HCControlClear,
1818 OHCI1394_HCControl_noByteSwapData);
1820 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1821 reg_write(ohci, OHCI1394_LinkControlSet,
1822 OHCI1394_LinkControl_rcvSelfID |
1823 OHCI1394_LinkControl_rcvPhyPkt |
1824 OHCI1394_LinkControl_cycleTimerEnable |
1825 OHCI1394_LinkControl_cycleMaster);
1827 reg_write(ohci, OHCI1394_ATRetries,
1828 OHCI1394_MAX_AT_REQ_RETRIES |
1829 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1830 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1833 seconds = lower_32_bits(get_seconds());
1834 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1835 ohci->bus_time = seconds & ~0x3f;
1837 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1838 if (version >= OHCI_VERSION_1_1) {
1839 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1841 card->broadcast_channel_auto_allocated = true;
1844 /* Get implemented bits of the priority arbitration request counter. */
1845 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1846 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1847 reg_write(ohci, OHCI1394_FairnessControl, 0);
1848 card->priority_budget_implemented = ohci->pri_req_max != 0;
1850 ar_context_run(&ohci->ar_request_ctx);
1851 ar_context_run(&ohci->ar_response_ctx);
1853 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1854 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1855 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1857 ret = configure_1394a_enhancements(ohci);
1861 /* Activate link_on bit and contender bit in our self ID packets.*/
1862 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1867 * When the link is not yet enabled, the atomic config rom
1868 * update mechanism described below in ohci_set_config_rom()
1869 * is not active. We have to update ConfigRomHeader and
1870 * BusOptions manually, and the write to ConfigROMmap takes
1871 * effect immediately. We tie this to the enabling of the
1872 * link, so we have a valid config rom before enabling - the
1873 * OHCI requires that ConfigROMhdr and BusOptions have valid
1874 * values before enabling.
1876 * However, when the ConfigROMmap is written, some controllers
1877 * always read back quadlets 0 and 2 from the config rom to
1878 * the ConfigRomHeader and BusOptions registers on bus reset.
1879 * They shouldn't do that in this initial case where the link
1880 * isn't enabled. This means we have to use the same
1881 * workaround here, setting the bus header to 0 and then write
1882 * the right values in the bus reset tasklet.
1886 ohci->next_config_rom =
1887 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1888 &ohci->next_config_rom_bus,
1890 if (ohci->next_config_rom == NULL)
1893 copy_config_rom(ohci->next_config_rom, config_rom, length);
1896 * In the suspend case, config_rom is NULL, which
1897 * means that we just reuse the old config rom.
1899 ohci->next_config_rom = ohci->config_rom;
1900 ohci->next_config_rom_bus = ohci->config_rom_bus;
1903 ohci->next_header = ohci->next_config_rom[0];
1904 ohci->next_config_rom[0] = 0;
1905 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1906 reg_write(ohci, OHCI1394_BusOptions,
1907 be32_to_cpu(ohci->next_config_rom[2]));
1908 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1910 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1912 if (!(ohci->quirks & QUIRK_NO_MSI))
1913 pci_enable_msi(dev);
1914 if (request_irq(dev->irq, irq_handler,
1915 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1916 ohci_driver_name, ohci)) {
1917 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1918 pci_disable_msi(dev);
1919 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1920 ohci->config_rom, ohci->config_rom_bus);
1924 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1925 OHCI1394_RQPkt | OHCI1394_RSPkt |
1926 OHCI1394_isochTx | OHCI1394_isochRx |
1927 OHCI1394_postedWriteErr |
1928 OHCI1394_selfIDComplete |
1929 OHCI1394_regAccessFail |
1930 OHCI1394_cycle64Seconds |
1931 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1932 OHCI1394_masterIntEnable;
1933 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1934 irqs |= OHCI1394_busReset;
1935 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1937 reg_write(ohci, OHCI1394_HCControlSet,
1938 OHCI1394_HCControl_linkEnable |
1939 OHCI1394_HCControl_BIBimageValid);
1942 /* We are ready to go, reset bus to finish initialization. */
1943 fw_schedule_bus_reset(&ohci->card, false, true);
1948 static int ohci_set_config_rom(struct fw_card *card,
1949 const __be32 *config_rom, size_t length)
1951 struct fw_ohci *ohci;
1952 unsigned long flags;
1954 __be32 *next_config_rom;
1955 dma_addr_t uninitialized_var(next_config_rom_bus);
1957 ohci = fw_ohci(card);
1960 * When the OHCI controller is enabled, the config rom update
1961 * mechanism is a bit tricky, but easy enough to use. See
1962 * section 5.5.6 in the OHCI specification.
1964 * The OHCI controller caches the new config rom address in a
1965 * shadow register (ConfigROMmapNext) and needs a bus reset
1966 * for the changes to take place. When the bus reset is
1967 * detected, the controller loads the new values for the
1968 * ConfigRomHeader and BusOptions registers from the specified
1969 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1970 * shadow register. All automatically and atomically.
1972 * Now, there's a twist to this story. The automatic load of
1973 * ConfigRomHeader and BusOptions doesn't honor the
1974 * noByteSwapData bit, so with a be32 config rom, the
1975 * controller will load be32 values in to these registers
1976 * during the atomic update, even on litte endian
1977 * architectures. The workaround we use is to put a 0 in the
1978 * header quadlet; 0 is endian agnostic and means that the
1979 * config rom isn't ready yet. In the bus reset tasklet we
1980 * then set up the real values for the two registers.
1982 * We use ohci->lock to avoid racing with the code that sets
1983 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1987 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1988 &next_config_rom_bus, GFP_KERNEL);
1989 if (next_config_rom == NULL)
1992 spin_lock_irqsave(&ohci->lock, flags);
1994 if (ohci->next_config_rom == NULL) {
1995 ohci->next_config_rom = next_config_rom;
1996 ohci->next_config_rom_bus = next_config_rom_bus;
1998 copy_config_rom(ohci->next_config_rom, config_rom, length);
2000 ohci->next_header = config_rom[0];
2001 ohci->next_config_rom[0] = 0;
2003 reg_write(ohci, OHCI1394_ConfigROMmap,
2004 ohci->next_config_rom_bus);
2008 spin_unlock_irqrestore(&ohci->lock, flags);
2011 * Now initiate a bus reset to have the changes take
2012 * effect. We clean up the old config rom memory and DMA
2013 * mappings in the bus reset tasklet, since the OHCI
2014 * controller could need to access it before the bus reset
2018 fw_schedule_bus_reset(&ohci->card, true, true);
2020 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2021 next_config_rom, next_config_rom_bus);
2026 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2028 struct fw_ohci *ohci = fw_ohci(card);
2030 at_context_transmit(&ohci->at_request_ctx, packet);
2033 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2035 struct fw_ohci *ohci = fw_ohci(card);
2037 at_context_transmit(&ohci->at_response_ctx, packet);
2040 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2042 struct fw_ohci *ohci = fw_ohci(card);
2043 struct context *ctx = &ohci->at_request_ctx;
2044 struct driver_data *driver_data = packet->driver_data;
2047 tasklet_disable(&ctx->tasklet);
2049 if (packet->ack != 0)
2052 if (packet->payload_mapped)
2053 dma_unmap_single(ohci->card.device, packet->payload_bus,
2054 packet->payload_length, DMA_TO_DEVICE);
2056 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2057 driver_data->packet = NULL;
2058 packet->ack = RCODE_CANCELLED;
2059 packet->callback(packet, &ohci->card, packet->ack);
2062 tasklet_enable(&ctx->tasklet);
2067 static int ohci_enable_phys_dma(struct fw_card *card,
2068 int node_id, int generation)
2070 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2073 struct fw_ohci *ohci = fw_ohci(card);
2074 unsigned long flags;
2078 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2079 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2082 spin_lock_irqsave(&ohci->lock, flags);
2084 if (ohci->generation != generation) {
2090 * Note, if the node ID contains a non-local bus ID, physical DMA is
2091 * enabled for _all_ nodes on remote buses.
2094 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2096 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2098 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2102 spin_unlock_irqrestore(&ohci->lock, flags);
2105 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2108 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2110 struct fw_ohci *ohci = fw_ohci(card);
2111 unsigned long flags;
2114 switch (csr_offset) {
2115 case CSR_STATE_CLEAR:
2117 if (ohci->is_root &&
2118 (reg_read(ohci, OHCI1394_LinkControlSet) &
2119 OHCI1394_LinkControl_cycleMaster))
2120 value = CSR_STATE_BIT_CMSTR;
2123 if (ohci->csr_state_setclear_abdicate)
2124 value |= CSR_STATE_BIT_ABDICATE;
2129 return reg_read(ohci, OHCI1394_NodeID) << 16;
2131 case CSR_CYCLE_TIME:
2132 return get_cycle_time(ohci);
2136 * We might be called just after the cycle timer has wrapped
2137 * around but just before the cycle64Seconds handler, so we
2138 * better check here, too, if the bus time needs to be updated.
2140 spin_lock_irqsave(&ohci->lock, flags);
2141 value = update_bus_time(ohci);
2142 spin_unlock_irqrestore(&ohci->lock, flags);
2145 case CSR_BUSY_TIMEOUT:
2146 value = reg_read(ohci, OHCI1394_ATRetries);
2147 return (value >> 4) & 0x0ffff00f;
2149 case CSR_PRIORITY_BUDGET:
2150 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2151 (ohci->pri_req_max << 8);
2159 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2161 struct fw_ohci *ohci = fw_ohci(card);
2162 unsigned long flags;
2164 switch (csr_offset) {
2165 case CSR_STATE_CLEAR:
2166 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2167 reg_write(ohci, OHCI1394_LinkControlClear,
2168 OHCI1394_LinkControl_cycleMaster);
2171 if (value & CSR_STATE_BIT_ABDICATE)
2172 ohci->csr_state_setclear_abdicate = false;
2176 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2177 reg_write(ohci, OHCI1394_LinkControlSet,
2178 OHCI1394_LinkControl_cycleMaster);
2181 if (value & CSR_STATE_BIT_ABDICATE)
2182 ohci->csr_state_setclear_abdicate = true;
2186 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2190 case CSR_CYCLE_TIME:
2191 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2192 reg_write(ohci, OHCI1394_IntEventSet,
2193 OHCI1394_cycleInconsistent);
2198 spin_lock_irqsave(&ohci->lock, flags);
2199 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2200 spin_unlock_irqrestore(&ohci->lock, flags);
2203 case CSR_BUSY_TIMEOUT:
2204 value = (value & 0xf) | ((value & 0xf) << 4) |
2205 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2206 reg_write(ohci, OHCI1394_ATRetries, value);
2210 case CSR_PRIORITY_BUDGET:
2211 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2221 static void copy_iso_headers(struct iso_context *ctx, void *p)
2223 int i = ctx->header_length;
2225 if (i + ctx->base.header_size > PAGE_SIZE)
2229 * The iso header is byteswapped to little endian by
2230 * the controller, but the remaining header quadlets
2231 * are big endian. We want to present all the headers
2232 * as big endian, so we have to swap the first quadlet.
2234 if (ctx->base.header_size > 0)
2235 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2236 if (ctx->base.header_size > 4)
2237 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2238 if (ctx->base.header_size > 8)
2239 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2240 ctx->header_length += ctx->base.header_size;
2243 static int handle_ir_packet_per_buffer(struct context *context,
2244 struct descriptor *d,
2245 struct descriptor *last)
2247 struct iso_context *ctx =
2248 container_of(context, struct iso_context, context);
2249 struct descriptor *pd;
2253 for (pd = d; pd <= last; pd++)
2254 if (pd->transfer_status)
2257 /* Descriptor(s) not done yet, stop iteration */
2261 copy_iso_headers(ctx, p);
2263 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2264 ir_header = (__le32 *) p;
2265 ctx->base.callback.sc(&ctx->base,
2266 le32_to_cpu(ir_header[0]) & 0xffff,
2267 ctx->header_length, ctx->header,
2268 ctx->base.callback_data);
2269 ctx->header_length = 0;
2275 /* d == last because each descriptor block is only a single descriptor. */
2276 static int handle_ir_buffer_fill(struct context *context,
2277 struct descriptor *d,
2278 struct descriptor *last)
2280 struct iso_context *ctx =
2281 container_of(context, struct iso_context, context);
2283 if (!last->transfer_status)
2284 /* Descriptor(s) not done yet, stop iteration */
2287 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2288 ctx->base.callback.mc(&ctx->base,
2289 le32_to_cpu(last->data_address) +
2290 le16_to_cpu(last->req_count) -
2291 le16_to_cpu(last->res_count),
2292 ctx->base.callback_data);
2297 static int handle_it_packet(struct context *context,
2298 struct descriptor *d,
2299 struct descriptor *last)
2301 struct iso_context *ctx =
2302 container_of(context, struct iso_context, context);
2304 struct descriptor *pd;
2306 for (pd = d; pd <= last; pd++)
2307 if (pd->transfer_status)
2310 /* Descriptor(s) not done yet, stop iteration */
2313 i = ctx->header_length;
2314 if (i + 4 < PAGE_SIZE) {
2315 /* Present this value as big-endian to match the receive code */
2316 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2317 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2318 le16_to_cpu(pd->res_count));
2319 ctx->header_length += 4;
2321 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2322 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2323 ctx->header_length, ctx->header,
2324 ctx->base.callback_data);
2325 ctx->header_length = 0;
2330 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2332 u32 hi = channels >> 32, lo = channels;
2334 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2335 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2336 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2337 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2339 ohci->mc_channels = channels;
2342 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2343 int type, int channel, size_t header_size)
2345 struct fw_ohci *ohci = fw_ohci(card);
2346 struct iso_context *uninitialized_var(ctx);
2347 descriptor_callback_t uninitialized_var(callback);
2348 u64 *uninitialized_var(channels);
2349 u32 *uninitialized_var(mask), uninitialized_var(regs);
2350 unsigned long flags;
2351 int index, ret = -EBUSY;
2353 spin_lock_irqsave(&ohci->lock, flags);
2356 case FW_ISO_CONTEXT_TRANSMIT:
2357 mask = &ohci->it_context_mask;
2358 callback = handle_it_packet;
2359 index = ffs(*mask) - 1;
2361 *mask &= ~(1 << index);
2362 regs = OHCI1394_IsoXmitContextBase(index);
2363 ctx = &ohci->it_context_list[index];
2367 case FW_ISO_CONTEXT_RECEIVE:
2368 channels = &ohci->ir_context_channels;
2369 mask = &ohci->ir_context_mask;
2370 callback = handle_ir_packet_per_buffer;
2371 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2373 *channels &= ~(1ULL << channel);
2374 *mask &= ~(1 << index);
2375 regs = OHCI1394_IsoRcvContextBase(index);
2376 ctx = &ohci->ir_context_list[index];
2380 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2381 mask = &ohci->ir_context_mask;
2382 callback = handle_ir_buffer_fill;
2383 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2385 ohci->mc_allocated = true;
2386 *mask &= ~(1 << index);
2387 regs = OHCI1394_IsoRcvContextBase(index);
2388 ctx = &ohci->ir_context_list[index];
2397 spin_unlock_irqrestore(&ohci->lock, flags);
2400 return ERR_PTR(ret);
2402 memset(ctx, 0, sizeof(*ctx));
2403 ctx->header_length = 0;
2404 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2405 if (ctx->header == NULL) {
2409 ret = context_init(&ctx->context, ohci, regs, callback);
2411 goto out_with_header;
2413 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2414 set_multichannel_mask(ohci, 0);
2419 free_page((unsigned long)ctx->header);
2421 spin_lock_irqsave(&ohci->lock, flags);
2424 case FW_ISO_CONTEXT_RECEIVE:
2425 *channels |= 1ULL << channel;
2428 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2429 ohci->mc_allocated = false;
2432 *mask |= 1 << index;
2434 spin_unlock_irqrestore(&ohci->lock, flags);
2436 return ERR_PTR(ret);
2439 static int ohci_start_iso(struct fw_iso_context *base,
2440 s32 cycle, u32 sync, u32 tags)
2442 struct iso_context *ctx = container_of(base, struct iso_context, base);
2443 struct fw_ohci *ohci = ctx->context.ohci;
2444 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2447 switch (ctx->base.type) {
2448 case FW_ISO_CONTEXT_TRANSMIT:
2449 index = ctx - ohci->it_context_list;
2452 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2453 (cycle & 0x7fff) << 16;
2455 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2456 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2457 context_run(&ctx->context, match);
2460 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2461 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2463 case FW_ISO_CONTEXT_RECEIVE:
2464 index = ctx - ohci->ir_context_list;
2465 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2467 match |= (cycle & 0x07fff) << 12;
2468 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2471 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2472 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2473 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2474 context_run(&ctx->context, control);
2481 static int ohci_stop_iso(struct fw_iso_context *base)
2483 struct fw_ohci *ohci = fw_ohci(base->card);
2484 struct iso_context *ctx = container_of(base, struct iso_context, base);
2487 switch (ctx->base.type) {
2488 case FW_ISO_CONTEXT_TRANSMIT:
2489 index = ctx - ohci->it_context_list;
2490 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2493 case FW_ISO_CONTEXT_RECEIVE:
2494 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2495 index = ctx - ohci->ir_context_list;
2496 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2500 context_stop(&ctx->context);
2505 static void ohci_free_iso_context(struct fw_iso_context *base)
2507 struct fw_ohci *ohci = fw_ohci(base->card);
2508 struct iso_context *ctx = container_of(base, struct iso_context, base);
2509 unsigned long flags;
2512 ohci_stop_iso(base);
2513 context_release(&ctx->context);
2514 free_page((unsigned long)ctx->header);
2516 spin_lock_irqsave(&ohci->lock, flags);
2518 switch (base->type) {
2519 case FW_ISO_CONTEXT_TRANSMIT:
2520 index = ctx - ohci->it_context_list;
2521 ohci->it_context_mask |= 1 << index;
2524 case FW_ISO_CONTEXT_RECEIVE:
2525 index = ctx - ohci->ir_context_list;
2526 ohci->ir_context_mask |= 1 << index;
2527 ohci->ir_context_channels |= 1ULL << base->channel;
2530 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2531 index = ctx - ohci->ir_context_list;
2532 ohci->ir_context_mask |= 1 << index;
2533 ohci->ir_context_channels |= ohci->mc_channels;
2534 ohci->mc_channels = 0;
2535 ohci->mc_allocated = false;
2539 spin_unlock_irqrestore(&ohci->lock, flags);
2542 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2544 struct fw_ohci *ohci = fw_ohci(base->card);
2545 unsigned long flags;
2548 switch (base->type) {
2549 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2551 spin_lock_irqsave(&ohci->lock, flags);
2553 /* Don't allow multichannel to grab other contexts' channels. */
2554 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2555 *channels = ohci->ir_context_channels;
2558 set_multichannel_mask(ohci, *channels);
2562 spin_unlock_irqrestore(&ohci->lock, flags);
2572 static int queue_iso_transmit(struct iso_context *ctx,
2573 struct fw_iso_packet *packet,
2574 struct fw_iso_buffer *buffer,
2575 unsigned long payload)
2577 struct descriptor *d, *last, *pd;
2578 struct fw_iso_packet *p;
2580 dma_addr_t d_bus, page_bus;
2581 u32 z, header_z, payload_z, irq;
2582 u32 payload_index, payload_end_index, next_page_index;
2583 int page, end_page, i, length, offset;
2586 payload_index = payload;
2592 if (p->header_length > 0)
2595 /* Determine the first page the payload isn't contained in. */
2596 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2597 if (p->payload_length > 0)
2598 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2604 /* Get header size in number of descriptors. */
2605 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2607 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2612 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2613 d[0].req_count = cpu_to_le16(8);
2615 * Link the skip address to this descriptor itself. This causes
2616 * a context to skip a cycle whenever lost cycles or FIFO
2617 * overruns occur, without dropping the data. The application
2618 * should then decide whether this is an error condition or not.
2619 * FIXME: Make the context's cycle-lost behaviour configurable?
2621 d[0].branch_address = cpu_to_le32(d_bus | z);
2623 header = (__le32 *) &d[1];
2624 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2625 IT_HEADER_TAG(p->tag) |
2626 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2627 IT_HEADER_CHANNEL(ctx->base.channel) |
2628 IT_HEADER_SPEED(ctx->base.speed));
2630 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2631 p->payload_length));
2634 if (p->header_length > 0) {
2635 d[2].req_count = cpu_to_le16(p->header_length);
2636 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2637 memcpy(&d[z], p->header, p->header_length);
2640 pd = d + z - payload_z;
2641 payload_end_index = payload_index + p->payload_length;
2642 for (i = 0; i < payload_z; i++) {
2643 page = payload_index >> PAGE_SHIFT;
2644 offset = payload_index & ~PAGE_MASK;
2645 next_page_index = (page + 1) << PAGE_SHIFT;
2647 min(next_page_index, payload_end_index) - payload_index;
2648 pd[i].req_count = cpu_to_le16(length);
2650 page_bus = page_private(buffer->pages[page]);
2651 pd[i].data_address = cpu_to_le32(page_bus + offset);
2653 payload_index += length;
2657 irq = DESCRIPTOR_IRQ_ALWAYS;
2659 irq = DESCRIPTOR_NO_IRQ;
2661 last = z == 2 ? d : d + z - 1;
2662 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2664 DESCRIPTOR_BRANCH_ALWAYS |
2667 context_append(&ctx->context, d, z, header_z);
2672 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2673 struct fw_iso_packet *packet,
2674 struct fw_iso_buffer *buffer,
2675 unsigned long payload)
2677 struct descriptor *d, *pd;
2678 dma_addr_t d_bus, page_bus;
2679 u32 z, header_z, rest;
2681 int page, offset, packet_count, header_size, payload_per_buffer;
2684 * The OHCI controller puts the isochronous header and trailer in the
2685 * buffer, so we need at least 8 bytes.
2687 packet_count = packet->header_length / ctx->base.header_size;
2688 header_size = max(ctx->base.header_size, (size_t)8);
2690 /* Get header size in number of descriptors. */
2691 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2692 page = payload >> PAGE_SHIFT;
2693 offset = payload & ~PAGE_MASK;
2694 payload_per_buffer = packet->payload_length / packet_count;
2696 for (i = 0; i < packet_count; i++) {
2697 /* d points to the header descriptor */
2698 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2699 d = context_get_descriptors(&ctx->context,
2700 z + header_z, &d_bus);
2704 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2705 DESCRIPTOR_INPUT_MORE);
2706 if (packet->skip && i == 0)
2707 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2708 d->req_count = cpu_to_le16(header_size);
2709 d->res_count = d->req_count;
2710 d->transfer_status = 0;
2711 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2713 rest = payload_per_buffer;
2715 for (j = 1; j < z; j++) {
2717 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2718 DESCRIPTOR_INPUT_MORE);
2720 if (offset + rest < PAGE_SIZE)
2723 length = PAGE_SIZE - offset;
2724 pd->req_count = cpu_to_le16(length);
2725 pd->res_count = pd->req_count;
2726 pd->transfer_status = 0;
2728 page_bus = page_private(buffer->pages[page]);
2729 pd->data_address = cpu_to_le32(page_bus + offset);
2731 offset = (offset + length) & ~PAGE_MASK;
2736 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2737 DESCRIPTOR_INPUT_LAST |
2738 DESCRIPTOR_BRANCH_ALWAYS);
2739 if (packet->interrupt && i == packet_count - 1)
2740 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2742 context_append(&ctx->context, d, z, header_z);
2748 static int queue_iso_buffer_fill(struct iso_context *ctx,
2749 struct fw_iso_packet *packet,
2750 struct fw_iso_buffer *buffer,
2751 unsigned long payload)
2753 struct descriptor *d;
2754 dma_addr_t d_bus, page_bus;
2755 int page, offset, rest, z, i, length;
2757 page = payload >> PAGE_SHIFT;
2758 offset = payload & ~PAGE_MASK;
2759 rest = packet->payload_length;
2761 /* We need one descriptor for each page in the buffer. */
2762 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2764 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2767 for (i = 0; i < z; i++) {
2768 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2772 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2773 DESCRIPTOR_BRANCH_ALWAYS);
2774 if (packet->skip && i == 0)
2775 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2776 if (packet->interrupt && i == z - 1)
2777 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2779 if (offset + rest < PAGE_SIZE)
2782 length = PAGE_SIZE - offset;
2783 d->req_count = cpu_to_le16(length);
2784 d->res_count = d->req_count;
2785 d->transfer_status = 0;
2787 page_bus = page_private(buffer->pages[page]);
2788 d->data_address = cpu_to_le32(page_bus + offset);
2794 context_append(&ctx->context, d, 1, 0);
2800 static int ohci_queue_iso(struct fw_iso_context *base,
2801 struct fw_iso_packet *packet,
2802 struct fw_iso_buffer *buffer,
2803 unsigned long payload)
2805 struct iso_context *ctx = container_of(base, struct iso_context, base);
2806 unsigned long flags;
2809 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2810 switch (base->type) {
2811 case FW_ISO_CONTEXT_TRANSMIT:
2812 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2814 case FW_ISO_CONTEXT_RECEIVE:
2815 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2817 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2818 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2821 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2826 static const struct fw_card_driver ohci_driver = {
2827 .enable = ohci_enable,
2828 .read_phy_reg = ohci_read_phy_reg,
2829 .update_phy_reg = ohci_update_phy_reg,
2830 .set_config_rom = ohci_set_config_rom,
2831 .send_request = ohci_send_request,
2832 .send_response = ohci_send_response,
2833 .cancel_packet = ohci_cancel_packet,
2834 .enable_phys_dma = ohci_enable_phys_dma,
2835 .read_csr = ohci_read_csr,
2836 .write_csr = ohci_write_csr,
2838 .allocate_iso_context = ohci_allocate_iso_context,
2839 .free_iso_context = ohci_free_iso_context,
2840 .set_iso_channels = ohci_set_iso_channels,
2841 .queue_iso = ohci_queue_iso,
2842 .start_iso = ohci_start_iso,
2843 .stop_iso = ohci_stop_iso,
2846 #ifdef CONFIG_PPC_PMAC
2847 static void pmac_ohci_on(struct pci_dev *dev)
2849 if (machine_is(powermac)) {
2850 struct device_node *ofn = pci_device_to_OF_node(dev);
2853 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2854 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2859 static void pmac_ohci_off(struct pci_dev *dev)
2861 if (machine_is(powermac)) {
2862 struct device_node *ofn = pci_device_to_OF_node(dev);
2865 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2866 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2871 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2872 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2873 #endif /* CONFIG_PPC_PMAC */
2875 static int __devinit pci_probe(struct pci_dev *dev,
2876 const struct pci_device_id *ent)
2878 struct fw_ohci *ohci;
2879 u32 bus_options, max_receive, link_speed, version;
2881 int i, err, n_ir, n_it;
2884 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2890 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2894 err = pci_enable_device(dev);
2896 fw_error("Failed to enable OHCI hardware\n");
2900 pci_set_master(dev);
2901 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2902 pci_set_drvdata(dev, ohci);
2904 spin_lock_init(&ohci->lock);
2905 mutex_init(&ohci->phy_reg_mutex);
2907 tasklet_init(&ohci->bus_reset_tasklet,
2908 bus_reset_tasklet, (unsigned long)ohci);
2910 err = pci_request_region(dev, 0, ohci_driver_name);
2912 fw_error("MMIO resource unavailable\n");
2916 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2917 if (ohci->registers == NULL) {
2918 fw_error("Failed to remap registers\n");
2923 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2924 if (ohci_quirks[i].vendor == dev->vendor &&
2925 (ohci_quirks[i].device == dev->device ||
2926 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2927 ohci->quirks = ohci_quirks[i].flags;
2931 ohci->quirks = param_quirks;
2933 ar_context_init(&ohci->ar_request_ctx, ohci,
2934 OHCI1394_AsReqRcvContextControlSet);
2936 ar_context_init(&ohci->ar_response_ctx, ohci,
2937 OHCI1394_AsRspRcvContextControlSet);
2939 context_init(&ohci->at_request_ctx, ohci,
2940 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2942 context_init(&ohci->at_response_ctx, ohci,
2943 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2945 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2946 ohci->ir_context_channels = ~0ULL;
2947 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2948 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2949 n_ir = hweight32(ohci->ir_context_mask);
2950 size = sizeof(struct iso_context) * n_ir;
2951 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2953 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2954 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2955 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2956 n_it = hweight32(ohci->it_context_mask);
2957 size = sizeof(struct iso_context) * n_it;
2958 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2960 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2965 /* self-id dma buffer allocation */
2966 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2970 if (ohci->self_id_cpu == NULL) {
2975 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2976 max_receive = (bus_options >> 12) & 0xf;
2977 link_speed = bus_options & 0x7;
2978 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2979 reg_read(ohci, OHCI1394_GUIDLo);
2981 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2985 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2986 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2987 "%d IR + %d IT contexts, quirks 0x%x\n",
2988 dev_name(&dev->dev), version >> 16, version & 0xff,
2989 n_ir, n_it, ohci->quirks);
2994 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2995 ohci->self_id_cpu, ohci->self_id_bus);
2997 kfree(ohci->ir_context_list);
2998 kfree(ohci->it_context_list);
2999 context_release(&ohci->at_response_ctx);
3000 context_release(&ohci->at_request_ctx);
3001 ar_context_release(&ohci->ar_response_ctx);
3002 ar_context_release(&ohci->ar_request_ctx);
3003 pci_iounmap(dev, ohci->registers);
3005 pci_release_region(dev, 0);
3007 pci_disable_device(dev);
3013 fw_error("Out of memory\n");
3018 static void pci_remove(struct pci_dev *dev)
3020 struct fw_ohci *ohci;
3022 ohci = pci_get_drvdata(dev);
3023 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3025 fw_core_remove_card(&ohci->card);
3028 * FIXME: Fail all pending packets here, now that the upper
3029 * layers can't queue any more.
3032 software_reset(ohci);
3033 free_irq(dev->irq, ohci);
3035 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3036 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3037 ohci->next_config_rom, ohci->next_config_rom_bus);
3038 if (ohci->config_rom)
3039 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3040 ohci->config_rom, ohci->config_rom_bus);
3041 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3042 ohci->self_id_cpu, ohci->self_id_bus);
3043 ar_context_release(&ohci->ar_request_ctx);
3044 ar_context_release(&ohci->ar_response_ctx);
3045 context_release(&ohci->at_request_ctx);
3046 context_release(&ohci->at_response_ctx);
3047 kfree(ohci->it_context_list);
3048 kfree(ohci->ir_context_list);
3049 pci_disable_msi(dev);
3050 pci_iounmap(dev, ohci->registers);
3051 pci_release_region(dev, 0);
3052 pci_disable_device(dev);
3056 fw_notify("Removed fw-ohci device.\n");
3060 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3062 struct fw_ohci *ohci = pci_get_drvdata(dev);
3065 software_reset(ohci);
3066 free_irq(dev->irq, ohci);
3067 pci_disable_msi(dev);
3068 err = pci_save_state(dev);
3070 fw_error("pci_save_state failed\n");
3073 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3075 fw_error("pci_set_power_state failed with %d\n", err);
3081 static int pci_resume(struct pci_dev *dev)
3083 struct fw_ohci *ohci = pci_get_drvdata(dev);
3087 pci_set_power_state(dev, PCI_D0);
3088 pci_restore_state(dev);
3089 err = pci_enable_device(dev);
3091 fw_error("pci_enable_device failed\n");
3095 return ohci_enable(&ohci->card, NULL, 0);
3099 static const struct pci_device_id pci_table[] = {
3100 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3104 MODULE_DEVICE_TABLE(pci, pci_table);
3106 static struct pci_driver fw_ohci_pci_driver = {
3107 .name = ohci_driver_name,
3108 .id_table = pci_table,
3110 .remove = pci_remove,
3112 .resume = pci_resume,
3113 .suspend = pci_suspend,
3117 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3118 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3119 MODULE_LICENSE("GPL");
3121 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3122 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3123 MODULE_ALIAS("ohci1394");
3126 static int __init fw_ohci_init(void)
3128 return pci_register_driver(&fw_ohci_pci_driver);
3131 static void __exit fw_ohci_cleanup(void)
3133 pci_unregister_driver(&fw_ohci_pci_driver);
3136 module_init(fw_ohci_init);
3137 module_exit(fw_ohci_cleanup);