drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/compiler.h>
  22 #include <linux/delay.h>
  23 #include <linux/device.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/firewire.h>
  26 #include <linux/firewire-constants.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kernel.h>
  31 #include <linux/list.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci_ids.h>
  37 #include <linux/slab.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/string.h>
  40
  41 #include <asm/byteorder.h>
  42 #include <asm/page.h>
  43 #include <asm/system.h>
  44
  45 #ifdef CONFIG_PPC_PMAC
  46 #include <asm/pmac_feature.h>
  47 #endif
  48
  49 #include "core.h"
  50 #include "ohci.h"
  51
  52 #define DESCRIPTOR_OUTPUT_MORE          0
  53 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  54 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  55 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  56 #define DESCRIPTOR_STATUS               (1 << 11)
  57 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  58 #define DESCRIPTOR_PING                 (1 << 7)
  59 #define DESCRIPTOR_YY                   (1 << 6)
  60 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  61 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  62 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  63 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  64 #define DESCRIPTOR_WAIT                 (3 << 0)
  65
  66 struct descriptor {
  67         __le16 req_count;
  68         __le16 control;
  69         __le32 data_address;
  70         __le32 branch_address;
  71         __le16 res_count;
  72         __le16 transfer_status;
  73 } __attribute__((aligned(16)));
  74
  75 #define CONTROL_SET(regs)       (regs)
  76 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  77 #define COMMAND_PTR(regs)       ((regs) + 12)
  78 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  79
  80 struct ar_buffer {
  81         struct descriptor descriptor;
  82         struct ar_buffer *next;
  83         __le32 data[0];
  84 };
  85
  86 struct ar_context {
  87         struct fw_ohci *ohci;
  88         struct ar_buffer *current_buffer;
  89         struct ar_buffer *last_buffer;
  90         void *pointer;
  91         u32 regs;
  92         struct tasklet_struct tasklet;
  93 };
  94
  95 struct context;
  96
  97 typedef int (*descriptor_callback_t)(struct context *ctx,
  98                                      struct descriptor *d,
  99                                      struct descriptor *last);
 100
 101 /*
 102  * A buffer that contains a block of DMA-able coherent memory used for
 103  * storing a portion of a DMA descriptor program.
 104  */
 105 struct descriptor_buffer {
 106         struct list_head list;
 107         dma_addr_t buffer_bus;
 108         size_t buffer_size;
 109         size_t used;
 110         struct descriptor buffer[0];
 111 };
 112
 113 struct context {
 114         struct fw_ohci *ohci;
 115         u32 regs;
 116         int total_allocation;
 117
 118         /*
 119          * List of page-sized buffers for storing DMA descriptors.
 120          * Head of list contains buffers in use and tail of list contains
 121          * free buffers.
 122          */
 123         struct list_head buffer_list;
 124
 125         /*
 126          * Pointer to a buffer inside buffer_list that contains the tail
 127          * end of the current DMA program.
 128          */
 129         struct descriptor_buffer *buffer_tail;
 130
 131         /*
 132          * The descriptor containing the branch address of the first
 133          * descriptor that has not yet been filled by the device.
 134          */
 135         struct descriptor *last;
 136
 137         /*
 138          * The last descriptor in the DMA program.  It contains the branch
 139          * address that must be updated upon appending a new descriptor.
 140          */
 141         struct descriptor *prev;
 142
 143         descriptor_callback_t callback;
 144
 145         struct tasklet_struct tasklet;
 146 };
 147
 148 #define IT_HEADER_SY(v)          ((v) <<  0)
 149 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 150 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 151 #define IT_HEADER_TAG(v)         ((v) << 14)
 152 #define IT_HEADER_SPEED(v)       ((v) << 16)
 153 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 154
 155 struct iso_context {
 156         struct fw_iso_context base;
 157         struct context context;
 158         int excess_bytes;
 159         void *header;
 160         size_t header_length;
 161 };
 162
 163 #define CONFIG_ROM_SIZE 1024
 164
 165 struct fw_ohci {
 166         struct fw_card card;
 167
 168         __iomem char *registers;
 169         int node_id;
 170         int generation;
 171         int request_generation; /* for timestamping incoming requests */
 172         unsigned quirks;
 173
 174         /*
 175          * Spinlock for accessing fw_ohci data.  Never call out of
 176          * this driver with this lock held.
 177          */
 178         spinlock_t lock;
 179
 180         struct ar_context ar_request_ctx;
 181         struct ar_context ar_response_ctx;
 182         struct context at_request_ctx;
 183         struct context at_response_ctx;
 184
 185         u32 it_context_mask;
 186         struct iso_context *it_context_list;
 187         u64 ir_context_channels;
 188         u32 ir_context_mask;
 189         struct iso_context *ir_context_list;
 190
 191         __be32    *config_rom;
 192         dma_addr_t config_rom_bus;
 193         __be32    *next_config_rom;
 194         dma_addr_t next_config_rom_bus;
 195         __be32     next_header;
 196
 197         __le32    *self_id_cpu;
 198         dma_addr_t self_id_bus;
 199         struct tasklet_struct bus_reset_tasklet;
 200
 201         u32 self_id_buffer[512];
 202 };
 203
 204 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 205 {
 206         return container_of(card, struct fw_ohci, card);
 207 }
 208
 209 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 210 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 211 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 212 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 213 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 214 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 215
 216 #define CONTEXT_RUN     0x8000
 217 #define CONTEXT_WAKE    0x1000
 218 #define CONTEXT_DEAD    0x0800
 219 #define CONTEXT_ACTIVE  0x0400
 220
 221 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 222 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 223 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 224
 225 #define OHCI1394_REGISTER_SIZE          0x800
 226 #define OHCI_LOOP_COUNT                 500
 227 #define OHCI1394_PCI_HCI_Control        0x40
 228 #define SELF_ID_BUF_SIZE                0x800
 229 #define OHCI_TCODE_PHY_PACKET           0x0e
 230 #define OHCI_VERSION_1_1                0x010010
 231
 232 static char ohci_driver_name[] = KBUILD_MODNAME;
 233
 234 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 235
 236 #define QUIRK_CYCLE_TIMER               1
 237 #define QUIRK_RESET_PACKET              2
 238 #define QUIRK_BE_HEADERS                4
 239
 240 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 241 static const struct {
 242         unsigned short vendor, device, flags;
 243 } ohci_quirks[] = {
 244         {PCI_VENDOR_ID_TI,      PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
 245                                                             QUIRK_RESET_PACKET},
 246         {PCI_VENDOR_ID_TI,      PCI_ANY_ID,     QUIRK_RESET_PACKET},
 247         {PCI_VENDOR_ID_AL,      PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 248         {PCI_VENDOR_ID_NEC,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 249         {PCI_VENDOR_ID_VIA,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 250         {PCI_VENDOR_ID_APPLE,   PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
 251 };
 252
 253 /* This overrides anything that was found in ohci_quirks[]. */
 254 static int param_quirks;
 255 module_param_named(quirks, param_quirks, int, 0644);
 256 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 257         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 258         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 259         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 260         ")");
 261
 262 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 263
 264 #define OHCI_PARAM_DEBUG_AT_AR          1
 265 #define OHCI_PARAM_DEBUG_SELFIDS        2
 266 #define OHCI_PARAM_DEBUG_IRQS           4
 267 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 268
 269 static int param_debug;
 270 module_param_named(debug, param_debug, int, 0644);
 271 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 272         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 273         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 274         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 275         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 276         ", or a combination, or all = -1)");
 277
 278 static void log_irqs(u32 evt)
 279 {
 280         if (likely(!(param_debug &
 281                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 282                 return;
 283
 284         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 285             !(evt & OHCI1394_busReset))
 286                 return;
 287
 288         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 289             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 290             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 291             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 292             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 293             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 294             evt & OHCI1394_isochRx              ? " IR"                 : "",
 295             evt & OHCI1394_isochTx              ? " IT"                 : "",
 296             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 297             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 298             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 299             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 300             evt & OHCI1394_busReset             ? " busReset"           : "",
 301             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 302                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 303                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 304                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 305                     OHCI1394_cycleTooLong | OHCI1394_cycleInconsistent |
 306                     OHCI1394_regAccessFail | OHCI1394_busReset)
 307                                                 ? " ?"                  : "");
 308 }
 309
 310 static const char *speed[] = {
 311         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 312 };
 313 static const char *power[] = {
 314         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 315         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 316 };
 317 static const char port[] = { '.', '-', 'p', 'c', };
 318
 319 static char _p(u32 *s, int shift)
 320 {
 321         return port[*s >> shift & 3];
 322 }
 323
 324 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 325 {
 326         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 327                 return;
 328
 329         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 330                   self_id_count, generation, node_id);
 331
 332         for (; self_id_count--; ++s)
 333                 if ((*s & 1 << 23) == 0)
 334                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 335                             "%s gc=%d %s %s%s%s\n",
 336                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 337                             speed[*s >> 14 & 3], *s >> 16 & 63,
 338                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 339                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 340                 else
 341                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 342                             *s, *s >> 24 & 63,
 343                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 344                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 345 }
 346
 347 static const char *evts[] = {
 348         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 349         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 350         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 351         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 352         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 353         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 354         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 355         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 356         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 357         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 358         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 359         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 360         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 361         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 362         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 363         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 364         [0x20] = "pending/cancelled",
 365 };
 366 static const char *tcodes[] = {
 367         [0x0] = "QW req",               [0x1] = "BW req",
 368         [0x2] = "W resp",               [0x3] = "-reserved-",
 369         [0x4] = "QR req",               [0x5] = "BR req",
 370         [0x6] = "QR resp",              [0x7] = "BR resp",
 371         [0x8] = "cycle start",          [0x9] = "Lk req",
 372         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 373         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 374         [0xe] = "link internal",        [0xf] = "-reserved-",
 375 };
 376 static const char *phys[] = {
 377         [0x0] = "phy config packet",    [0x1] = "link-on packet",
 378         [0x2] = "self-id packet",       [0x3] = "-reserved-",
 379 };
 380
 381 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 382 {
 383         int tcode = header[0] >> 4 & 0xf;
 384         char specific[12];
 385
 386         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 387                 return;
 388
 389         if (unlikely(evt >= ARRAY_SIZE(evts)))
 390                         evt = 0x1f;
 391
 392         if (evt == OHCI1394_evt_bus_reset) {
 393                 fw_notify("A%c evt_bus_reset, generation %d\n",
 394                     dir, (header[2] >> 16) & 0xff);
 395                 return;
 396         }
 397
 398         if (header[0] == ~header[1]) {
 399                 fw_notify("A%c %s, %s, %08x\n",
 400                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
 401                 return;
 402         }
 403
 404         switch (tcode) {
 405         case 0x0: case 0x6: case 0x8:
 406                 snprintf(specific, sizeof(specific), " = %08x",
 407                          be32_to_cpu((__force __be32)header[3]));
 408                 break;
 409         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 410                 snprintf(specific, sizeof(specific), " %x,%x",
 411                          header[3] >> 16, header[3] & 0xffff);
 412                 break;
 413         default:
 414                 specific[0] = '\0';
 415         }
 416
 417         switch (tcode) {
 418         case 0xe: case 0xa:
 419                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 420                 break;
 421         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 422                 fw_notify("A%c spd %x tl %02x, "
 423                     "%04x -> %04x, %s, "
 424                     "%s, %04x%08x%s\n",
 425                     dir, speed, header[0] >> 10 & 0x3f,
 426                     header[1] >> 16, header[0] >> 16, evts[evt],
 427                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 428                 break;
 429         default:
 430                 fw_notify("A%c spd %x tl %02x, "
 431                     "%04x -> %04x, %s, "
 432                     "%s%s\n",
 433                     dir, speed, header[0] >> 10 & 0x3f,
 434                     header[1] >> 16, header[0] >> 16, evts[evt],
 435                     tcodes[tcode], specific);
 436         }
 437 }
 438
 439 #else
 440
 441 #define log_irqs(evt)
 442 #define log_selfids(node_id, generation, self_id_count, sid)
 443 #define log_ar_at_event(dir, speed, header, evt)
 444
 445 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 446
 447 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 448 {
 449         writel(data, ohci->registers + offset);
 450 }
 451
 452 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 453 {
 454         return readl(ohci->registers + offset);
 455 }
 456
 457 static inline void flush_writes(const struct fw_ohci *ohci)
 458 {
 459         /* Do a dummy read to flush writes. */
 460         reg_read(ohci, OHCI1394_Version);
 461 }
 462
 463 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 464                                int clear_bits, int set_bits)
 465 {
 466         struct fw_ohci *ohci = fw_ohci(card);
 467         u32 val, old;
 468
 469         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 470         flush_writes(ohci);
 471         msleep(2);
 472         val = reg_read(ohci, OHCI1394_PhyControl);
 473         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 474                 fw_error("failed to set phy reg bits.\n");
 475                 return -EBUSY;
 476         }
 477
 478         old = OHCI1394_PhyControl_ReadData(val);
 479         old = (old & ~clear_bits) | set_bits;
 480         reg_write(ohci, OHCI1394_PhyControl,
 481                   OHCI1394_PhyControl_Write(addr, old));
 482
 483         return 0;
 484 }
 485
 486 static int ar_context_add_page(struct ar_context *ctx)
 487 {
 488         struct device *dev = ctx->ohci->card.device;
 489         struct ar_buffer *ab;
 490         dma_addr_t uninitialized_var(ab_bus);
 491         size_t offset;
 492
 493         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
 494         if (ab == NULL)
 495                 return -ENOMEM;
 496
 497         ab->next = NULL;
 498         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 499         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 500                                                     DESCRIPTOR_STATUS |
 501                                                     DESCRIPTOR_BRANCH_ALWAYS);
 502         offset = offsetof(struct ar_buffer, data);
 503         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 504         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 505         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 506         ab->descriptor.branch_address = 0;
 507
 508         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 509         ctx->last_buffer->next = ab;
 510         ctx->last_buffer = ab;
 511
 512         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 513         flush_writes(ctx->ohci);
 514
 515         return 0;
 516 }
 517
 518 static void ar_context_release(struct ar_context *ctx)
 519 {
 520         struct ar_buffer *ab, *ab_next;
 521         size_t offset;
 522         dma_addr_t ab_bus;
 523
 524         for (ab = ctx->current_buffer; ab; ab = ab_next) {
 525                 ab_next = ab->next;
 526                 offset = offsetof(struct ar_buffer, data);
 527                 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 528                 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
 529                                   ab, ab_bus);
 530         }
 531 }
 532
 533 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 534 #define cond_le32_to_cpu(v) \
 535         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 536 #else
 537 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 538 #endif
 539
 540 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 541 {
 542         struct fw_ohci *ohci = ctx->ohci;
 543         struct fw_packet p;
 544         u32 status, length, tcode;
 545         int evt;
 546
 547         p.header[0] = cond_le32_to_cpu(buffer[0]);
 548         p.header[1] = cond_le32_to_cpu(buffer[1]);
 549         p.header[2] = cond_le32_to_cpu(buffer[2]);
 550
 551         tcode = (p.header[0] >> 4) & 0x0f;
 552         switch (tcode) {
 553         case TCODE_WRITE_QUADLET_REQUEST:
 554         case TCODE_READ_QUADLET_RESPONSE:
 555                 p.header[3] = (__force __u32) buffer[3];
 556                 p.header_length = 16;
 557                 p.payload_length = 0;
 558                 break;
 559
 560         case TCODE_READ_BLOCK_REQUEST :
 561                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 562                 p.header_length = 16;
 563                 p.payload_length = 0;
 564                 break;
 565
 566         case TCODE_WRITE_BLOCK_REQUEST:
 567         case TCODE_READ_BLOCK_RESPONSE:
 568         case TCODE_LOCK_REQUEST:
 569         case TCODE_LOCK_RESPONSE:
 570                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 571                 p.header_length = 16;
 572                 p.payload_length = p.header[3] >> 16;
 573                 break;
 574
 575         case TCODE_WRITE_RESPONSE:
 576         case TCODE_READ_QUADLET_REQUEST:
 577         case OHCI_TCODE_PHY_PACKET:
 578                 p.header_length = 12;
 579                 p.payload_length = 0;
 580                 break;
 581
 582         default:
 583                 /* FIXME: Stop context, discard everything, and restart? */
 584                 p.header_length = 0;
 585                 p.payload_length = 0;
 586         }
 587
 588         p.payload = (void *) buffer + p.header_length;
 589
 590         /* FIXME: What to do about evt_* errors? */
 591         length = (p.header_length + p.payload_length + 3) / 4;
 592         status = cond_le32_to_cpu(buffer[length]);
 593         evt    = (status >> 16) & 0x1f;
 594
 595         p.ack        = evt - 16;
 596         p.speed      = (status >> 21) & 0x7;
 597         p.timestamp  = status & 0xffff;
 598         p.generation = ohci->request_generation;
 599
 600         log_ar_at_event('R', p.speed, p.header, evt);
 601
 602         /*
 603          * The OHCI bus reset handler synthesizes a phy packet with
 604          * the new generation number when a bus reset happens (see
 605          * section 8.4.2.3).  This helps us determine when a request
 606          * was received and make sure we send the response in the same
 607          * generation.  We only need this for requests; for responses
 608          * we use the unique tlabel for finding the matching
 609          * request.
 610          *
 611          * Alas some chips sometimes emit bus reset packets with a
 612          * wrong generation.  We set the correct generation for these
 613          * at a slightly incorrect time (in bus_reset_tasklet).
 614          */
 615         if (evt == OHCI1394_evt_bus_reset) {
 616                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 617                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 618         } else if (ctx == &ohci->ar_request_ctx) {
 619                 fw_core_handle_request(&ohci->card, &p);
 620         } else {
 621                 fw_core_handle_response(&ohci->card, &p);
 622         }
 623
 624         return buffer + length + 1;
 625 }
 626
 627 static void ar_context_tasklet(unsigned long data)
 628 {
 629         struct ar_context *ctx = (struct ar_context *)data;
 630         struct fw_ohci *ohci = ctx->ohci;
 631         struct ar_buffer *ab;
 632         struct descriptor *d;
 633         void *buffer, *end;
 634
 635         ab = ctx->current_buffer;
 636         d = &ab->descriptor;
 637
 638         if (d->res_count == 0) {
 639                 size_t size, rest, offset;
 640                 dma_addr_t start_bus;
 641                 void *start;
 642
 643                 /*
 644                  * This descriptor is finished and we may have a
 645                  * packet split across this and the next buffer. We
 646                  * reuse the page for reassembling the split packet.
 647                  */
 648
 649                 offset = offsetof(struct ar_buffer, data);
 650                 start = buffer = ab;
 651                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 652
 653                 ab = ab->next;
 654                 d = &ab->descriptor;
 655                 size = buffer + PAGE_SIZE - ctx->pointer;
 656                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 657                 memmove(buffer, ctx->pointer, size);
 658                 memcpy(buffer + size, ab->data, rest);
 659                 ctx->current_buffer = ab;
 660                 ctx->pointer = (void *) ab->data + rest;
 661                 end = buffer + size + rest;
 662
 663                 while (buffer < end)
 664                         buffer = handle_ar_packet(ctx, buffer);
 665
 666                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
 667                                   start, start_bus);
 668                 ar_context_add_page(ctx);
 669         } else {
 670                 buffer = ctx->pointer;
 671                 ctx->pointer = end =
 672                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 673
 674                 while (buffer < end)
 675                         buffer = handle_ar_packet(ctx, buffer);
 676         }
 677 }
 678
 679 static int ar_context_init(struct ar_context *ctx,
 680                            struct fw_ohci *ohci, u32 regs)
 681 {
 682         struct ar_buffer ab;
 683
 684         ctx->regs        = regs;
 685         ctx->ohci        = ohci;
 686         ctx->last_buffer = &ab;
 687         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 688
 689         ar_context_add_page(ctx);
 690         ar_context_add_page(ctx);
 691         ctx->current_buffer = ab.next;
 692         ctx->pointer = ctx->current_buffer->data;
 693
 694         return 0;
 695 }
 696
 697 static void ar_context_run(struct ar_context *ctx)
 698 {
 699         struct ar_buffer *ab = ctx->current_buffer;
 700         dma_addr_t ab_bus;
 701         size_t offset;
 702
 703         offset = offsetof(struct ar_buffer, data);
 704         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 705
 706         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 707         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 708         flush_writes(ctx->ohci);
 709 }
 710
 711 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
 712 {
 713         int b, key;
 714
 715         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
 716         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
 717
 718         /* figure out which descriptor the branch address goes in */
 719         if (z == 2 && (b == 3 || key == 2))
 720                 return d;
 721         else
 722                 return d + z - 1;
 723 }
 724
 725 static void context_tasklet(unsigned long data)
 726 {
 727         struct context *ctx = (struct context *) data;
 728         struct descriptor *d, *last;
 729         u32 address;
 730         int z;
 731         struct descriptor_buffer *desc;
 732
 733         desc = list_entry(ctx->buffer_list.next,
 734                         struct descriptor_buffer, list);
 735         last = ctx->last;
 736         while (last->branch_address != 0) {
 737                 struct descriptor_buffer *old_desc = desc;
 738                 address = le32_to_cpu(last->branch_address);
 739                 z = address & 0xf;
 740                 address &= ~0xf;
 741
 742                 /* If the branch address points to a buffer outside of the
 743                  * current buffer, advance to the next buffer. */
 744                 if (address < desc->buffer_bus ||
 745                                 address >= desc->buffer_bus + desc->used)
 746                         desc = list_entry(desc->list.next,
 747                                         struct descriptor_buffer, list);
 748                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
 749                 last = find_branch_descriptor(d, z);
 750
 751                 if (!ctx->callback(ctx, d, last))
 752                         break;
 753
 754                 if (old_desc != desc) {
 755                         /* If we've advanced to the next buffer, move the
 756                          * previous buffer to the free list. */
 757                         unsigned long flags;
 758                         old_desc->used = 0;
 759                         spin_lock_irqsave(&ctx->ohci->lock, flags);
 760                         list_move_tail(&old_desc->list, &ctx->buffer_list);
 761                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 762                 }
 763                 ctx->last = last;
 764         }
 765 }
 766
 767 /*
 768  * Allocate a new buffer and add it to the list of free buffers for this
 769  * context.  Must be called with ohci->lock held.
 770  */
 771 static int context_add_buffer(struct context *ctx)
 772 {
 773         struct descriptor_buffer *desc;
 774         dma_addr_t uninitialized_var(bus_addr);
 775         int offset;
 776
 777         /*
 778          * 16MB of descriptors should be far more than enough for any DMA
 779          * program.  This will catch run-away userspace or DoS attacks.
 780          */
 781         if (ctx->total_allocation >= 16*1024*1024)
 782                 return -ENOMEM;
 783
 784         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
 785                         &bus_addr, GFP_ATOMIC);
 786         if (!desc)
 787                 return -ENOMEM;
 788
 789         offset = (void *)&desc->buffer - (void *)desc;
 790         desc->buffer_size = PAGE_SIZE - offset;
 791         desc->buffer_bus = bus_addr + offset;
 792         desc->used = 0;
 793
 794         list_add_tail(&desc->list, &ctx->buffer_list);
 795         ctx->total_allocation += PAGE_SIZE;
 796
 797         return 0;
 798 }
 799
 800 static int context_init(struct context *ctx, struct fw_ohci *ohci,
 801                         u32 regs, descriptor_callback_t callback)
 802 {
 803         ctx->ohci = ohci;
 804         ctx->regs = regs;
 805         ctx->total_allocation = 0;
 806
 807         INIT_LIST_HEAD(&ctx->buffer_list);
 808         if (context_add_buffer(ctx) < 0)
 809                 return -ENOMEM;
 810
 811         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
 812                         struct descriptor_buffer, list);
 813
 814         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 815         ctx->callback = callback;
 816
 817         /*
 818          * We put a dummy descriptor in the buffer that has a NULL
 819          * branch address and looks like it's been sent.  That way we
 820          * have a descriptor to append DMA programs to.
 821          */
 822         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
 823         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 824         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
 825         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
 826         ctx->last = ctx->buffer_tail->buffer;
 827         ctx->prev = ctx->buffer_tail->buffer;
 828
 829         return 0;
 830 }
 831
 832 static void context_release(struct context *ctx)
 833 {
 834         struct fw_card *card = &ctx->ohci->card;
 835         struct descriptor_buffer *desc, *tmp;
 836
 837         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
 838                 dma_free_coherent(card->device, PAGE_SIZE, desc,
 839                         desc->buffer_bus -
 840                         ((void *)&desc->buffer - (void *)desc));
 841 }
 842
 843 /* Must be called with ohci->lock held */
 844 static struct descriptor *context_get_descriptors(struct context *ctx,
 845                                                   int z, dma_addr_t *d_bus)
 846 {
 847         struct descriptor *d = NULL;
 848         struct descriptor_buffer *desc = ctx->buffer_tail;
 849
 850         if (z * sizeof(*d) > desc->buffer_size)
 851                 return NULL;
 852
 853         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
 854                 /* No room for the descriptor in this buffer, so advance to the
 855                  * next one. */
 856
 857                 if (desc->list.next == &ctx->buffer_list) {
 858                         /* If there is no free buffer next in the list,
 859                          * allocate one. */
 860                         if (context_add_buffer(ctx) < 0)
 861                                 return NULL;
 862                 }
 863                 desc = list_entry(desc->list.next,
 864                                 struct descriptor_buffer, list);
 865                 ctx->buffer_tail = desc;
 866         }
 867
 868         d = desc->buffer + desc->used / sizeof(*d);
 869         memset(d, 0, z * sizeof(*d));
 870         *d_bus = desc->buffer_bus + desc->used;
 871
 872         return d;
 873 }
 874
 875 static void context_run(struct context *ctx, u32 extra)
 876 {
 877         struct fw_ohci *ohci = ctx->ohci;
 878
 879         reg_write(ohci, COMMAND_PTR(ctx->regs),
 880                   le32_to_cpu(ctx->last->branch_address));
 881         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 882         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 883         flush_writes(ohci);
 884 }
 885
 886 static void context_append(struct context *ctx,
 887                            struct descriptor *d, int z, int extra)
 888 {
 889         dma_addr_t d_bus;
 890         struct descriptor_buffer *desc = ctx->buffer_tail;
 891
 892         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
 893
 894         desc->used += (z + extra) * sizeof(*d);
 895         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
 896         ctx->prev = find_branch_descriptor(d, z);
 897
 898         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 899         flush_writes(ctx->ohci);
 900 }
 901
 902 static void context_stop(struct context *ctx)
 903 {
 904         u32 reg;
 905         int i;
 906
 907         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 908         flush_writes(ctx->ohci);
 909
 910         for (i = 0; i < 10; i++) {
 911                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 912                 if ((reg & CONTEXT_ACTIVE) == 0)
 913                         return;
 914
 915                 mdelay(1);
 916         }
 917         fw_error("Error: DMA context still active (0x%08x)\n", reg);
 918 }
 919
 920 struct driver_data {
 921         struct fw_packet *packet;
 922 };
 923
 924 /*
 925  * This function apppends a packet to the DMA queue for transmission.
 926  * Must always be called with the ochi->lock held to ensure proper
 927  * generation handling and locking around packet queue manipulation.
 928  */
 929 static int at_context_queue_packet(struct context *ctx,
 930                                    struct fw_packet *packet)
 931 {
 932         struct fw_ohci *ohci = ctx->ohci;
 933         dma_addr_t d_bus, uninitialized_var(payload_bus);
 934         struct driver_data *driver_data;
 935         struct descriptor *d, *last;
 936         __le32 *header;
 937         int z, tcode;
 938         u32 reg;
 939
 940         d = context_get_descriptors(ctx, 4, &d_bus);
 941         if (d == NULL) {
 942                 packet->ack = RCODE_SEND_ERROR;
 943                 return -1;
 944         }
 945
 946         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 947         d[0].res_count = cpu_to_le16(packet->timestamp);
 948
 949         /*
 950          * The DMA format for asyncronous link packets is different
 951          * from the IEEE1394 layout, so shift the fields around
 952          * accordingly.  If header_length is 8, it's a PHY packet, to
 953          * which we need to prepend an extra quadlet.
 954          */
 955
 956         header = (__le32 *) &d[1];
 957         switch (packet->header_length) {
 958         case 16:
 959         case 12:
 960                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 961                                         (packet->speed << 16));
 962                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 963                                         (packet->header[0] & 0xffff0000));
 964                 header[2] = cpu_to_le32(packet->header[2]);
 965
 966                 tcode = (packet->header[0] >> 4) & 0x0f;
 967                 if (TCODE_IS_BLOCK_PACKET(tcode))
 968                         header[3] = cpu_to_le32(packet->header[3]);
 969                 else
 970                         header[3] = (__force __le32) packet->header[3];
 971
 972                 d[0].req_count = cpu_to_le16(packet->header_length);
 973                 break;
 974
 975         case 8:
 976                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 977                                         (packet->speed << 16));
 978                 header[1] = cpu_to_le32(packet->header[0]);
 979                 header[2] = cpu_to_le32(packet->header[1]);
 980                 d[0].req_count = cpu_to_le16(12);
 981                 break;
 982
 983         case 4:
 984                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 985                                         (packet->speed << 16));
 986                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
 987                 d[0].req_count = cpu_to_le16(8);
 988                 break;
 989
 990         default:
 991                 /* BUG(); */
 992                 packet->ack = RCODE_SEND_ERROR;
 993                 return -1;
 994         }
 995
 996         driver_data = (struct driver_data *) &d[3];
 997         driver_data->packet = packet;
 998         packet->driver_data = driver_data;
 999
1000         if (packet->payload_length > 0) {
1001                 payload_bus =
1002                         dma_map_single(ohci->card.device, packet->payload,
1003                                        packet->payload_length, DMA_TO_DEVICE);
1004                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1005                         packet->ack = RCODE_SEND_ERROR;
1006                         return -1;
1007                 }
1008                 packet->payload_bus     = payload_bus;
1009                 packet->payload_mapped  = true;
1010
1011                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1012                 d[2].data_address = cpu_to_le32(payload_bus);
1013                 last = &d[2];
1014                 z = 3;
1015         } else {
1016                 last = &d[0];
1017                 z = 2;
1018         }
1019
1020         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1021                                      DESCRIPTOR_IRQ_ALWAYS |
1022                                      DESCRIPTOR_BRANCH_ALWAYS);
1023
1024         /*
1025          * If the controller and packet generations don't match, we need to
1026          * bail out and try again.  If IntEvent.busReset is set, the AT context
1027          * is halted, so appending to the context and trying to run it is
1028          * futile.  Most controllers do the right thing and just flush the AT
1029          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1030          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1031          * up stalling out.  So we just bail out in software and try again
1032          * later, and everyone is happy.
1033          * FIXME: Document how the locking works.
1034          */
1035         if (ohci->generation != packet->generation ||
1036             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1037                 if (packet->payload_mapped)
1038                         dma_unmap_single(ohci->card.device, payload_bus,
1039                                          packet->payload_length, DMA_TO_DEVICE);
1040                 packet->ack = RCODE_GENERATION;
1041                 return -1;
1042         }
1043
1044         context_append(ctx, d, z, 4 - z);
1045
1046         /* If the context isn't already running, start it up. */
1047         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1048         if ((reg & CONTEXT_RUN) == 0)
1049                 context_run(ctx, 0);
1050
1051         return 0;
1052 }
1053
1054 static int handle_at_packet(struct context *context,
1055                             struct descriptor *d,
1056                             struct descriptor *last)
1057 {
1058         struct driver_data *driver_data;
1059         struct fw_packet *packet;
1060         struct fw_ohci *ohci = context->ohci;
1061         int evt;
1062
1063         if (last->transfer_status == 0)
1064                 /* This descriptor isn't done yet, stop iteration. */
1065                 return 0;
1066
1067         driver_data = (struct driver_data *) &d[3];
1068         packet = driver_data->packet;
1069         if (packet == NULL)
1070                 /* This packet was cancelled, just continue. */
1071                 return 1;
1072
1073         if (packet->payload_mapped)
1074                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1075                                  packet->payload_length, DMA_TO_DEVICE);
1076
1077         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1078         packet->timestamp = le16_to_cpu(last->res_count);
1079
1080         log_ar_at_event('T', packet->speed, packet->header, evt);
1081
1082         switch (evt) {
1083         case OHCI1394_evt_timeout:
1084                 /* Async response transmit timed out. */
1085                 packet->ack = RCODE_CANCELLED;
1086                 break;
1087
1088         case OHCI1394_evt_flushed:
1089                 /*
1090                  * The packet was flushed should give same error as
1091                  * when we try to use a stale generation count.
1092                  */
1093                 packet->ack = RCODE_GENERATION;
1094                 break;
1095
1096         case OHCI1394_evt_missing_ack:
1097                 /*
1098                  * Using a valid (current) generation count, but the
1099                  * node is not on the bus or not sending acks.
1100                  */
1101                 packet->ack = RCODE_NO_ACK;
1102                 break;
1103
1104         case ACK_COMPLETE + 0x10:
1105         case ACK_PENDING + 0x10:
1106         case ACK_BUSY_X + 0x10:
1107         case ACK_BUSY_A + 0x10:
1108         case ACK_BUSY_B + 0x10:
1109         case ACK_DATA_ERROR + 0x10:
1110         case ACK_TYPE_ERROR + 0x10:
1111                 packet->ack = evt - 0x10;
1112                 break;
1113
1114         default:
1115                 packet->ack = RCODE_SEND_ERROR;
1116                 break;
1117         }
1118
1119         packet->callback(packet, &ohci->card, packet->ack);
1120
1121         return 1;
1122 }
1123
1124 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1125 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1126 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1127 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1128 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1129
1130 static void handle_local_rom(struct fw_ohci *ohci,
1131                              struct fw_packet *packet, u32 csr)
1132 {
1133         struct fw_packet response;
1134         int tcode, length, i;
1135
1136         tcode = HEADER_GET_TCODE(packet->header[0]);
1137         if (TCODE_IS_BLOCK_PACKET(tcode))
1138                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1139         else
1140                 length = 4;
1141
1142         i = csr - CSR_CONFIG_ROM;
1143         if (i + length > CONFIG_ROM_SIZE) {
1144                 fw_fill_response(&response, packet->header,
1145                                  RCODE_ADDRESS_ERROR, NULL, 0);
1146         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1147                 fw_fill_response(&response, packet->header,
1148                                  RCODE_TYPE_ERROR, NULL, 0);
1149         } else {
1150                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1151                                  (void *) ohci->config_rom + i, length);
1152         }
1153
1154         fw_core_handle_response(&ohci->card, &response);
1155 }
1156
1157 static void handle_local_lock(struct fw_ohci *ohci,
1158                               struct fw_packet *packet, u32 csr)
1159 {
1160         struct fw_packet response;
1161         int tcode, length, ext_tcode, sel, try;
1162         __be32 *payload, lock_old;
1163         u32 lock_arg, lock_data;
1164
1165         tcode = HEADER_GET_TCODE(packet->header[0]);
1166         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1167         payload = packet->payload;
1168         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1169
1170         if (tcode == TCODE_LOCK_REQUEST &&
1171             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1172                 lock_arg = be32_to_cpu(payload[0]);
1173                 lock_data = be32_to_cpu(payload[1]);
1174         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1175                 lock_arg = 0;
1176                 lock_data = 0;
1177         } else {
1178                 fw_fill_response(&response, packet->header,
1179                                  RCODE_TYPE_ERROR, NULL, 0);
1180                 goto out;
1181         }
1182
1183         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1184         reg_write(ohci, OHCI1394_CSRData, lock_data);
1185         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1186         reg_write(ohci, OHCI1394_CSRControl, sel);
1187
1188         for (try = 0; try < 20; try++)
1189                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1190                         lock_old = cpu_to_be32(reg_read(ohci,
1191                                                         OHCI1394_CSRData));
1192                         fw_fill_response(&response, packet->header,
1193                                          RCODE_COMPLETE,
1194                                          &lock_old, sizeof(lock_old));
1195                         goto out;
1196                 }
1197
1198         fw_error("swap not done (CSR lock timeout)\n");
1199         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1200
1201  out:
1202         fw_core_handle_response(&ohci->card, &response);
1203 }
1204
1205 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1206 {
1207         u64 offset, csr;
1208
1209         if (ctx == &ctx->ohci->at_request_ctx) {
1210                 packet->ack = ACK_PENDING;
1211                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1212         }
1213
1214         offset =
1215                 ((unsigned long long)
1216                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1217                 packet->header[2];
1218         csr = offset - CSR_REGISTER_BASE;
1219
1220         /* Handle config rom reads. */
1221         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1222                 handle_local_rom(ctx->ohci, packet, csr);
1223         else switch (csr) {
1224         case CSR_BUS_MANAGER_ID:
1225         case CSR_BANDWIDTH_AVAILABLE:
1226         case CSR_CHANNELS_AVAILABLE_HI:
1227         case CSR_CHANNELS_AVAILABLE_LO:
1228                 handle_local_lock(ctx->ohci, packet, csr);
1229                 break;
1230         default:
1231                 if (ctx == &ctx->ohci->at_request_ctx)
1232                         fw_core_handle_request(&ctx->ohci->card, packet);
1233                 else
1234                         fw_core_handle_response(&ctx->ohci->card, packet);
1235                 break;
1236         }
1237
1238         if (ctx == &ctx->ohci->at_response_ctx) {
1239                 packet->ack = ACK_COMPLETE;
1240                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1241         }
1242 }
1243
1244 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1245 {
1246         unsigned long flags;
1247         int ret;
1248
1249         spin_lock_irqsave(&ctx->ohci->lock, flags);
1250
1251         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1252             ctx->ohci->generation == packet->generation) {
1253                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1254                 handle_local_request(ctx, packet);
1255                 return;
1256         }
1257
1258         ret = at_context_queue_packet(ctx, packet);
1259         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1260
1261         if (ret < 0)
1262                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1263
1264 }
1265
1266 static void bus_reset_tasklet(unsigned long data)
1267 {
1268         struct fw_ohci *ohci = (struct fw_ohci *)data;
1269         int self_id_count, i, j, reg;
1270         int generation, new_generation;
1271         unsigned long flags;
1272         void *free_rom = NULL;
1273         dma_addr_t free_rom_bus = 0;
1274
1275         reg = reg_read(ohci, OHCI1394_NodeID);
1276         if (!(reg & OHCI1394_NodeID_idValid)) {
1277                 fw_notify("node ID not valid, new bus reset in progress\n");
1278                 return;
1279         }
1280         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1281                 fw_notify("malconfigured bus\n");
1282                 return;
1283         }
1284         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1285                                OHCI1394_NodeID_nodeNumber);
1286
1287         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1288         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1289                 fw_notify("inconsistent self IDs\n");
1290                 return;
1291         }
1292         /*
1293          * The count in the SelfIDCount register is the number of
1294          * bytes in the self ID receive buffer.  Since we also receive
1295          * the inverted quadlets and a header quadlet, we shift one
1296          * bit extra to get the actual number of self IDs.
1297          */
1298         self_id_count = (reg >> 3) & 0xff;
1299         if (self_id_count == 0 || self_id_count > 252) {
1300                 fw_notify("inconsistent self IDs\n");
1301                 return;
1302         }
1303         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1304         rmb();
1305
1306         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1307                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1308                         fw_notify("inconsistent self IDs\n");
1309                         return;
1310                 }
1311                 ohci->self_id_buffer[j] =
1312                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1313         }
1314         rmb();
1315
1316         /*
1317          * Check the consistency of the self IDs we just read.  The
1318          * problem we face is that a new bus reset can start while we
1319          * read out the self IDs from the DMA buffer. If this happens,
1320          * the DMA buffer will be overwritten with new self IDs and we
1321          * will read out inconsistent data.  The OHCI specification
1322          * (section 11.2) recommends a technique similar to
1323          * linux/seqlock.h, where we remember the generation of the
1324          * self IDs in the buffer before reading them out and compare
1325          * it to the current generation after reading them out.  If
1326          * the two generations match we know we have a consistent set
1327          * of self IDs.
1328          */
1329
1330         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1331         if (new_generation != generation) {
1332                 fw_notify("recursive bus reset detected, "
1333                           "discarding self ids\n");
1334                 return;
1335         }
1336
1337         /* FIXME: Document how the locking works. */
1338         spin_lock_irqsave(&ohci->lock, flags);
1339
1340         ohci->generation = generation;
1341         context_stop(&ohci->at_request_ctx);
1342         context_stop(&ohci->at_response_ctx);
1343         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1344
1345         if (ohci->quirks & QUIRK_RESET_PACKET)
1346                 ohci->request_generation = generation;
1347
1348         /*
1349          * This next bit is unrelated to the AT context stuff but we
1350          * have to do it under the spinlock also.  If a new config rom
1351          * was set up before this reset, the old one is now no longer
1352          * in use and we can free it. Update the config rom pointers
1353          * to point to the current config rom and clear the
1354          * next_config_rom pointer so a new update can take place.
1355          */
1356
1357         if (ohci->next_config_rom != NULL) {
1358                 if (ohci->next_config_rom != ohci->config_rom) {
1359                         free_rom      = ohci->config_rom;
1360                         free_rom_bus  = ohci->config_rom_bus;
1361                 }
1362                 ohci->config_rom      = ohci->next_config_rom;
1363                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1364                 ohci->next_config_rom = NULL;
1365
1366                 /*
1367                  * Restore config_rom image and manually update
1368                  * config_rom registers.  Writing the header quadlet
1369                  * will indicate that the config rom is ready, so we
1370                  * do that last.
1371                  */
1372                 reg_write(ohci, OHCI1394_BusOptions,
1373                           be32_to_cpu(ohci->config_rom[2]));
1374                 ohci->config_rom[0] = ohci->next_header;
1375                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1376                           be32_to_cpu(ohci->next_header));
1377         }
1378
1379 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1380         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1381         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1382 #endif
1383
1384         spin_unlock_irqrestore(&ohci->lock, flags);
1385
1386         if (free_rom)
1387                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1388                                   free_rom, free_rom_bus);
1389
1390         log_selfids(ohci->node_id, generation,
1391                     self_id_count, ohci->self_id_buffer);
1392
1393         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1394                                  self_id_count, ohci->self_id_buffer);
1395 }
1396
1397 static irqreturn_t irq_handler(int irq, void *data)
1398 {
1399         struct fw_ohci *ohci = data;
1400         u32 event, iso_event;
1401         int i;
1402
1403         event = reg_read(ohci, OHCI1394_IntEventClear);
1404
1405         if (!event || !~event)
1406                 return IRQ_NONE;
1407
1408         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1409         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1410         log_irqs(event);
1411
1412         if (event & OHCI1394_selfIDComplete)
1413                 tasklet_schedule(&ohci->bus_reset_tasklet);
1414
1415         if (event & OHCI1394_RQPkt)
1416                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1417
1418         if (event & OHCI1394_RSPkt)
1419                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1420
1421         if (event & OHCI1394_reqTxComplete)
1422                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1423
1424         if (event & OHCI1394_respTxComplete)
1425                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1426
1427         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1428         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1429
1430         while (iso_event) {
1431                 i = ffs(iso_event) - 1;
1432                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1433                 iso_event &= ~(1 << i);
1434         }
1435
1436         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1437         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1438
1439         while (iso_event) {
1440                 i = ffs(iso_event) - 1;
1441                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1442                 iso_event &= ~(1 << i);
1443         }
1444
1445         if (unlikely(event & OHCI1394_regAccessFail))
1446                 fw_error("Register access failure - "
1447                          "please notify linux1394-devel@lists.sf.net\n");
1448
1449         if (unlikely(event & OHCI1394_postedWriteErr))
1450                 fw_error("PCI posted write error\n");
1451
1452         if (unlikely(event & OHCI1394_cycleTooLong)) {
1453                 if (printk_ratelimit())
1454                         fw_notify("isochronous cycle too long\n");
1455                 reg_write(ohci, OHCI1394_LinkControlSet,
1456                           OHCI1394_LinkControl_cycleMaster);
1457         }
1458
1459         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1460                 /*
1461                  * We need to clear this event bit in order to make
1462                  * cycleMatch isochronous I/O work.  In theory we should
1463                  * stop active cycleMatch iso contexts now and restart
1464                  * them at least two cycles later.  (FIXME?)
1465                  */
1466                 if (printk_ratelimit())
1467                         fw_notify("isochronous cycle inconsistent\n");
1468         }
1469
1470         return IRQ_HANDLED;
1471 }
1472
1473 static int software_reset(struct fw_ohci *ohci)
1474 {
1475         int i;
1476
1477         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1478
1479         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1480                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1481                      OHCI1394_HCControl_softReset) == 0)
1482                         return 0;
1483                 msleep(1);
1484         }
1485
1486         return -EBUSY;
1487 }
1488
1489 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1490 {
1491         size_t size = length * 4;
1492
1493         memcpy(dest, src, size);
1494         if (size < CONFIG_ROM_SIZE)
1495                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1496 }
1497
1498 static int ohci_enable(struct fw_card *card,
1499                        const __be32 *config_rom, size_t length)
1500 {
1501         struct fw_ohci *ohci = fw_ohci(card);
1502         struct pci_dev *dev = to_pci_dev(card->device);
1503         u32 lps;
1504         int i;
1505
1506         if (software_reset(ohci)) {
1507                 fw_error("Failed to reset ohci card.\n");
1508                 return -EBUSY;
1509         }
1510
1511         /*
1512          * Now enable LPS, which we need in order to start accessing
1513          * most of the registers.  In fact, on some cards (ALI M5251),
1514          * accessing registers in the SClk domain without LPS enabled
1515          * will lock up the machine.  Wait 50msec to make sure we have
1516          * full link enabled.  However, with some cards (well, at least
1517          * a JMicron PCIe card), we have to try again sometimes.
1518          */
1519         reg_write(ohci, OHCI1394_HCControlSet,
1520                   OHCI1394_HCControl_LPS |
1521                   OHCI1394_HCControl_postedWriteEnable);
1522         flush_writes(ohci);
1523
1524         for (lps = 0, i = 0; !lps && i < 3; i++) {
1525                 msleep(50);
1526                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1527                       OHCI1394_HCControl_LPS;
1528         }
1529
1530         if (!lps) {
1531                 fw_error("Failed to set Link Power Status\n");
1532                 return -EIO;
1533         }
1534
1535         reg_write(ohci, OHCI1394_HCControlClear,
1536                   OHCI1394_HCControl_noByteSwapData);
1537
1538         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1539         reg_write(ohci, OHCI1394_LinkControlClear,
1540                   OHCI1394_LinkControl_rcvPhyPkt);
1541         reg_write(ohci, OHCI1394_LinkControlSet,
1542                   OHCI1394_LinkControl_rcvSelfID |
1543                   OHCI1394_LinkControl_cycleTimerEnable |
1544                   OHCI1394_LinkControl_cycleMaster);
1545
1546         reg_write(ohci, OHCI1394_ATRetries,
1547                   OHCI1394_MAX_AT_REQ_RETRIES |
1548                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1549                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1550
1551         ar_context_run(&ohci->ar_request_ctx);
1552         ar_context_run(&ohci->ar_response_ctx);
1553
1554         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1555         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1556         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1557         reg_write(ohci, OHCI1394_IntMaskSet,
1558                   OHCI1394_selfIDComplete |
1559                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1560                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1561                   OHCI1394_isochRx | OHCI1394_isochTx |
1562                   OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1563                   OHCI1394_cycleInconsistent | OHCI1394_regAccessFail |
1564                   OHCI1394_masterIntEnable);
1565         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1566                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1567
1568         /* Activate link_on bit and contender bit in our self ID packets.*/
1569         if (ohci_update_phy_reg(card, 4, 0,
1570                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1571                 return -EIO;
1572
1573         /*
1574          * When the link is not yet enabled, the atomic config rom
1575          * update mechanism described below in ohci_set_config_rom()
1576          * is not active.  We have to update ConfigRomHeader and
1577          * BusOptions manually, and the write to ConfigROMmap takes
1578          * effect immediately.  We tie this to the enabling of the
1579          * link, so we have a valid config rom before enabling - the
1580          * OHCI requires that ConfigROMhdr and BusOptions have valid
1581          * values before enabling.
1582          *
1583          * However, when the ConfigROMmap is written, some controllers
1584          * always read back quadlets 0 and 2 from the config rom to
1585          * the ConfigRomHeader and BusOptions registers on bus reset.
1586          * They shouldn't do that in this initial case where the link
1587          * isn't enabled.  This means we have to use the same
1588          * workaround here, setting the bus header to 0 and then write
1589          * the right values in the bus reset tasklet.
1590          */
1591
1592         if (config_rom) {
1593                 ohci->next_config_rom =
1594                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1595                                            &ohci->next_config_rom_bus,
1596                                            GFP_KERNEL);
1597                 if (ohci->next_config_rom == NULL)
1598                         return -ENOMEM;
1599
1600                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1601         } else {
1602                 /*
1603                  * In the suspend case, config_rom is NULL, which
1604                  * means that we just reuse the old config rom.
1605                  */
1606                 ohci->next_config_rom = ohci->config_rom;
1607                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1608         }
1609
1610         ohci->next_header = ohci->next_config_rom[0];
1611         ohci->next_config_rom[0] = 0;
1612         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1613         reg_write(ohci, OHCI1394_BusOptions,
1614                   be32_to_cpu(ohci->next_config_rom[2]));
1615         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1616
1617         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1618
1619         if (request_irq(dev->irq, irq_handler,
1620                         IRQF_SHARED, ohci_driver_name, ohci)) {
1621                 fw_error("Failed to allocate shared interrupt %d.\n",
1622                          dev->irq);
1623                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1624                                   ohci->config_rom, ohci->config_rom_bus);
1625                 return -EIO;
1626         }
1627
1628         reg_write(ohci, OHCI1394_HCControlSet,
1629                   OHCI1394_HCControl_linkEnable |
1630                   OHCI1394_HCControl_BIBimageValid);
1631         flush_writes(ohci);
1632
1633         /*
1634          * We are ready to go, initiate bus reset to finish the
1635          * initialization.
1636          */
1637
1638         fw_core_initiate_bus_reset(&ohci->card, 1);
1639
1640         return 0;
1641 }
1642
1643 static int ohci_set_config_rom(struct fw_card *card,
1644                                const __be32 *config_rom, size_t length)
1645 {
1646         struct fw_ohci *ohci;
1647         unsigned long flags;
1648         int ret = -EBUSY;
1649         __be32 *next_config_rom;
1650         dma_addr_t uninitialized_var(next_config_rom_bus);
1651
1652         ohci = fw_ohci(card);
1653
1654         /*
1655          * When the OHCI controller is enabled, the config rom update
1656          * mechanism is a bit tricky, but easy enough to use.  See
1657          * section 5.5.6 in the OHCI specification.
1658          *
1659          * The OHCI controller caches the new config rom address in a
1660          * shadow register (ConfigROMmapNext) and needs a bus reset
1661          * for the changes to take place.  When the bus reset is
1662          * detected, the controller loads the new values for the
1663          * ConfigRomHeader and BusOptions registers from the specified
1664          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1665          * shadow register. All automatically and atomically.
1666          *
1667          * Now, there's a twist to this story.  The automatic load of
1668          * ConfigRomHeader and BusOptions doesn't honor the
1669          * noByteSwapData bit, so with a be32 config rom, the
1670          * controller will load be32 values in to these registers
1671          * during the atomic update, even on litte endian
1672          * architectures.  The workaround we use is to put a 0 in the
1673          * header quadlet; 0 is endian agnostic and means that the
1674          * config rom isn't ready yet.  In the bus reset tasklet we
1675          * then set up the real values for the two registers.
1676          *
1677          * We use ohci->lock to avoid racing with the code that sets
1678          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1679          */
1680
1681         next_config_rom =
1682                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1683                                    &next_config_rom_bus, GFP_KERNEL);
1684         if (next_config_rom == NULL)
1685                 return -ENOMEM;
1686
1687         spin_lock_irqsave(&ohci->lock, flags);
1688
1689         if (ohci->next_config_rom == NULL) {
1690                 ohci->next_config_rom = next_config_rom;
1691                 ohci->next_config_rom_bus = next_config_rom_bus;
1692
1693                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1694
1695                 ohci->next_header = config_rom[0];
1696                 ohci->next_config_rom[0] = 0;
1697
1698                 reg_write(ohci, OHCI1394_ConfigROMmap,
1699                           ohci->next_config_rom_bus);
1700                 ret = 0;
1701         }
1702
1703         spin_unlock_irqrestore(&ohci->lock, flags);
1704
1705         /*
1706          * Now initiate a bus reset to have the changes take
1707          * effect. We clean up the old config rom memory and DMA
1708          * mappings in the bus reset tasklet, since the OHCI
1709          * controller could need to access it before the bus reset
1710          * takes effect.
1711          */
1712         if (ret == 0)
1713                 fw_core_initiate_bus_reset(&ohci->card, 1);
1714         else
1715                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1716                                   next_config_rom, next_config_rom_bus);
1717
1718         return ret;
1719 }
1720
1721 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1722 {
1723         struct fw_ohci *ohci = fw_ohci(card);
1724
1725         at_context_transmit(&ohci->at_request_ctx, packet);
1726 }
1727
1728 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1729 {
1730         struct fw_ohci *ohci = fw_ohci(card);
1731
1732         at_context_transmit(&ohci->at_response_ctx, packet);
1733 }
1734
1735 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1736 {
1737         struct fw_ohci *ohci = fw_ohci(card);
1738         struct context *ctx = &ohci->at_request_ctx;
1739         struct driver_data *driver_data = packet->driver_data;
1740         int ret = -ENOENT;
1741
1742         tasklet_disable(&ctx->tasklet);
1743
1744         if (packet->ack != 0)
1745                 goto out;
1746
1747         if (packet->payload_mapped)
1748                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1749                                  packet->payload_length, DMA_TO_DEVICE);
1750
1751         log_ar_at_event('T', packet->speed, packet->header, 0x20);
1752         driver_data->packet = NULL;
1753         packet->ack = RCODE_CANCELLED;
1754         packet->callback(packet, &ohci->card, packet->ack);
1755         ret = 0;
1756  out:
1757         tasklet_enable(&ctx->tasklet);
1758
1759         return ret;
1760 }
1761
1762 static int ohci_enable_phys_dma(struct fw_card *card,
1763                                 int node_id, int generation)
1764 {
1765 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1766         return 0;
1767 #else
1768         struct fw_ohci *ohci = fw_ohci(card);
1769         unsigned long flags;
1770         int n, ret = 0;
1771
1772         /*
1773          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1774          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1775          */
1776
1777         spin_lock_irqsave(&ohci->lock, flags);
1778
1779         if (ohci->generation != generation) {
1780                 ret = -ESTALE;
1781                 goto out;
1782         }
1783
1784         /*
1785          * Note, if the node ID contains a non-local bus ID, physical DMA is
1786          * enabled for _all_ nodes on remote buses.
1787          */
1788
1789         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1790         if (n < 32)
1791                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1792         else
1793                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1794
1795         flush_writes(ohci);
1796  out:
1797         spin_unlock_irqrestore(&ohci->lock, flags);
1798
1799         return ret;
1800 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1801 }
1802
1803 static u32 cycle_timer_ticks(u32 cycle_timer)
1804 {
1805         u32 ticks;
1806
1807         ticks = cycle_timer & 0xfff;
1808         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1809         ticks += (3072 * 8000) * (cycle_timer >> 25);
1810
1811         return ticks;
1812 }
1813
1814 /*
1815  * Some controllers exhibit one or more of the following bugs when updating the
1816  * iso cycle timer register:
1817  *  - When the lowest six bits are wrapping around to zero, a read that happens
1818  *    at the same time will return garbage in the lowest ten bits.
1819  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1820  *    not incremented for about 60 ns.
1821  *  - Occasionally, the entire register reads zero.
1822  *
1823  * To catch these, we read the register three times and ensure that the
1824  * difference between each two consecutive reads is approximately the same, i.e.
1825  * less than twice the other.  Furthermore, any negative difference indicates an
1826  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1827  * execute, so we have enough precision to compute the ratio of the differences.)
1828  */
1829 static u32 ohci_get_cycle_time(struct fw_card *card)
1830 {
1831         struct fw_ohci *ohci = fw_ohci(card);
1832         u32 c0, c1, c2;
1833         u32 t0, t1, t2;
1834         s32 diff01, diff12;
1835         int i;
1836
1837         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1838
1839         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1840                 i = 0;
1841                 c1 = c2;
1842                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1843                 do {
1844                         c0 = c1;
1845                         c1 = c2;
1846                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1847                         t0 = cycle_timer_ticks(c0);
1848                         t1 = cycle_timer_ticks(c1);
1849                         t2 = cycle_timer_ticks(c2);
1850                         diff01 = t1 - t0;
1851                         diff12 = t2 - t1;
1852                 } while ((diff01 <= 0 || diff12 <= 0 ||
1853                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1854                          && i++ < 20);
1855         }
1856
1857         return c2;
1858 }
1859
1860 static void copy_iso_headers(struct iso_context *ctx, void *p)
1861 {
1862         int i = ctx->header_length;
1863
1864         if (i + ctx->base.header_size > PAGE_SIZE)
1865                 return;
1866
1867         /*
1868          * The iso header is byteswapped to little endian by
1869          * the controller, but the remaining header quadlets
1870          * are big endian.  We want to present all the headers
1871          * as big endian, so we have to swap the first quadlet.
1872          */
1873         if (ctx->base.header_size > 0)
1874                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1875         if (ctx->base.header_size > 4)
1876                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1877         if (ctx->base.header_size > 8)
1878                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1879         ctx->header_length += ctx->base.header_size;
1880 }
1881
1882 static int handle_ir_packet_per_buffer(struct context *context,
1883                                        struct descriptor *d,
1884                                        struct descriptor *last)
1885 {
1886         struct iso_context *ctx =
1887                 container_of(context, struct iso_context, context);
1888         struct descriptor *pd;
1889         __le32 *ir_header;
1890         void *p;
1891
1892         for (pd = d; pd <= last; pd++) {
1893                 if (pd->transfer_status)
1894                         break;
1895         }
1896         if (pd > last)
1897                 /* Descriptor(s) not done yet, stop iteration */
1898                 return 0;
1899
1900         p = last + 1;
1901         copy_iso_headers(ctx, p);
1902
1903         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1904                 ir_header = (__le32 *) p;
1905                 ctx->base.callback(&ctx->base,
1906                                    le32_to_cpu(ir_header[0]) & 0xffff,
1907                                    ctx->header_length, ctx->header,
1908                                    ctx->base.callback_data);
1909                 ctx->header_length = 0;
1910         }
1911
1912         return 1;
1913 }
1914
1915 static int handle_it_packet(struct context *context,
1916                             struct descriptor *d,
1917                             struct descriptor *last)
1918 {
1919         struct iso_context *ctx =
1920                 container_of(context, struct iso_context, context);
1921         int i;
1922         struct descriptor *pd;
1923
1924         for (pd = d; pd <= last; pd++)
1925                 if (pd->transfer_status)
1926                         break;
1927         if (pd > last)
1928                 /* Descriptor(s) not done yet, stop iteration */
1929                 return 0;
1930
1931         i = ctx->header_length;
1932         if (i + 4 < PAGE_SIZE) {
1933                 /* Present this value as big-endian to match the receive code */
1934                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
1935                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
1936                                 le16_to_cpu(pd->res_count));
1937                 ctx->header_length += 4;
1938         }
1939         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1940                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1941                                    ctx->header_length, ctx->header,
1942                                    ctx->base.callback_data);
1943                 ctx->header_length = 0;
1944         }
1945         return 1;
1946 }
1947
1948 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1949                                 int type, int channel, size_t header_size)
1950 {
1951         struct fw_ohci *ohci = fw_ohci(card);
1952         struct iso_context *ctx, *list;
1953         descriptor_callback_t callback;
1954         u64 *channels, dont_care = ~0ULL;
1955         u32 *mask, regs;
1956         unsigned long flags;
1957         int index, ret = -ENOMEM;
1958
1959         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1960                 channels = &dont_care;
1961                 mask = &ohci->it_context_mask;
1962                 list = ohci->it_context_list;
1963                 callback = handle_it_packet;
1964         } else {
1965                 channels = &ohci->ir_context_channels;
1966                 mask = &ohci->ir_context_mask;
1967                 list = ohci->ir_context_list;
1968                 callback = handle_ir_packet_per_buffer;
1969         }
1970
1971         spin_lock_irqsave(&ohci->lock, flags);
1972         index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1973         if (index >= 0) {
1974                 *channels &= ~(1ULL << channel);
1975                 *mask &= ~(1 << index);
1976         }
1977         spin_unlock_irqrestore(&ohci->lock, flags);
1978
1979         if (index < 0)
1980                 return ERR_PTR(-EBUSY);
1981
1982         if (type == FW_ISO_CONTEXT_TRANSMIT)
1983                 regs = OHCI1394_IsoXmitContextBase(index);
1984         else
1985                 regs = OHCI1394_IsoRcvContextBase(index);
1986
1987         ctx = &list[index];
1988         memset(ctx, 0, sizeof(*ctx));
1989         ctx->header_length = 0;
1990         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1991         if (ctx->header == NULL)
1992                 goto out;
1993
1994         ret = context_init(&ctx->context, ohci, regs, callback);
1995         if (ret < 0)
1996                 goto out_with_header;
1997
1998         return &ctx->base;
1999
2000  out_with_header:
2001         free_page((unsigned long)ctx->header);
2002  out:
2003         spin_lock_irqsave(&ohci->lock, flags);
2004         *mask |= 1 << index;
2005         spin_unlock_irqrestore(&ohci->lock, flags);
2006
2007         return ERR_PTR(ret);
2008 }
2009
2010 static int ohci_start_iso(struct fw_iso_context *base,
2011                           s32 cycle, u32 sync, u32 tags)
2012 {
2013         struct iso_context *ctx = container_of(base, struct iso_context, base);
2014         struct fw_ohci *ohci = ctx->context.ohci;
2015         u32 control, match;
2016         int index;
2017
2018         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2019                 index = ctx - ohci->it_context_list;
2020                 match = 0;
2021                 if (cycle >= 0)
2022                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2023                                 (cycle & 0x7fff) << 16;
2024
2025                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2026                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2027                 context_run(&ctx->context, match);
2028         } else {
2029                 index = ctx - ohci->ir_context_list;
2030                 control = IR_CONTEXT_ISOCH_HEADER;
2031                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2032                 if (cycle >= 0) {
2033                         match |= (cycle & 0x07fff) << 12;
2034                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2035                 }
2036
2037                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2038                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2039                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2040                 context_run(&ctx->context, control);
2041         }
2042
2043         return 0;
2044 }
2045
2046 static int ohci_stop_iso(struct fw_iso_context *base)
2047 {
2048         struct fw_ohci *ohci = fw_ohci(base->card);
2049         struct iso_context *ctx = container_of(base, struct iso_context, base);
2050         int index;
2051
2052         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2053                 index = ctx - ohci->it_context_list;
2054                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2055         } else {
2056                 index = ctx - ohci->ir_context_list;
2057                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2058         }
2059         flush_writes(ohci);
2060         context_stop(&ctx->context);
2061
2062         return 0;
2063 }
2064
2065 static void ohci_free_iso_context(struct fw_iso_context *base)
2066 {
2067         struct fw_ohci *ohci = fw_ohci(base->card);
2068         struct iso_context *ctx = container_of(base, struct iso_context, base);
2069         unsigned long flags;
2070         int index;
2071
2072         ohci_stop_iso(base);
2073         context_release(&ctx->context);
2074         free_page((unsigned long)ctx->header);
2075
2076         spin_lock_irqsave(&ohci->lock, flags);
2077
2078         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2079                 index = ctx - ohci->it_context_list;
2080                 ohci->it_context_mask |= 1 << index;
2081         } else {
2082                 index = ctx - ohci->ir_context_list;
2083                 ohci->ir_context_mask |= 1 << index;
2084                 ohci->ir_context_channels |= 1ULL << base->channel;
2085         }
2086
2087         spin_unlock_irqrestore(&ohci->lock, flags);
2088 }
2089
2090 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2091                                    struct fw_iso_packet *packet,
2092                                    struct fw_iso_buffer *buffer,
2093                                    unsigned long payload)
2094 {
2095         struct iso_context *ctx = container_of(base, struct iso_context, base);
2096         struct descriptor *d, *last, *pd;
2097         struct fw_iso_packet *p;
2098         __le32 *header;
2099         dma_addr_t d_bus, page_bus;
2100         u32 z, header_z, payload_z, irq;
2101         u32 payload_index, payload_end_index, next_page_index;
2102         int page, end_page, i, length, offset;
2103
2104         p = packet;
2105         payload_index = payload;
2106
2107         if (p->skip)
2108                 z = 1;
2109         else
2110                 z = 2;
2111         if (p->header_length > 0)
2112                 z++;
2113
2114         /* Determine the first page the payload isn't contained in. */
2115         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2116         if (p->payload_length > 0)
2117                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2118         else
2119                 payload_z = 0;
2120
2121         z += payload_z;
2122
2123         /* Get header size in number of descriptors. */
2124         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2125
2126         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2127         if (d == NULL)
2128                 return -ENOMEM;
2129
2130         if (!p->skip) {
2131                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2132                 d[0].req_count = cpu_to_le16(8);
2133                 /*
2134                  * Link the skip address to this descriptor itself.  This causes
2135                  * a context to skip a cycle whenever lost cycles or FIFO
2136                  * overruns occur, without dropping the data.  The application
2137                  * should then decide whether this is an error condition or not.
2138                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2139                  */
2140                 d[0].branch_address = cpu_to_le32(d_bus | z);
2141
2142                 header = (__le32 *) &d[1];
2143                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2144                                         IT_HEADER_TAG(p->tag) |
2145                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2146                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2147                                         IT_HEADER_SPEED(ctx->base.speed));
2148                 header[1] =
2149                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2150                                                           p->payload_length));
2151         }
2152
2153         if (p->header_length > 0) {
2154                 d[2].req_count    = cpu_to_le16(p->header_length);
2155                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2156                 memcpy(&d[z], p->header, p->header_length);
2157         }
2158
2159         pd = d + z - payload_z;
2160         payload_end_index = payload_index + p->payload_length;
2161         for (i = 0; i < payload_z; i++) {
2162                 page               = payload_index >> PAGE_SHIFT;
2163                 offset             = payload_index & ~PAGE_MASK;
2164                 next_page_index    = (page + 1) << PAGE_SHIFT;
2165                 length             =
2166                         min(next_page_index, payload_end_index) - payload_index;
2167                 pd[i].req_count    = cpu_to_le16(length);
2168
2169                 page_bus = page_private(buffer->pages[page]);
2170                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2171
2172                 payload_index += length;
2173         }
2174
2175         if (p->interrupt)
2176                 irq = DESCRIPTOR_IRQ_ALWAYS;
2177         else
2178                 irq = DESCRIPTOR_NO_IRQ;
2179
2180         last = z == 2 ? d : d + z - 1;
2181         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2182                                      DESCRIPTOR_STATUS |
2183                                      DESCRIPTOR_BRANCH_ALWAYS |
2184                                      irq);
2185
2186         context_append(&ctx->context, d, z, header_z);
2187
2188         return 0;
2189 }
2190
2191 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2192                                         struct fw_iso_packet *packet,
2193                                         struct fw_iso_buffer *buffer,
2194                                         unsigned long payload)
2195 {
2196         struct iso_context *ctx = container_of(base, struct iso_context, base);
2197         struct descriptor *d, *pd;
2198         struct fw_iso_packet *p = packet;
2199         dma_addr_t d_bus, page_bus;
2200         u32 z, header_z, rest;
2201         int i, j, length;
2202         int page, offset, packet_count, header_size, payload_per_buffer;
2203
2204         /*
2205          * The OHCI controller puts the isochronous header and trailer in the
2206          * buffer, so we need at least 8 bytes.
2207          */
2208         packet_count = p->header_length / ctx->base.header_size;
2209         header_size  = max(ctx->base.header_size, (size_t)8);
2210
2211         /* Get header size in number of descriptors. */
2212         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2213         page     = payload >> PAGE_SHIFT;
2214         offset   = payload & ~PAGE_MASK;
2215         payload_per_buffer = p->payload_length / packet_count;
2216
2217         for (i = 0; i < packet_count; i++) {
2218                 /* d points to the header descriptor */
2219                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2220                 d = context_get_descriptors(&ctx->context,
2221                                 z + header_z, &d_bus);
2222                 if (d == NULL)
2223                         return -ENOMEM;
2224
2225                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2226                                               DESCRIPTOR_INPUT_MORE);
2227                 if (p->skip && i == 0)
2228                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2229                 d->req_count    = cpu_to_le16(header_size);
2230                 d->res_count    = d->req_count;
2231                 d->transfer_status = 0;
2232                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2233
2234                 rest = payload_per_buffer;
2235                 pd = d;
2236                 for (j = 1; j < z; j++) {
2237                         pd++;
2238                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2239                                                   DESCRIPTOR_INPUT_MORE);
2240
2241                         if (offset + rest < PAGE_SIZE)
2242                                 length = rest;
2243                         else
2244                                 length = PAGE_SIZE - offset;
2245                         pd->req_count = cpu_to_le16(length);
2246                         pd->res_count = pd->req_count;
2247                         pd->transfer_status = 0;
2248
2249                         page_bus = page_private(buffer->pages[page]);
2250                         pd->data_address = cpu_to_le32(page_bus + offset);
2251
2252                         offset = (offset + length) & ~PAGE_MASK;
2253                         rest -= length;
2254                         if (offset == 0)
2255                                 page++;
2256                 }
2257                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2258                                           DESCRIPTOR_INPUT_LAST |
2259                                           DESCRIPTOR_BRANCH_ALWAYS);
2260                 if (p->interrupt && i == packet_count - 1)
2261                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2262
2263                 context_append(&ctx->context, d, z, header_z);
2264         }
2265
2266         return 0;
2267 }
2268
2269 static int ohci_queue_iso(struct fw_iso_context *base,
2270                           struct fw_iso_packet *packet,
2271                           struct fw_iso_buffer *buffer,
2272                           unsigned long payload)
2273 {
2274         struct iso_context *ctx = container_of(base, struct iso_context, base);
2275         unsigned long flags;
2276         int ret;
2277
2278         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2279         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2280                 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2281         else
2282                 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2283                                                         buffer, payload);
2284         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2285
2286         return ret;
2287 }
2288
2289 static const struct fw_card_driver ohci_driver = {
2290         .enable                 = ohci_enable,
2291         .update_phy_reg         = ohci_update_phy_reg,
2292         .set_config_rom         = ohci_set_config_rom,
2293         .send_request           = ohci_send_request,
2294         .send_response          = ohci_send_response,
2295         .cancel_packet          = ohci_cancel_packet,
2296         .enable_phys_dma        = ohci_enable_phys_dma,
2297         .get_cycle_time         = ohci_get_cycle_time,
2298
2299         .allocate_iso_context   = ohci_allocate_iso_context,
2300         .free_iso_context       = ohci_free_iso_context,
2301         .queue_iso              = ohci_queue_iso,
2302         .start_iso              = ohci_start_iso,
2303         .stop_iso               = ohci_stop_iso,
2304 };
2305
2306 #ifdef CONFIG_PPC_PMAC
2307 static void ohci_pmac_on(struct pci_dev *dev)
2308 {
2309         if (machine_is(powermac)) {
2310                 struct device_node *ofn = pci_device_to_OF_node(dev);
2311
2312                 if (ofn) {
2313                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2314                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2315                 }
2316         }
2317 }
2318
2319 static void ohci_pmac_off(struct pci_dev *dev)
2320 {
2321         if (machine_is(powermac)) {
2322                 struct device_node *ofn = pci_device_to_OF_node(dev);
2323
2324                 if (ofn) {
2325                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2326                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2327                 }
2328         }
2329 }
2330 #else
2331 #define ohci_pmac_on(dev)
2332 #define ohci_pmac_off(dev)
2333 #endif /* CONFIG_PPC_PMAC */
2334
2335 static int __devinit pci_probe(struct pci_dev *dev,
2336                                const struct pci_device_id *ent)
2337 {
2338         struct fw_ohci *ohci;
2339         u32 bus_options, max_receive, link_speed, version;
2340         u64 guid;
2341         int i, err, n_ir, n_it;
2342         size_t size;
2343
2344         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2345         if (ohci == NULL) {
2346                 err = -ENOMEM;
2347                 goto fail;
2348         }
2349
2350         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2351
2352         ohci_pmac_on(dev);
2353
2354         err = pci_enable_device(dev);
2355         if (err) {
2356                 fw_error("Failed to enable OHCI hardware\n");
2357                 goto fail_free;
2358         }
2359
2360         pci_set_master(dev);
2361         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2362         pci_set_drvdata(dev, ohci);
2363
2364         spin_lock_init(&ohci->lock);
2365
2366         tasklet_init(&ohci->bus_reset_tasklet,
2367                      bus_reset_tasklet, (unsigned long)ohci);
2368
2369         err = pci_request_region(dev, 0, ohci_driver_name);
2370         if (err) {
2371                 fw_error("MMIO resource unavailable\n");
2372                 goto fail_disable;
2373         }
2374
2375         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2376         if (ohci->registers == NULL) {
2377                 fw_error("Failed to remap registers\n");
2378                 err = -ENXIO;
2379                 goto fail_iomem;
2380         }
2381
2382         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2383                 if (ohci_quirks[i].vendor == dev->vendor &&
2384                     (ohci_quirks[i].device == dev->device ||
2385                      ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2386                         ohci->quirks = ohci_quirks[i].flags;
2387                         break;
2388                 }
2389         if (param_quirks)
2390                 ohci->quirks = param_quirks;
2391
2392         ar_context_init(&ohci->ar_request_ctx, ohci,
2393                         OHCI1394_AsReqRcvContextControlSet);
2394
2395         ar_context_init(&ohci->ar_response_ctx, ohci,
2396                         OHCI1394_AsRspRcvContextControlSet);
2397
2398         context_init(&ohci->at_request_ctx, ohci,
2399                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2400
2401         context_init(&ohci->at_response_ctx, ohci,
2402                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2403
2404         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2405         ohci->ir_context_channels = ~0ULL;
2406         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2407         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2408         n_ir = hweight32(ohci->ir_context_mask);
2409         size = sizeof(struct iso_context) * n_ir;
2410         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2411
2412         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2413         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2414         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2415         n_it = hweight32(ohci->it_context_mask);
2416         size = sizeof(struct iso_context) * n_it;
2417         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2418
2419         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2420                 err = -ENOMEM;
2421                 goto fail_contexts;
2422         }
2423
2424         /* self-id dma buffer allocation */
2425         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2426                                                SELF_ID_BUF_SIZE,
2427                                                &ohci->self_id_bus,
2428                                                GFP_KERNEL);
2429         if (ohci->self_id_cpu == NULL) {
2430                 err = -ENOMEM;
2431                 goto fail_contexts;
2432         }
2433
2434         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2435         max_receive = (bus_options >> 12) & 0xf;
2436         link_speed = bus_options & 0x7;
2437         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2438                 reg_read(ohci, OHCI1394_GUIDLo);
2439
2440         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2441         if (err)
2442                 goto fail_self_id;
2443
2444         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2445         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2446                   "%d IR + %d IT contexts, quirks 0x%x\n",
2447                   dev_name(&dev->dev), version >> 16, version & 0xff,
2448                   n_ir, n_it, ohci->quirks);
2449
2450         return 0;
2451
2452  fail_self_id:
2453         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2454                           ohci->self_id_cpu, ohci->self_id_bus);
2455  fail_contexts:
2456         kfree(ohci->ir_context_list);
2457         kfree(ohci->it_context_list);
2458         context_release(&ohci->at_response_ctx);
2459         context_release(&ohci->at_request_ctx);
2460         ar_context_release(&ohci->ar_response_ctx);
2461         ar_context_release(&ohci->ar_request_ctx);
2462         pci_iounmap(dev, ohci->registers);
2463  fail_iomem:
2464         pci_release_region(dev, 0);
2465  fail_disable:
2466         pci_disable_device(dev);
2467  fail_free:
2468         kfree(&ohci->card);
2469         ohci_pmac_off(dev);
2470  fail:
2471         if (err == -ENOMEM)
2472                 fw_error("Out of memory\n");
2473
2474         return err;
2475 }
2476
2477 static void pci_remove(struct pci_dev *dev)
2478 {
2479         struct fw_ohci *ohci;
2480
2481         ohci = pci_get_drvdata(dev);
2482         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2483         flush_writes(ohci);
2484         fw_core_remove_card(&ohci->card);
2485
2486         /*
2487          * FIXME: Fail all pending packets here, now that the upper
2488          * layers can't queue any more.
2489          */
2490
2491         software_reset(ohci);
2492         free_irq(dev->irq, ohci);
2493
2494         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2495                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2496                                   ohci->next_config_rom, ohci->next_config_rom_bus);
2497         if (ohci->config_rom)
2498                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2499                                   ohci->config_rom, ohci->config_rom_bus);
2500         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2501                           ohci->self_id_cpu, ohci->self_id_bus);
2502         ar_context_release(&ohci->ar_request_ctx);
2503         ar_context_release(&ohci->ar_response_ctx);
2504         context_release(&ohci->at_request_ctx);
2505         context_release(&ohci->at_response_ctx);
2506         kfree(ohci->it_context_list);
2507         kfree(ohci->ir_context_list);
2508         pci_iounmap(dev, ohci->registers);
2509         pci_release_region(dev, 0);
2510         pci_disable_device(dev);
2511         kfree(&ohci->card);
2512         ohci_pmac_off(dev);
2513
2514         fw_notify("Removed fw-ohci device.\n");
2515 }
2516
2517 #ifdef CONFIG_PM
2518 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2519 {
2520         struct fw_ohci *ohci = pci_get_drvdata(dev);
2521         int err;
2522
2523         software_reset(ohci);
2524         free_irq(dev->irq, ohci);
2525         err = pci_save_state(dev);
2526         if (err) {
2527                 fw_error("pci_save_state failed\n");
2528                 return err;
2529         }
2530         err = pci_set_power_state(dev, pci_choose_state(dev, state));
2531         if (err)
2532                 fw_error("pci_set_power_state failed with %d\n", err);
2533         ohci_pmac_off(dev);
2534
2535         return 0;
2536 }
2537
2538 static int pci_resume(struct pci_dev *dev)
2539 {
2540         struct fw_ohci *ohci = pci_get_drvdata(dev);
2541         int err;
2542
2543         ohci_pmac_on(dev);
2544         pci_set_power_state(dev, PCI_D0);
2545         pci_restore_state(dev);
2546         err = pci_enable_device(dev);
2547         if (err) {
2548                 fw_error("pci_enable_device failed\n");
2549                 return err;
2550         }
2551
2552         return ohci_enable(&ohci->card, NULL, 0);
2553 }
2554 #endif
2555
2556 static const struct pci_device_id pci_table[] = {
2557         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2558         { }
2559 };
2560
2561 MODULE_DEVICE_TABLE(pci, pci_table);
2562
2563 static struct pci_driver fw_ohci_pci_driver = {
2564         .name           = ohci_driver_name,
2565         .id_table       = pci_table,
2566         .probe          = pci_probe,
2567         .remove         = pci_remove,
2568 #ifdef CONFIG_PM
2569         .resume         = pci_resume,
2570         .suspend        = pci_suspend,
2571 #endif
2572 };
2573
2574 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2575 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2576 MODULE_LICENSE("GPL");
2577
2578 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2579 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2580 MODULE_ALIAS("ohci1394");
2581 #endif
2582
2583 static int __init fw_ohci_init(void)
2584 {
2585         return pci_register_driver(&fw_ohci_pci_driver);
2586 }
2587
2588 static void __exit fw_ohci_cleanup(void)
2589 {
2590         pci_unregister_driver(&fw_ohci_pci_driver);
2591 }
2592
2593 module_init(fw_ohci_init);
2594 module_exit(fw_ohci_cleanup);