drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bug.h>
  22 #include <linux/compiler.h>
  23 #include <linux/delay.h>
  24 #include <linux/device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/firewire.h>
  27 #include <linux/firewire-constants.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kernel.h>
  32 #include <linux/list.h>
  33 #include <linux/mm.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/mutex.h>
  37 #include <linux/pci.h>
  38 #include <linux/pci_ids.h>
  39 #include <linux/slab.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/string.h>
  42 #include <linux/time.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/page.h>
  46 #include <asm/system.h>
  47
  48 #ifdef CONFIG_PPC_PMAC
  49 #include <asm/pmac_feature.h>
  50 #endif
  51
  52 #include "core.h"
  53 #include "ohci.h"
  54
  55 #define DESCRIPTOR_OUTPUT_MORE          0
  56 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  57 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  58 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  59 #define DESCRIPTOR_STATUS               (1 << 11)
  60 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  61 #define DESCRIPTOR_PING                 (1 << 7)
  62 #define DESCRIPTOR_YY                   (1 << 6)
  63 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  64 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  65 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  66 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  67 #define DESCRIPTOR_WAIT                 (3 << 0)
  68
  69 struct descriptor {
  70         __le16 req_count;
  71         __le16 control;
  72         __le32 data_address;
  73         __le32 branch_address;
  74         __le16 res_count;
  75         __le16 transfer_status;
  76 } __attribute__((aligned(16)));
  77
  78 #define CONTROL_SET(regs)       (regs)
  79 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  80 #define COMMAND_PTR(regs)       ((regs) + 12)
  81 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  82
  83 struct ar_buffer {
  84         struct descriptor descriptor;
  85         struct ar_buffer *next;
  86         __le32 data[0];
  87 };
  88
  89 struct ar_context {
  90         struct fw_ohci *ohci;
  91         struct ar_buffer *current_buffer;
  92         struct ar_buffer *last_buffer;
  93         void *pointer;
  94         u32 regs;
  95         struct tasklet_struct tasklet;
  96 };
  97
  98 struct context;
  99
 100 typedef int (*descriptor_callback_t)(struct context *ctx,
 101                                      struct descriptor *d,
 102                                      struct descriptor *last);
 103
 104 /*
 105  * A buffer that contains a block of DMA-able coherent memory used for
 106  * storing a portion of a DMA descriptor program.
 107  */
 108 struct descriptor_buffer {
 109         struct list_head list;
 110         dma_addr_t buffer_bus;
 111         size_t buffer_size;
 112         size_t used;
 113         struct descriptor buffer[0];
 114 };
 115
 116 struct context {
 117         struct fw_ohci *ohci;
 118         u32 regs;
 119         int total_allocation;
 120
 121         /*
 122          * List of page-sized buffers for storing DMA descriptors.
 123          * Head of list contains buffers in use and tail of list contains
 124          * free buffers.
 125          */
 126         struct list_head buffer_list;
 127
 128         /*
 129          * Pointer to a buffer inside buffer_list that contains the tail
 130          * end of the current DMA program.
 131          */
 132         struct descriptor_buffer *buffer_tail;
 133
 134         /*
 135          * The descriptor containing the branch address of the first
 136          * descriptor that has not yet been filled by the device.
 137          */
 138         struct descriptor *last;
 139
 140         /*
 141          * The last descriptor in the DMA program.  It contains the branch
 142          * address that must be updated upon appending a new descriptor.
 143          */
 144         struct descriptor *prev;
 145
 146         descriptor_callback_t callback;
 147
 148         struct tasklet_struct tasklet;
 149 };
 150
 151 #define IT_HEADER_SY(v)          ((v) <<  0)
 152 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 153 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 154 #define IT_HEADER_TAG(v)         ((v) << 14)
 155 #define IT_HEADER_SPEED(v)       ((v) << 16)
 156 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 157
 158 struct iso_context {
 159         struct fw_iso_context base;
 160         struct context context;
 161         int excess_bytes;
 162         void *header;
 163         size_t header_length;
 164 };
 165
 166 #define CONFIG_ROM_SIZE 1024
 167
 168 struct fw_ohci {
 169         struct fw_card card;
 170
 171         __iomem char *registers;
 172         int node_id;
 173         int generation;
 174         int request_generation; /* for timestamping incoming requests */
 175         unsigned quirks;
 176         unsigned int pri_req_max;
 177         u32 bus_time;
 178         bool is_root;
 179         bool csr_state_setclear_abdicate;
 180
 181         /*
 182          * Spinlock for accessing fw_ohci data.  Never call out of
 183          * this driver with this lock held.
 184          */
 185         spinlock_t lock;
 186
 187         struct mutex phy_reg_mutex;
 188
 189         struct ar_context ar_request_ctx;
 190         struct ar_context ar_response_ctx;
 191         struct context at_request_ctx;
 192         struct context at_response_ctx;
 193
 194         u32 it_context_mask;     /* unoccupied IT contexts */
 195         struct iso_context *it_context_list;
 196         u64 ir_context_channels; /* unoccupied channels */
 197         u32 ir_context_mask;     /* unoccupied IR contexts */
 198         struct iso_context *ir_context_list;
 199         u64 mc_channels; /* channels in use by the multichannel IR context */
 200         bool mc_allocated;
 201
 202         __be32    *config_rom;
 203         dma_addr_t config_rom_bus;
 204         __be32    *next_config_rom;
 205         dma_addr_t next_config_rom_bus;
 206         __be32     next_header;
 207
 208         __le32    *self_id_cpu;
 209         dma_addr_t self_id_bus;
 210         struct tasklet_struct bus_reset_tasklet;
 211
 212         u32 self_id_buffer[512];
 213 };
 214
 215 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 216 {
 217         return container_of(card, struct fw_ohci, card);
 218 }
 219
 220 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 221 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 222 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 223 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 224 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 225 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 226
 227 #define CONTEXT_RUN     0x8000
 228 #define CONTEXT_WAKE    0x1000
 229 #define CONTEXT_DEAD    0x0800
 230 #define CONTEXT_ACTIVE  0x0400
 231
 232 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 233 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 234 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 235
 236 #define OHCI1394_REGISTER_SIZE          0x800
 237 #define OHCI_LOOP_COUNT                 500
 238 #define OHCI1394_PCI_HCI_Control        0x40
 239 #define SELF_ID_BUF_SIZE                0x800
 240 #define OHCI_TCODE_PHY_PACKET           0x0e
 241 #define OHCI_VERSION_1_1                0x010010
 242
 243 static char ohci_driver_name[] = KBUILD_MODNAME;
 244
 245 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 246 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 247
 248 #define QUIRK_CYCLE_TIMER               1
 249 #define QUIRK_RESET_PACKET              2
 250 #define QUIRK_BE_HEADERS                4
 251 #define QUIRK_NO_1394A                  8
 252 #define QUIRK_NO_MSI                    16
 253
 254 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 255 static const struct {
 256         unsigned short vendor, device, flags;
 257 } ohci_quirks[] = {
 258         {PCI_VENDOR_ID_TI,      PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
 259                                                             QUIRK_RESET_PACKET |
 260                                                             QUIRK_NO_1394A},
 261         {PCI_VENDOR_ID_TI,      PCI_ANY_ID,     QUIRK_RESET_PACKET},
 262         {PCI_VENDOR_ID_AL,      PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 263         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
 264         {PCI_VENDOR_ID_NEC,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 265         {PCI_VENDOR_ID_VIA,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 266         {PCI_VENDOR_ID_RICOH,   PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 267         {PCI_VENDOR_ID_APPLE,   PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
 268 };
 269
 270 /* This overrides anything that was found in ohci_quirks[]. */
 271 static int param_quirks;
 272 module_param_named(quirks, param_quirks, int, 0644);
 273 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 274         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 275         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 276         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 277         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 278         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 279         ")");
 280
 281 #define OHCI_PARAM_DEBUG_AT_AR          1
 282 #define OHCI_PARAM_DEBUG_SELFIDS        2
 283 #define OHCI_PARAM_DEBUG_IRQS           4
 284 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 285
 286 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 287
 288 static int param_debug;
 289 module_param_named(debug, param_debug, int, 0644);
 290 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 291         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 292         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 293         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 294         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 295         ", or a combination, or all = -1)");
 296
 297 static void log_irqs(u32 evt)
 298 {
 299         if (likely(!(param_debug &
 300                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 301                 return;
 302
 303         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 304             !(evt & OHCI1394_busReset))
 305                 return;
 306
 307         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 308             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 309             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 310             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 311             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 312             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 313             evt & OHCI1394_isochRx              ? " IR"                 : "",
 314             evt & OHCI1394_isochTx              ? " IT"                 : "",
 315             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 316             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 317             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 318             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 319             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 320             evt & OHCI1394_busReset             ? " busReset"           : "",
 321             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 322                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 323                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 324                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 325                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 326                     OHCI1394_cycleInconsistent |
 327                     OHCI1394_regAccessFail | OHCI1394_busReset)
 328                                                 ? " ?"                  : "");
 329 }
 330
 331 static const char *speed[] = {
 332         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 333 };
 334 static const char *power[] = {
 335         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 336         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 337 };
 338 static const char port[] = { '.', '-', 'p', 'c', };
 339
 340 static char _p(u32 *s, int shift)
 341 {
 342         return port[*s >> shift & 3];
 343 }
 344
 345 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 346 {
 347         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 348                 return;
 349
 350         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 351                   self_id_count, generation, node_id);
 352
 353         for (; self_id_count--; ++s)
 354                 if ((*s & 1 << 23) == 0)
 355                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 356                             "%s gc=%d %s %s%s%s\n",
 357                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 358                             speed[*s >> 14 & 3], *s >> 16 & 63,
 359                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 360                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 361                 else
 362                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 363                             *s, *s >> 24 & 63,
 364                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 365                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 366 }
 367
 368 static const char *evts[] = {
 369         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 370         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 371         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 372         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 373         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 374         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 375         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 376         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 377         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 378         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 379         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 380         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 381         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 382         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 383         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 384         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 385         [0x20] = "pending/cancelled",
 386 };
 387 static const char *tcodes[] = {
 388         [0x0] = "QW req",               [0x1] = "BW req",
 389         [0x2] = "W resp",               [0x3] = "-reserved-",
 390         [0x4] = "QR req",               [0x5] = "BR req",
 391         [0x6] = "QR resp",              [0x7] = "BR resp",
 392         [0x8] = "cycle start",          [0x9] = "Lk req",
 393         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 394         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 395         [0xe] = "link internal",        [0xf] = "-reserved-",
 396 };
 397 static const char *phys[] = {
 398         [0x0] = "phy config packet",    [0x1] = "link-on packet",
 399         [0x2] = "self-id packet",       [0x3] = "-reserved-",
 400 };
 401
 402 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 403 {
 404         int tcode = header[0] >> 4 & 0xf;
 405         char specific[12];
 406
 407         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 408                 return;
 409
 410         if (unlikely(evt >= ARRAY_SIZE(evts)))
 411                         evt = 0x1f;
 412
 413         if (evt == OHCI1394_evt_bus_reset) {
 414                 fw_notify("A%c evt_bus_reset, generation %d\n",
 415                     dir, (header[2] >> 16) & 0xff);
 416                 return;
 417         }
 418
 419         if (header[0] == ~header[1]) {
 420                 fw_notify("A%c %s, %s, %08x\n",
 421                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
 422                 return;
 423         }
 424
 425         switch (tcode) {
 426         case 0x0: case 0x6: case 0x8:
 427                 snprintf(specific, sizeof(specific), " = %08x",
 428                          be32_to_cpu((__force __be32)header[3]));
 429                 break;
 430         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 431                 snprintf(specific, sizeof(specific), " %x,%x",
 432                          header[3] >> 16, header[3] & 0xffff);
 433                 break;
 434         default:
 435                 specific[0] = '\0';
 436         }
 437
 438         switch (tcode) {
 439         case 0xe: case 0xa:
 440                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 441                 break;
 442         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 443                 fw_notify("A%c spd %x tl %02x, "
 444                     "%04x -> %04x, %s, "
 445                     "%s, %04x%08x%s\n",
 446                     dir, speed, header[0] >> 10 & 0x3f,
 447                     header[1] >> 16, header[0] >> 16, evts[evt],
 448                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 449                 break;
 450         default:
 451                 fw_notify("A%c spd %x tl %02x, "
 452                     "%04x -> %04x, %s, "
 453                     "%s%s\n",
 454                     dir, speed, header[0] >> 10 & 0x3f,
 455                     header[1] >> 16, header[0] >> 16, evts[evt],
 456                     tcodes[tcode], specific);
 457         }
 458 }
 459
 460 #else
 461
 462 #define param_debug 0
 463 static inline void log_irqs(u32 evt) {}
 464 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 465 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 466
 467 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 468
 469 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 470 {
 471         writel(data, ohci->registers + offset);
 472 }
 473
 474 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 475 {
 476         return readl(ohci->registers + offset);
 477 }
 478
 479 static inline void flush_writes(const struct fw_ohci *ohci)
 480 {
 481         /* Do a dummy read to flush writes. */
 482         reg_read(ohci, OHCI1394_Version);
 483 }
 484
 485 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 486 {
 487         u32 val;
 488         int i;
 489
 490         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 491         for (i = 0; i < 3 + 100; i++) {
 492                 val = reg_read(ohci, OHCI1394_PhyControl);
 493                 if (val & OHCI1394_PhyControl_ReadDone)
 494                         return OHCI1394_PhyControl_ReadData(val);
 495
 496                 /*
 497                  * Try a few times without waiting.  Sleeping is necessary
 498                  * only when the link/PHY interface is busy.
 499                  */
 500                 if (i >= 3)
 501                         msleep(1);
 502         }
 503         fw_error("failed to read phy reg\n");
 504
 505         return -EBUSY;
 506 }
 507
 508 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 509 {
 510         int i;
 511
 512         reg_write(ohci, OHCI1394_PhyControl,
 513                   OHCI1394_PhyControl_Write(addr, val));
 514         for (i = 0; i < 3 + 100; i++) {
 515                 val = reg_read(ohci, OHCI1394_PhyControl);
 516                 if (!(val & OHCI1394_PhyControl_WritePending))
 517                         return 0;
 518
 519                 if (i >= 3)
 520                         msleep(1);
 521         }
 522         fw_error("failed to write phy reg\n");
 523
 524         return -EBUSY;
 525 }
 526
 527 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 528                           int clear_bits, int set_bits)
 529 {
 530         int ret = read_phy_reg(ohci, addr);
 531         if (ret < 0)
 532                 return ret;
 533
 534         /*
 535          * The interrupt status bits are cleared by writing a one bit.
 536          * Avoid clearing them unless explicitly requested in set_bits.
 537          */
 538         if (addr == 5)
 539                 clear_bits |= PHY_INT_STATUS_BITS;
 540
 541         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 542 }
 543
 544 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 545 {
 546         int ret;
 547
 548         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 549         if (ret < 0)
 550                 return ret;
 551
 552         return read_phy_reg(ohci, addr);
 553 }
 554
 555 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 556 {
 557         struct fw_ohci *ohci = fw_ohci(card);
 558         int ret;
 559
 560         mutex_lock(&ohci->phy_reg_mutex);
 561         ret = read_phy_reg(ohci, addr);
 562         mutex_unlock(&ohci->phy_reg_mutex);
 563
 564         return ret;
 565 }
 566
 567 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 568                                int clear_bits, int set_bits)
 569 {
 570         struct fw_ohci *ohci = fw_ohci(card);
 571         int ret;
 572
 573         mutex_lock(&ohci->phy_reg_mutex);
 574         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 575         mutex_unlock(&ohci->phy_reg_mutex);
 576
 577         return ret;
 578 }
 579
 580 static void ar_context_link_page(struct ar_context *ctx,
 581                                  struct ar_buffer *ab, dma_addr_t ab_bus)
 582 {
 583         size_t offset;
 584
 585         ab->next = NULL;
 586         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 587         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 588                                                     DESCRIPTOR_STATUS |
 589                                                     DESCRIPTOR_BRANCH_ALWAYS);
 590         offset = offsetof(struct ar_buffer, data);
 591         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 592         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 593         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 594         ab->descriptor.branch_address = 0;
 595
 596         wmb(); /* finish init of new descriptors before branch_address update */
 597         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 598         ctx->last_buffer->next = ab;
 599         ctx->last_buffer = ab;
 600
 601         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 602         flush_writes(ctx->ohci);
 603 }
 604
 605 static int ar_context_add_page(struct ar_context *ctx)
 606 {
 607         struct device *dev = ctx->ohci->card.device;
 608         struct ar_buffer *ab;
 609         dma_addr_t uninitialized_var(ab_bus);
 610
 611         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
 612         if (ab == NULL)
 613                 return -ENOMEM;
 614
 615         ar_context_link_page(ctx, ab, ab_bus);
 616
 617         return 0;
 618 }
 619
 620 static void ar_context_release(struct ar_context *ctx)
 621 {
 622         struct ar_buffer *ab, *ab_next;
 623         size_t offset;
 624         dma_addr_t ab_bus;
 625
 626         for (ab = ctx->current_buffer; ab; ab = ab_next) {
 627                 ab_next = ab->next;
 628                 offset = offsetof(struct ar_buffer, data);
 629                 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 630                 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
 631                                   ab, ab_bus);
 632         }
 633 }
 634
 635 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 636 #define cond_le32_to_cpu(v) \
 637         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 638 #else
 639 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 640 #endif
 641
 642 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 643 {
 644         struct fw_ohci *ohci = ctx->ohci;
 645         struct fw_packet p;
 646         u32 status, length, tcode;
 647         int evt;
 648
 649         p.header[0] = cond_le32_to_cpu(buffer[0]);
 650         p.header[1] = cond_le32_to_cpu(buffer[1]);
 651         p.header[2] = cond_le32_to_cpu(buffer[2]);
 652
 653         tcode = (p.header[0] >> 4) & 0x0f;
 654         switch (tcode) {
 655         case TCODE_WRITE_QUADLET_REQUEST:
 656         case TCODE_READ_QUADLET_RESPONSE:
 657                 p.header[3] = (__force __u32) buffer[3];
 658                 p.header_length = 16;
 659                 p.payload_length = 0;
 660                 break;
 661
 662         case TCODE_READ_BLOCK_REQUEST :
 663                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 664                 p.header_length = 16;
 665                 p.payload_length = 0;
 666                 break;
 667
 668         case TCODE_WRITE_BLOCK_REQUEST:
 669         case TCODE_READ_BLOCK_RESPONSE:
 670         case TCODE_LOCK_REQUEST:
 671         case TCODE_LOCK_RESPONSE:
 672                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 673                 p.header_length = 16;
 674                 p.payload_length = p.header[3] >> 16;
 675                 break;
 676
 677         case TCODE_WRITE_RESPONSE:
 678         case TCODE_READ_QUADLET_REQUEST:
 679         case OHCI_TCODE_PHY_PACKET:
 680                 p.header_length = 12;
 681                 p.payload_length = 0;
 682                 break;
 683
 684         default:
 685                 /* FIXME: Stop context, discard everything, and restart? */
 686                 p.header_length = 0;
 687                 p.payload_length = 0;
 688         }
 689
 690         p.payload = (void *) buffer + p.header_length;
 691
 692         /* FIXME: What to do about evt_* errors? */
 693         length = (p.header_length + p.payload_length + 3) / 4;
 694         status = cond_le32_to_cpu(buffer[length]);
 695         evt    = (status >> 16) & 0x1f;
 696
 697         p.ack        = evt - 16;
 698         p.speed      = (status >> 21) & 0x7;
 699         p.timestamp  = status & 0xffff;
 700         p.generation = ohci->request_generation;
 701
 702         log_ar_at_event('R', p.speed, p.header, evt);
 703
 704         /*
 705          * Several controllers, notably from NEC and VIA, forget to
 706          * write ack_complete status at PHY packet reception.
 707          */
 708         if (evt == OHCI1394_evt_no_status &&
 709             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 710                 p.ack = ACK_COMPLETE;
 711
 712         /*
 713          * The OHCI bus reset handler synthesizes a PHY packet with
 714          * the new generation number when a bus reset happens (see
 715          * section 8.4.2.3).  This helps us determine when a request
 716          * was received and make sure we send the response in the same
 717          * generation.  We only need this for requests; for responses
 718          * we use the unique tlabel for finding the matching
 719          * request.
 720          *
 721          * Alas some chips sometimes emit bus reset packets with a
 722          * wrong generation.  We set the correct generation for these
 723          * at a slightly incorrect time (in bus_reset_tasklet).
 724          */
 725         if (evt == OHCI1394_evt_bus_reset) {
 726                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 727                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 728         } else if (ctx == &ohci->ar_request_ctx) {
 729                 fw_core_handle_request(&ohci->card, &p);
 730         } else {
 731                 fw_core_handle_response(&ohci->card, &p);
 732         }
 733
 734         return buffer + length + 1;
 735 }
 736
 737 static void ar_context_tasklet(unsigned long data)
 738 {
 739         struct ar_context *ctx = (struct ar_context *)data;
 740         struct ar_buffer *ab;
 741         struct descriptor *d;
 742         void *buffer, *end;
 743
 744         ab = ctx->current_buffer;
 745         d = &ab->descriptor;
 746
 747         if (d->res_count == 0) {
 748                 size_t size, size2, rest, pktsize, size3, offset;
 749                 dma_addr_t start_bus;
 750                 void *start;
 751
 752                 /*
 753                  * This descriptor is finished and we may have a
 754                  * packet split across this and the next buffer. We
 755                  * reuse the page for reassembling the split packet.
 756                  */
 757
 758                 offset = offsetof(struct ar_buffer, data);
 759                 start = ab;
 760                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 761                 buffer = ab->data;
 762
 763                 ab = ab->next;
 764                 d = &ab->descriptor;
 765                 size = start + PAGE_SIZE - ctx->pointer;
 766                 /* valid buffer data in the next page */
 767                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 768                 /* what actually fits in this page */
 769                 size2 = min(rest, (size_t)PAGE_SIZE - offset - size);
 770                 memmove(buffer, ctx->pointer, size);
 771                 memcpy(buffer + size, ab->data, size2);
 772
 773                 while (size > 0) {
 774                         void *next = handle_ar_packet(ctx, buffer);
 775                         pktsize = next - buffer;
 776                         if (pktsize >= size) {
 777                                 /*
 778                                  * We have handled all the data that was
 779                                  * originally in this page, so we can now
 780                                  * continue in the next page.
 781                                  */
 782                                 buffer = next;
 783                                 break;
 784                         }
 785                         /* move the next packet to the start of the buffer */
 786                         memmove(buffer, next, size + size2 - pktsize);
 787                         size -= pktsize;
 788                         /* fill up this page again */
 789                         size3 = min(rest - size2,
 790                                     (size_t)PAGE_SIZE - offset - size - size2);
 791                         memcpy(buffer + size + size2,
 792                                (void *) ab->data + size2, size3);
 793                         size2 += size3;
 794                 }
 795
 796                 if (rest > 0) {
 797                         /* handle the packets that are fully in the next page */
 798                         buffer = (void *) ab->data +
 799                                         (buffer - (start + offset + size));
 800                         end = (void *) ab->data + rest;
 801
 802                         while (buffer < end)
 803                                 buffer = handle_ar_packet(ctx, buffer);
 804
 805                         ctx->current_buffer = ab;
 806                         ctx->pointer = end;
 807
 808                         ar_context_link_page(ctx, start, start_bus);
 809                 } else {
 810                         ctx->pointer = start + PAGE_SIZE;
 811                 }
 812         } else {
 813                 buffer = ctx->pointer;
 814                 ctx->pointer = end =
 815                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 816
 817                 while (buffer < end)
 818                         buffer = handle_ar_packet(ctx, buffer);
 819         }
 820 }
 821
 822 static int ar_context_init(struct ar_context *ctx,
 823                            struct fw_ohci *ohci, u32 regs)
 824 {
 825         struct ar_buffer ab;
 826
 827         ctx->regs        = regs;
 828         ctx->ohci        = ohci;
 829         ctx->last_buffer = &ab;
 830         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 831
 832         ar_context_add_page(ctx);
 833         ar_context_add_page(ctx);
 834         ctx->current_buffer = ab.next;
 835         ctx->pointer = ctx->current_buffer->data;
 836
 837         return 0;
 838 }
 839
 840 static void ar_context_run(struct ar_context *ctx)
 841 {
 842         struct ar_buffer *ab = ctx->current_buffer;
 843         dma_addr_t ab_bus;
 844         size_t offset;
 845
 846         offset = offsetof(struct ar_buffer, data);
 847         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 848
 849         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 850         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 851         flush_writes(ctx->ohci);
 852 }
 853
 854 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
 855 {
 856         int b, key;
 857
 858         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
 859         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
 860
 861         /* figure out which descriptor the branch address goes in */
 862         if (z == 2 && (b == 3 || key == 2))
 863                 return d;
 864         else
 865                 return d + z - 1;
 866 }
 867
 868 static void context_tasklet(unsigned long data)
 869 {
 870         struct context *ctx = (struct context *) data;
 871         struct descriptor *d, *last;
 872         u32 address;
 873         int z;
 874         struct descriptor_buffer *desc;
 875
 876         desc = list_entry(ctx->buffer_list.next,
 877                         struct descriptor_buffer, list);
 878         last = ctx->last;
 879         while (last->branch_address != 0) {
 880                 struct descriptor_buffer *old_desc = desc;
 881                 address = le32_to_cpu(last->branch_address);
 882                 z = address & 0xf;
 883                 address &= ~0xf;
 884
 885                 /* If the branch address points to a buffer outside of the
 886                  * current buffer, advance to the next buffer. */
 887                 if (address < desc->buffer_bus ||
 888                                 address >= desc->buffer_bus + desc->used)
 889                         desc = list_entry(desc->list.next,
 890                                         struct descriptor_buffer, list);
 891                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
 892                 last = find_branch_descriptor(d, z);
 893
 894                 if (!ctx->callback(ctx, d, last))
 895                         break;
 896
 897                 if (old_desc != desc) {
 898                         /* If we've advanced to the next buffer, move the
 899                          * previous buffer to the free list. */
 900                         unsigned long flags;
 901                         old_desc->used = 0;
 902                         spin_lock_irqsave(&ctx->ohci->lock, flags);
 903                         list_move_tail(&old_desc->list, &ctx->buffer_list);
 904                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 905                 }
 906                 ctx->last = last;
 907         }
 908 }
 909
 910 /*
 911  * Allocate a new buffer and add it to the list of free buffers for this
 912  * context.  Must be called with ohci->lock held.
 913  */
 914 static int context_add_buffer(struct context *ctx)
 915 {
 916         struct descriptor_buffer *desc;
 917         dma_addr_t uninitialized_var(bus_addr);
 918         int offset;
 919
 920         /*
 921          * 16MB of descriptors should be far more than enough for any DMA
 922          * program.  This will catch run-away userspace or DoS attacks.
 923          */
 924         if (ctx->total_allocation >= 16*1024*1024)
 925                 return -ENOMEM;
 926
 927         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
 928                         &bus_addr, GFP_ATOMIC);
 929         if (!desc)
 930                 return -ENOMEM;
 931
 932         offset = (void *)&desc->buffer - (void *)desc;
 933         desc->buffer_size = PAGE_SIZE - offset;
 934         desc->buffer_bus = bus_addr + offset;
 935         desc->used = 0;
 936
 937         list_add_tail(&desc->list, &ctx->buffer_list);
 938         ctx->total_allocation += PAGE_SIZE;
 939
 940         return 0;
 941 }
 942
 943 static int context_init(struct context *ctx, struct fw_ohci *ohci,
 944                         u32 regs, descriptor_callback_t callback)
 945 {
 946         ctx->ohci = ohci;
 947         ctx->regs = regs;
 948         ctx->total_allocation = 0;
 949
 950         INIT_LIST_HEAD(&ctx->buffer_list);
 951         if (context_add_buffer(ctx) < 0)
 952                 return -ENOMEM;
 953
 954         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
 955                         struct descriptor_buffer, list);
 956
 957         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 958         ctx->callback = callback;
 959
 960         /*
 961          * We put a dummy descriptor in the buffer that has a NULL
 962          * branch address and looks like it's been sent.  That way we
 963          * have a descriptor to append DMA programs to.
 964          */
 965         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
 966         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 967         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
 968         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
 969         ctx->last = ctx->buffer_tail->buffer;
 970         ctx->prev = ctx->buffer_tail->buffer;
 971
 972         return 0;
 973 }
 974
 975 static void context_release(struct context *ctx)
 976 {
 977         struct fw_card *card = &ctx->ohci->card;
 978         struct descriptor_buffer *desc, *tmp;
 979
 980         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
 981                 dma_free_coherent(card->device, PAGE_SIZE, desc,
 982                         desc->buffer_bus -
 983                         ((void *)&desc->buffer - (void *)desc));
 984 }
 985
 986 /* Must be called with ohci->lock held */
 987 static struct descriptor *context_get_descriptors(struct context *ctx,
 988                                                   int z, dma_addr_t *d_bus)
 989 {
 990         struct descriptor *d = NULL;
 991         struct descriptor_buffer *desc = ctx->buffer_tail;
 992
 993         if (z * sizeof(*d) > desc->buffer_size)
 994                 return NULL;
 995
 996         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
 997                 /* No room for the descriptor in this buffer, so advance to the
 998                  * next one. */
 999
1000                 if (desc->list.next == &ctx->buffer_list) {
1001                         /* If there is no free buffer next in the list,
1002                          * allocate one. */
1003                         if (context_add_buffer(ctx) < 0)
1004                                 return NULL;
1005                 }
1006                 desc = list_entry(desc->list.next,
1007                                 struct descriptor_buffer, list);
1008                 ctx->buffer_tail = desc;
1009         }
1010
1011         d = desc->buffer + desc->used / sizeof(*d);
1012         memset(d, 0, z * sizeof(*d));
1013         *d_bus = desc->buffer_bus + desc->used;
1014
1015         return d;
1016 }
1017
1018 static void context_run(struct context *ctx, u32 extra)
1019 {
1020         struct fw_ohci *ohci = ctx->ohci;
1021
1022         reg_write(ohci, COMMAND_PTR(ctx->regs),
1023                   le32_to_cpu(ctx->last->branch_address));
1024         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1025         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1026         flush_writes(ohci);
1027 }
1028
1029 static void context_append(struct context *ctx,
1030                            struct descriptor *d, int z, int extra)
1031 {
1032         dma_addr_t d_bus;
1033         struct descriptor_buffer *desc = ctx->buffer_tail;
1034
1035         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1036
1037         desc->used += (z + extra) * sizeof(*d);
1038
1039         wmb(); /* finish init of new descriptors before branch_address update */
1040         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1041         ctx->prev = find_branch_descriptor(d, z);
1042
1043         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1044         flush_writes(ctx->ohci);
1045 }
1046
1047 static void context_stop(struct context *ctx)
1048 {
1049         u32 reg;
1050         int i;
1051
1052         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1053         flush_writes(ctx->ohci);
1054
1055         for (i = 0; i < 10; i++) {
1056                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1057                 if ((reg & CONTEXT_ACTIVE) == 0)
1058                         return;
1059
1060                 mdelay(1);
1061         }
1062         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1063 }
1064
1065 struct driver_data {
1066         struct fw_packet *packet;
1067 };
1068
1069 /*
1070  * This function apppends a packet to the DMA queue for transmission.
1071  * Must always be called with the ochi->lock held to ensure proper
1072  * generation handling and locking around packet queue manipulation.
1073  */
1074 static int at_context_queue_packet(struct context *ctx,
1075                                    struct fw_packet *packet)
1076 {
1077         struct fw_ohci *ohci = ctx->ohci;
1078         dma_addr_t d_bus, uninitialized_var(payload_bus);
1079         struct driver_data *driver_data;
1080         struct descriptor *d, *last;
1081         __le32 *header;
1082         int z, tcode;
1083         u32 reg;
1084
1085         d = context_get_descriptors(ctx, 4, &d_bus);
1086         if (d == NULL) {
1087                 packet->ack = RCODE_SEND_ERROR;
1088                 return -1;
1089         }
1090
1091         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1092         d[0].res_count = cpu_to_le16(packet->timestamp);
1093
1094         /*
1095          * The DMA format for asyncronous link packets is different
1096          * from the IEEE1394 layout, so shift the fields around
1097          * accordingly.  If header_length is 8, it's a PHY packet, to
1098          * which we need to prepend an extra quadlet.
1099          */
1100
1101         header = (__le32 *) &d[1];
1102         switch (packet->header_length) {
1103         case 16:
1104         case 12:
1105                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1106                                         (packet->speed << 16));
1107                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1108                                         (packet->header[0] & 0xffff0000));
1109                 header[2] = cpu_to_le32(packet->header[2]);
1110
1111                 tcode = (packet->header[0] >> 4) & 0x0f;
1112                 if (TCODE_IS_BLOCK_PACKET(tcode))
1113                         header[3] = cpu_to_le32(packet->header[3]);
1114                 else
1115                         header[3] = (__force __le32) packet->header[3];
1116
1117                 d[0].req_count = cpu_to_le16(packet->header_length);
1118                 break;
1119
1120         case 8:
1121                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1122                                         (packet->speed << 16));
1123                 header[1] = cpu_to_le32(packet->header[0]);
1124                 header[2] = cpu_to_le32(packet->header[1]);
1125                 d[0].req_count = cpu_to_le16(12);
1126
1127                 if (is_ping_packet(packet->header))
1128                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1129                 break;
1130
1131         case 4:
1132                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1133                                         (packet->speed << 16));
1134                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1135                 d[0].req_count = cpu_to_le16(8);
1136                 break;
1137
1138         default:
1139                 /* BUG(); */
1140                 packet->ack = RCODE_SEND_ERROR;
1141                 return -1;
1142         }
1143
1144         driver_data = (struct driver_data *) &d[3];
1145         driver_data->packet = packet;
1146         packet->driver_data = driver_data;
1147
1148         if (packet->payload_length > 0) {
1149                 payload_bus =
1150                         dma_map_single(ohci->card.device, packet->payload,
1151                                        packet->payload_length, DMA_TO_DEVICE);
1152                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1153                         packet->ack = RCODE_SEND_ERROR;
1154                         return -1;
1155                 }
1156                 packet->payload_bus     = payload_bus;
1157                 packet->payload_mapped  = true;
1158
1159                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1160                 d[2].data_address = cpu_to_le32(payload_bus);
1161                 last = &d[2];
1162                 z = 3;
1163         } else {
1164                 last = &d[0];
1165                 z = 2;
1166         }
1167
1168         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1169                                      DESCRIPTOR_IRQ_ALWAYS |
1170                                      DESCRIPTOR_BRANCH_ALWAYS);
1171
1172         /*
1173          * If the controller and packet generations don't match, we need to
1174          * bail out and try again.  If IntEvent.busReset is set, the AT context
1175          * is halted, so appending to the context and trying to run it is
1176          * futile.  Most controllers do the right thing and just flush the AT
1177          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1178          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1179          * up stalling out.  So we just bail out in software and try again
1180          * later, and everyone is happy.
1181          * FIXME: Document how the locking works.
1182          */
1183         if (ohci->generation != packet->generation ||
1184             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1185                 if (packet->payload_mapped)
1186                         dma_unmap_single(ohci->card.device, payload_bus,
1187                                          packet->payload_length, DMA_TO_DEVICE);
1188                 packet->ack = RCODE_GENERATION;
1189                 return -1;
1190         }
1191
1192         context_append(ctx, d, z, 4 - z);
1193
1194         /* If the context isn't already running, start it up. */
1195         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1196         if ((reg & CONTEXT_RUN) == 0)
1197                 context_run(ctx, 0);
1198
1199         return 0;
1200 }
1201
1202 static int handle_at_packet(struct context *context,
1203                             struct descriptor *d,
1204                             struct descriptor *last)
1205 {
1206         struct driver_data *driver_data;
1207         struct fw_packet *packet;
1208         struct fw_ohci *ohci = context->ohci;
1209         int evt;
1210
1211         if (last->transfer_status == 0)
1212                 /* This descriptor isn't done yet, stop iteration. */
1213                 return 0;
1214
1215         driver_data = (struct driver_data *) &d[3];
1216         packet = driver_data->packet;
1217         if (packet == NULL)
1218                 /* This packet was cancelled, just continue. */
1219                 return 1;
1220
1221         if (packet->payload_mapped)
1222                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1223                                  packet->payload_length, DMA_TO_DEVICE);
1224
1225         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1226         packet->timestamp = le16_to_cpu(last->res_count);
1227
1228         log_ar_at_event('T', packet->speed, packet->header, evt);
1229
1230         switch (evt) {
1231         case OHCI1394_evt_timeout:
1232                 /* Async response transmit timed out. */
1233                 packet->ack = RCODE_CANCELLED;
1234                 break;
1235
1236         case OHCI1394_evt_flushed:
1237                 /*
1238                  * The packet was flushed should give same error as
1239                  * when we try to use a stale generation count.
1240                  */
1241                 packet->ack = RCODE_GENERATION;
1242                 break;
1243
1244         case OHCI1394_evt_missing_ack:
1245                 /*
1246                  * Using a valid (current) generation count, but the
1247                  * node is not on the bus or not sending acks.
1248                  */
1249                 packet->ack = RCODE_NO_ACK;
1250                 break;
1251
1252         case ACK_COMPLETE + 0x10:
1253         case ACK_PENDING + 0x10:
1254         case ACK_BUSY_X + 0x10:
1255         case ACK_BUSY_A + 0x10:
1256         case ACK_BUSY_B + 0x10:
1257         case ACK_DATA_ERROR + 0x10:
1258         case ACK_TYPE_ERROR + 0x10:
1259                 packet->ack = evt - 0x10;
1260                 break;
1261
1262         default:
1263                 packet->ack = RCODE_SEND_ERROR;
1264                 break;
1265         }
1266
1267         packet->callback(packet, &ohci->card, packet->ack);
1268
1269         return 1;
1270 }
1271
1272 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1273 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1274 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1275 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1276 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1277
1278 static void handle_local_rom(struct fw_ohci *ohci,
1279                              struct fw_packet *packet, u32 csr)
1280 {
1281         struct fw_packet response;
1282         int tcode, length, i;
1283
1284         tcode = HEADER_GET_TCODE(packet->header[0]);
1285         if (TCODE_IS_BLOCK_PACKET(tcode))
1286                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1287         else
1288                 length = 4;
1289
1290         i = csr - CSR_CONFIG_ROM;
1291         if (i + length > CONFIG_ROM_SIZE) {
1292                 fw_fill_response(&response, packet->header,
1293                                  RCODE_ADDRESS_ERROR, NULL, 0);
1294         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1295                 fw_fill_response(&response, packet->header,
1296                                  RCODE_TYPE_ERROR, NULL, 0);
1297         } else {
1298                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1299                                  (void *) ohci->config_rom + i, length);
1300         }
1301
1302         fw_core_handle_response(&ohci->card, &response);
1303 }
1304
1305 static void handle_local_lock(struct fw_ohci *ohci,
1306                               struct fw_packet *packet, u32 csr)
1307 {
1308         struct fw_packet response;
1309         int tcode, length, ext_tcode, sel, try;
1310         __be32 *payload, lock_old;
1311         u32 lock_arg, lock_data;
1312
1313         tcode = HEADER_GET_TCODE(packet->header[0]);
1314         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1315         payload = packet->payload;
1316         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1317
1318         if (tcode == TCODE_LOCK_REQUEST &&
1319             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1320                 lock_arg = be32_to_cpu(payload[0]);
1321                 lock_data = be32_to_cpu(payload[1]);
1322         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1323                 lock_arg = 0;
1324                 lock_data = 0;
1325         } else {
1326                 fw_fill_response(&response, packet->header,
1327                                  RCODE_TYPE_ERROR, NULL, 0);
1328                 goto out;
1329         }
1330
1331         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1332         reg_write(ohci, OHCI1394_CSRData, lock_data);
1333         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1334         reg_write(ohci, OHCI1394_CSRControl, sel);
1335
1336         for (try = 0; try < 20; try++)
1337                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1338                         lock_old = cpu_to_be32(reg_read(ohci,
1339                                                         OHCI1394_CSRData));
1340                         fw_fill_response(&response, packet->header,
1341                                          RCODE_COMPLETE,
1342                                          &lock_old, sizeof(lock_old));
1343                         goto out;
1344                 }
1345
1346         fw_error("swap not done (CSR lock timeout)\n");
1347         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1348
1349  out:
1350         fw_core_handle_response(&ohci->card, &response);
1351 }
1352
1353 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1354 {
1355         u64 offset, csr;
1356
1357         if (ctx == &ctx->ohci->at_request_ctx) {
1358                 packet->ack = ACK_PENDING;
1359                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1360         }
1361
1362         offset =
1363                 ((unsigned long long)
1364                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1365                 packet->header[2];
1366         csr = offset - CSR_REGISTER_BASE;
1367
1368         /* Handle config rom reads. */
1369         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1370                 handle_local_rom(ctx->ohci, packet, csr);
1371         else switch (csr) {
1372         case CSR_BUS_MANAGER_ID:
1373         case CSR_BANDWIDTH_AVAILABLE:
1374         case CSR_CHANNELS_AVAILABLE_HI:
1375         case CSR_CHANNELS_AVAILABLE_LO:
1376                 handle_local_lock(ctx->ohci, packet, csr);
1377                 break;
1378         default:
1379                 if (ctx == &ctx->ohci->at_request_ctx)
1380                         fw_core_handle_request(&ctx->ohci->card, packet);
1381                 else
1382                         fw_core_handle_response(&ctx->ohci->card, packet);
1383                 break;
1384         }
1385
1386         if (ctx == &ctx->ohci->at_response_ctx) {
1387                 packet->ack = ACK_COMPLETE;
1388                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1389         }
1390 }
1391
1392 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1393 {
1394         unsigned long flags;
1395         int ret;
1396
1397         spin_lock_irqsave(&ctx->ohci->lock, flags);
1398
1399         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1400             ctx->ohci->generation == packet->generation) {
1401                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1402                 handle_local_request(ctx, packet);
1403                 return;
1404         }
1405
1406         ret = at_context_queue_packet(ctx, packet);
1407         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1408
1409         if (ret < 0)
1410                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1411
1412 }
1413
1414 static u32 cycle_timer_ticks(u32 cycle_timer)
1415 {
1416         u32 ticks;
1417
1418         ticks = cycle_timer & 0xfff;
1419         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1420         ticks += (3072 * 8000) * (cycle_timer >> 25);
1421
1422         return ticks;
1423 }
1424
1425 /*
1426  * Some controllers exhibit one or more of the following bugs when updating the
1427  * iso cycle timer register:
1428  *  - When the lowest six bits are wrapping around to zero, a read that happens
1429  *    at the same time will return garbage in the lowest ten bits.
1430  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1431  *    not incremented for about 60 ns.
1432  *  - Occasionally, the entire register reads zero.
1433  *
1434  * To catch these, we read the register three times and ensure that the
1435  * difference between each two consecutive reads is approximately the same, i.e.
1436  * less than twice the other.  Furthermore, any negative difference indicates an
1437  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1438  * execute, so we have enough precision to compute the ratio of the differences.)
1439  */
1440 static u32 get_cycle_time(struct fw_ohci *ohci)
1441 {
1442         u32 c0, c1, c2;
1443         u32 t0, t1, t2;
1444         s32 diff01, diff12;
1445         int i;
1446
1447         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1448
1449         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1450                 i = 0;
1451                 c1 = c2;
1452                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1453                 do {
1454                         c0 = c1;
1455                         c1 = c2;
1456                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1457                         t0 = cycle_timer_ticks(c0);
1458                         t1 = cycle_timer_ticks(c1);
1459                         t2 = cycle_timer_ticks(c2);
1460                         diff01 = t1 - t0;
1461                         diff12 = t2 - t1;
1462                 } while ((diff01 <= 0 || diff12 <= 0 ||
1463                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1464                          && i++ < 20);
1465         }
1466
1467         return c2;
1468 }
1469
1470 /*
1471  * This function has to be called at least every 64 seconds.  The bus_time
1472  * field stores not only the upper 25 bits of the BUS_TIME register but also
1473  * the most significant bit of the cycle timer in bit 6 so that we can detect
1474  * changes in this bit.
1475  */
1476 static u32 update_bus_time(struct fw_ohci *ohci)
1477 {
1478         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1479
1480         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1481                 ohci->bus_time += 0x40;
1482
1483         return ohci->bus_time | cycle_time_seconds;
1484 }
1485
1486 static void bus_reset_tasklet(unsigned long data)
1487 {
1488         struct fw_ohci *ohci = (struct fw_ohci *)data;
1489         int self_id_count, i, j, reg;
1490         int generation, new_generation;
1491         unsigned long flags;
1492         void *free_rom = NULL;
1493         dma_addr_t free_rom_bus = 0;
1494         bool is_new_root;
1495
1496         reg = reg_read(ohci, OHCI1394_NodeID);
1497         if (!(reg & OHCI1394_NodeID_idValid)) {
1498                 fw_notify("node ID not valid, new bus reset in progress\n");
1499                 return;
1500         }
1501         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1502                 fw_notify("malconfigured bus\n");
1503                 return;
1504         }
1505         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1506                                OHCI1394_NodeID_nodeNumber);
1507
1508         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1509         if (!(ohci->is_root && is_new_root))
1510                 reg_write(ohci, OHCI1394_LinkControlSet,
1511                           OHCI1394_LinkControl_cycleMaster);
1512         ohci->is_root = is_new_root;
1513
1514         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1515         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1516                 fw_notify("inconsistent self IDs\n");
1517                 return;
1518         }
1519         /*
1520          * The count in the SelfIDCount register is the number of
1521          * bytes in the self ID receive buffer.  Since we also receive
1522          * the inverted quadlets and a header quadlet, we shift one
1523          * bit extra to get the actual number of self IDs.
1524          */
1525         self_id_count = (reg >> 3) & 0xff;
1526         if (self_id_count == 0 || self_id_count > 252) {
1527                 fw_notify("inconsistent self IDs\n");
1528                 return;
1529         }
1530         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1531         rmb();
1532
1533         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1534                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1535                         fw_notify("inconsistent self IDs\n");
1536                         return;
1537                 }
1538                 ohci->self_id_buffer[j] =
1539                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1540         }
1541         rmb();
1542
1543         /*
1544          * Check the consistency of the self IDs we just read.  The
1545          * problem we face is that a new bus reset can start while we
1546          * read out the self IDs from the DMA buffer. If this happens,
1547          * the DMA buffer will be overwritten with new self IDs and we
1548          * will read out inconsistent data.  The OHCI specification
1549          * (section 11.2) recommends a technique similar to
1550          * linux/seqlock.h, where we remember the generation of the
1551          * self IDs in the buffer before reading them out and compare
1552          * it to the current generation after reading them out.  If
1553          * the two generations match we know we have a consistent set
1554          * of self IDs.
1555          */
1556
1557         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1558         if (new_generation != generation) {
1559                 fw_notify("recursive bus reset detected, "
1560                           "discarding self ids\n");
1561                 return;
1562         }
1563
1564         /* FIXME: Document how the locking works. */
1565         spin_lock_irqsave(&ohci->lock, flags);
1566
1567         ohci->generation = generation;
1568         context_stop(&ohci->at_request_ctx);
1569         context_stop(&ohci->at_response_ctx);
1570         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1571
1572         if (ohci->quirks & QUIRK_RESET_PACKET)
1573                 ohci->request_generation = generation;
1574
1575         /*
1576          * This next bit is unrelated to the AT context stuff but we
1577          * have to do it under the spinlock also.  If a new config rom
1578          * was set up before this reset, the old one is now no longer
1579          * in use and we can free it. Update the config rom pointers
1580          * to point to the current config rom and clear the
1581          * next_config_rom pointer so a new update can take place.
1582          */
1583
1584         if (ohci->next_config_rom != NULL) {
1585                 if (ohci->next_config_rom != ohci->config_rom) {
1586                         free_rom      = ohci->config_rom;
1587                         free_rom_bus  = ohci->config_rom_bus;
1588                 }
1589                 ohci->config_rom      = ohci->next_config_rom;
1590                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1591                 ohci->next_config_rom = NULL;
1592
1593                 /*
1594                  * Restore config_rom image and manually update
1595                  * config_rom registers.  Writing the header quadlet
1596                  * will indicate that the config rom is ready, so we
1597                  * do that last.
1598                  */
1599                 reg_write(ohci, OHCI1394_BusOptions,
1600                           be32_to_cpu(ohci->config_rom[2]));
1601                 ohci->config_rom[0] = ohci->next_header;
1602                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1603                           be32_to_cpu(ohci->next_header));
1604         }
1605
1606 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1607         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1608         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1609 #endif
1610
1611         spin_unlock_irqrestore(&ohci->lock, flags);
1612
1613         if (free_rom)
1614                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1615                                   free_rom, free_rom_bus);
1616
1617         log_selfids(ohci->node_id, generation,
1618                     self_id_count, ohci->self_id_buffer);
1619
1620         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1621                                  self_id_count, ohci->self_id_buffer,
1622                                  ohci->csr_state_setclear_abdicate);
1623         ohci->csr_state_setclear_abdicate = false;
1624 }
1625
1626 static irqreturn_t irq_handler(int irq, void *data)
1627 {
1628         struct fw_ohci *ohci = data;
1629         u32 event, iso_event;
1630         int i;
1631
1632         event = reg_read(ohci, OHCI1394_IntEventClear);
1633
1634         if (!event || !~event)
1635                 return IRQ_NONE;
1636
1637         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1638         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1639         log_irqs(event);
1640
1641         if (event & OHCI1394_selfIDComplete)
1642                 tasklet_schedule(&ohci->bus_reset_tasklet);
1643
1644         if (event & OHCI1394_RQPkt)
1645                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1646
1647         if (event & OHCI1394_RSPkt)
1648                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1649
1650         if (event & OHCI1394_reqTxComplete)
1651                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1652
1653         if (event & OHCI1394_respTxComplete)
1654                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1655
1656         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1657         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1658
1659         while (iso_event) {
1660                 i = ffs(iso_event) - 1;
1661                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1662                 iso_event &= ~(1 << i);
1663         }
1664
1665         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1666         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1667
1668         while (iso_event) {
1669                 i = ffs(iso_event) - 1;
1670                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1671                 iso_event &= ~(1 << i);
1672         }
1673
1674         if (unlikely(event & OHCI1394_regAccessFail))
1675                 fw_error("Register access failure - "
1676                          "please notify linux1394-devel@lists.sf.net\n");
1677
1678         if (unlikely(event & OHCI1394_postedWriteErr))
1679                 fw_error("PCI posted write error\n");
1680
1681         if (unlikely(event & OHCI1394_cycleTooLong)) {
1682                 if (printk_ratelimit())
1683                         fw_notify("isochronous cycle too long\n");
1684                 reg_write(ohci, OHCI1394_LinkControlSet,
1685                           OHCI1394_LinkControl_cycleMaster);
1686         }
1687
1688         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1689                 /*
1690                  * We need to clear this event bit in order to make
1691                  * cycleMatch isochronous I/O work.  In theory we should
1692                  * stop active cycleMatch iso contexts now and restart
1693                  * them at least two cycles later.  (FIXME?)
1694                  */
1695                 if (printk_ratelimit())
1696                         fw_notify("isochronous cycle inconsistent\n");
1697         }
1698
1699         if (event & OHCI1394_cycle64Seconds) {
1700                 spin_lock(&ohci->lock);
1701                 update_bus_time(ohci);
1702                 spin_unlock(&ohci->lock);
1703         }
1704
1705         return IRQ_HANDLED;
1706 }
1707
1708 static int software_reset(struct fw_ohci *ohci)
1709 {
1710         int i;
1711
1712         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1713
1714         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1715                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1716                      OHCI1394_HCControl_softReset) == 0)
1717                         return 0;
1718                 msleep(1);
1719         }
1720
1721         return -EBUSY;
1722 }
1723
1724 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1725 {
1726         size_t size = length * 4;
1727
1728         memcpy(dest, src, size);
1729         if (size < CONFIG_ROM_SIZE)
1730                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1731 }
1732
1733 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1734 {
1735         bool enable_1394a;
1736         int ret, clear, set, offset;
1737
1738         /* Check if the driver should configure link and PHY. */
1739         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1740               OHCI1394_HCControl_programPhyEnable))
1741                 return 0;
1742
1743         /* Paranoia: check whether the PHY supports 1394a, too. */
1744         enable_1394a = false;
1745         ret = read_phy_reg(ohci, 2);
1746         if (ret < 0)
1747                 return ret;
1748         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1749                 ret = read_paged_phy_reg(ohci, 1, 8);
1750                 if (ret < 0)
1751                         return ret;
1752                 if (ret >= 1)
1753                         enable_1394a = true;
1754         }
1755
1756         if (ohci->quirks & QUIRK_NO_1394A)
1757                 enable_1394a = false;
1758
1759         /* Configure PHY and link consistently. */
1760         if (enable_1394a) {
1761                 clear = 0;
1762                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1763         } else {
1764                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1765                 set = 0;
1766         }
1767         ret = update_phy_reg(ohci, 5, clear, set);
1768         if (ret < 0)
1769                 return ret;
1770
1771         if (enable_1394a)
1772                 offset = OHCI1394_HCControlSet;
1773         else
1774                 offset = OHCI1394_HCControlClear;
1775         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1776
1777         /* Clean up: configuration has been taken care of. */
1778         reg_write(ohci, OHCI1394_HCControlClear,
1779                   OHCI1394_HCControl_programPhyEnable);
1780
1781         return 0;
1782 }
1783
1784 static int ohci_enable(struct fw_card *card,
1785                        const __be32 *config_rom, size_t length)
1786 {
1787         struct fw_ohci *ohci = fw_ohci(card);
1788         struct pci_dev *dev = to_pci_dev(card->device);
1789         u32 lps, seconds, version, irqs;
1790         int i, ret;
1791
1792         if (software_reset(ohci)) {
1793                 fw_error("Failed to reset ohci card.\n");
1794                 return -EBUSY;
1795         }
1796
1797         /*
1798          * Now enable LPS, which we need in order to start accessing
1799          * most of the registers.  In fact, on some cards (ALI M5251),
1800          * accessing registers in the SClk domain without LPS enabled
1801          * will lock up the machine.  Wait 50msec to make sure we have
1802          * full link enabled.  However, with some cards (well, at least
1803          * a JMicron PCIe card), we have to try again sometimes.
1804          */
1805         reg_write(ohci, OHCI1394_HCControlSet,
1806                   OHCI1394_HCControl_LPS |
1807                   OHCI1394_HCControl_postedWriteEnable);
1808         flush_writes(ohci);
1809
1810         for (lps = 0, i = 0; !lps && i < 3; i++) {
1811                 msleep(50);
1812                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1813                       OHCI1394_HCControl_LPS;
1814         }
1815
1816         if (!lps) {
1817                 fw_error("Failed to set Link Power Status\n");
1818                 return -EIO;
1819         }
1820
1821         reg_write(ohci, OHCI1394_HCControlClear,
1822                   OHCI1394_HCControl_noByteSwapData);
1823
1824         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1825         reg_write(ohci, OHCI1394_LinkControlSet,
1826                   OHCI1394_LinkControl_rcvSelfID |
1827                   OHCI1394_LinkControl_rcvPhyPkt |
1828                   OHCI1394_LinkControl_cycleTimerEnable |
1829                   OHCI1394_LinkControl_cycleMaster);
1830
1831         reg_write(ohci, OHCI1394_ATRetries,
1832                   OHCI1394_MAX_AT_REQ_RETRIES |
1833                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1834                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1835                   (200 << 16));
1836
1837         seconds = lower_32_bits(get_seconds());
1838         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1839         ohci->bus_time = seconds & ~0x3f;
1840
1841         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1842         if (version >= OHCI_VERSION_1_1) {
1843                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1844                           0xfffffffe);
1845                 card->broadcast_channel_auto_allocated = true;
1846         }
1847
1848         /* Get implemented bits of the priority arbitration request counter. */
1849         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1850         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1851         reg_write(ohci, OHCI1394_FairnessControl, 0);
1852         card->priority_budget_implemented = ohci->pri_req_max != 0;
1853
1854         ar_context_run(&ohci->ar_request_ctx);
1855         ar_context_run(&ohci->ar_response_ctx);
1856
1857         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1858         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1859         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1860
1861         ret = configure_1394a_enhancements(ohci);
1862         if (ret < 0)
1863                 return ret;
1864
1865         /* Activate link_on bit and contender bit in our self ID packets.*/
1866         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1867         if (ret < 0)
1868                 return ret;
1869
1870         /*
1871          * When the link is not yet enabled, the atomic config rom
1872          * update mechanism described below in ohci_set_config_rom()
1873          * is not active.  We have to update ConfigRomHeader and
1874          * BusOptions manually, and the write to ConfigROMmap takes
1875          * effect immediately.  We tie this to the enabling of the
1876          * link, so we have a valid config rom before enabling - the
1877          * OHCI requires that ConfigROMhdr and BusOptions have valid
1878          * values before enabling.
1879          *
1880          * However, when the ConfigROMmap is written, some controllers
1881          * always read back quadlets 0 and 2 from the config rom to
1882          * the ConfigRomHeader and BusOptions registers on bus reset.
1883          * They shouldn't do that in this initial case where the link
1884          * isn't enabled.  This means we have to use the same
1885          * workaround here, setting the bus header to 0 and then write
1886          * the right values in the bus reset tasklet.
1887          */
1888
1889         if (config_rom) {
1890                 ohci->next_config_rom =
1891                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1892                                            &ohci->next_config_rom_bus,
1893                                            GFP_KERNEL);
1894                 if (ohci->next_config_rom == NULL)
1895                         return -ENOMEM;
1896
1897                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1898         } else {
1899                 /*
1900                  * In the suspend case, config_rom is NULL, which
1901                  * means that we just reuse the old config rom.
1902                  */
1903                 ohci->next_config_rom = ohci->config_rom;
1904                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1905         }
1906
1907         ohci->next_header = ohci->next_config_rom[0];
1908         ohci->next_config_rom[0] = 0;
1909         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1910         reg_write(ohci, OHCI1394_BusOptions,
1911                   be32_to_cpu(ohci->next_config_rom[2]));
1912         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1913
1914         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1915
1916         if (!(ohci->quirks & QUIRK_NO_MSI))
1917                 pci_enable_msi(dev);
1918         if (request_irq(dev->irq, irq_handler,
1919                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1920                         ohci_driver_name, ohci)) {
1921                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1922                 pci_disable_msi(dev);
1923                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1924                                   ohci->config_rom, ohci->config_rom_bus);
1925                 return -EIO;
1926         }
1927
1928         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1929                 OHCI1394_RQPkt | OHCI1394_RSPkt |
1930                 OHCI1394_isochTx | OHCI1394_isochRx |
1931                 OHCI1394_postedWriteErr |
1932                 OHCI1394_selfIDComplete |
1933                 OHCI1394_regAccessFail |
1934                 OHCI1394_cycle64Seconds |
1935                 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1936                 OHCI1394_masterIntEnable;
1937         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1938                 irqs |= OHCI1394_busReset;
1939         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1940
1941         reg_write(ohci, OHCI1394_HCControlSet,
1942                   OHCI1394_HCControl_linkEnable |
1943                   OHCI1394_HCControl_BIBimageValid);
1944         flush_writes(ohci);
1945
1946         /* We are ready to go, reset bus to finish initialization. */
1947         fw_schedule_bus_reset(&ohci->card, false, true);
1948
1949         return 0;
1950 }
1951
1952 static int ohci_set_config_rom(struct fw_card *card,
1953                                const __be32 *config_rom, size_t length)
1954 {
1955         struct fw_ohci *ohci;
1956         unsigned long flags;
1957         int ret = -EBUSY;
1958         __be32 *next_config_rom;
1959         dma_addr_t uninitialized_var(next_config_rom_bus);
1960
1961         ohci = fw_ohci(card);
1962
1963         /*
1964          * When the OHCI controller is enabled, the config rom update
1965          * mechanism is a bit tricky, but easy enough to use.  See
1966          * section 5.5.6 in the OHCI specification.
1967          *
1968          * The OHCI controller caches the new config rom address in a
1969          * shadow register (ConfigROMmapNext) and needs a bus reset
1970          * for the changes to take place.  When the bus reset is
1971          * detected, the controller loads the new values for the
1972          * ConfigRomHeader and BusOptions registers from the specified
1973          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1974          * shadow register. All automatically and atomically.
1975          *
1976          * Now, there's a twist to this story.  The automatic load of
1977          * ConfigRomHeader and BusOptions doesn't honor the
1978          * noByteSwapData bit, so with a be32 config rom, the
1979          * controller will load be32 values in to these registers
1980          * during the atomic update, even on litte endian
1981          * architectures.  The workaround we use is to put a 0 in the
1982          * header quadlet; 0 is endian agnostic and means that the
1983          * config rom isn't ready yet.  In the bus reset tasklet we
1984          * then set up the real values for the two registers.
1985          *
1986          * We use ohci->lock to avoid racing with the code that sets
1987          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1988          */
1989
1990         next_config_rom =
1991                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1992                                    &next_config_rom_bus, GFP_KERNEL);
1993         if (next_config_rom == NULL)
1994                 return -ENOMEM;
1995
1996         spin_lock_irqsave(&ohci->lock, flags);
1997
1998         if (ohci->next_config_rom == NULL) {
1999                 ohci->next_config_rom = next_config_rom;
2000                 ohci->next_config_rom_bus = next_config_rom_bus;
2001
2002                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2003
2004                 ohci->next_header = config_rom[0];
2005                 ohci->next_config_rom[0] = 0;
2006
2007                 reg_write(ohci, OHCI1394_ConfigROMmap,
2008                           ohci->next_config_rom_bus);
2009                 ret = 0;
2010         }
2011
2012         spin_unlock_irqrestore(&ohci->lock, flags);
2013
2014         /*
2015          * Now initiate a bus reset to have the changes take
2016          * effect. We clean up the old config rom memory and DMA
2017          * mappings in the bus reset tasklet, since the OHCI
2018          * controller could need to access it before the bus reset
2019          * takes effect.
2020          */
2021         if (ret == 0)
2022                 fw_schedule_bus_reset(&ohci->card, true, true);
2023         else
2024                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2025                                   next_config_rom, next_config_rom_bus);
2026
2027         return ret;
2028 }
2029
2030 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2031 {
2032         struct fw_ohci *ohci = fw_ohci(card);
2033
2034         at_context_transmit(&ohci->at_request_ctx, packet);
2035 }
2036
2037 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2038 {
2039         struct fw_ohci *ohci = fw_ohci(card);
2040
2041         at_context_transmit(&ohci->at_response_ctx, packet);
2042 }
2043
2044 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2045 {
2046         struct fw_ohci *ohci = fw_ohci(card);
2047         struct context *ctx = &ohci->at_request_ctx;
2048         struct driver_data *driver_data = packet->driver_data;
2049         int ret = -ENOENT;
2050
2051         tasklet_disable(&ctx->tasklet);
2052
2053         if (packet->ack != 0)
2054                 goto out;
2055
2056         if (packet->payload_mapped)
2057                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2058                                  packet->payload_length, DMA_TO_DEVICE);
2059
2060         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2061         driver_data->packet = NULL;
2062         packet->ack = RCODE_CANCELLED;
2063         packet->callback(packet, &ohci->card, packet->ack);
2064         ret = 0;
2065  out:
2066         tasklet_enable(&ctx->tasklet);
2067
2068         return ret;
2069 }
2070
2071 static int ohci_enable_phys_dma(struct fw_card *card,
2072                                 int node_id, int generation)
2073 {
2074 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2075         return 0;
2076 #else
2077         struct fw_ohci *ohci = fw_ohci(card);
2078         unsigned long flags;
2079         int n, ret = 0;
2080
2081         /*
2082          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2083          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2084          */
2085
2086         spin_lock_irqsave(&ohci->lock, flags);
2087
2088         if (ohci->generation != generation) {
2089                 ret = -ESTALE;
2090                 goto out;
2091         }
2092
2093         /*
2094          * Note, if the node ID contains a non-local bus ID, physical DMA is
2095          * enabled for _all_ nodes on remote buses.
2096          */
2097
2098         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2099         if (n < 32)
2100                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2101         else
2102                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2103
2104         flush_writes(ohci);
2105  out:
2106         spin_unlock_irqrestore(&ohci->lock, flags);
2107
2108         return ret;
2109 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2110 }
2111
2112 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2113 {
2114         struct fw_ohci *ohci = fw_ohci(card);
2115         unsigned long flags;
2116         u32 value;
2117
2118         switch (csr_offset) {
2119         case CSR_STATE_CLEAR:
2120         case CSR_STATE_SET:
2121                 if (ohci->is_root &&
2122                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2123                      OHCI1394_LinkControl_cycleMaster))
2124                         value = CSR_STATE_BIT_CMSTR;
2125                 else
2126                         value = 0;
2127                 if (ohci->csr_state_setclear_abdicate)
2128                         value |= CSR_STATE_BIT_ABDICATE;
2129
2130                 return value;
2131
2132         case CSR_NODE_IDS:
2133                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2134
2135         case CSR_CYCLE_TIME:
2136                 return get_cycle_time(ohci);
2137
2138         case CSR_BUS_TIME:
2139                 /*
2140                  * We might be called just after the cycle timer has wrapped
2141                  * around but just before the cycle64Seconds handler, so we
2142                  * better check here, too, if the bus time needs to be updated.
2143                  */
2144                 spin_lock_irqsave(&ohci->lock, flags);
2145                 value = update_bus_time(ohci);
2146                 spin_unlock_irqrestore(&ohci->lock, flags);
2147                 return value;
2148
2149         case CSR_BUSY_TIMEOUT:
2150                 value = reg_read(ohci, OHCI1394_ATRetries);
2151                 return (value >> 4) & 0x0ffff00f;
2152
2153         case CSR_PRIORITY_BUDGET:
2154                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2155                         (ohci->pri_req_max << 8);
2156
2157         default:
2158                 WARN_ON(1);
2159                 return 0;
2160         }
2161 }
2162
2163 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2164 {
2165         struct fw_ohci *ohci = fw_ohci(card);
2166         unsigned long flags;
2167
2168         switch (csr_offset) {
2169         case CSR_STATE_CLEAR:
2170                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2171                         reg_write(ohci, OHCI1394_LinkControlClear,
2172                                   OHCI1394_LinkControl_cycleMaster);
2173                         flush_writes(ohci);
2174                 }
2175                 if (value & CSR_STATE_BIT_ABDICATE)
2176                         ohci->csr_state_setclear_abdicate = false;
2177                 break;
2178
2179         case CSR_STATE_SET:
2180                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2181                         reg_write(ohci, OHCI1394_LinkControlSet,
2182                                   OHCI1394_LinkControl_cycleMaster);
2183                         flush_writes(ohci);
2184                 }
2185                 if (value & CSR_STATE_BIT_ABDICATE)
2186                         ohci->csr_state_setclear_abdicate = true;
2187                 break;
2188
2189         case CSR_NODE_IDS:
2190                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2191                 flush_writes(ohci);
2192                 break;
2193
2194         case CSR_CYCLE_TIME:
2195                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2196                 reg_write(ohci, OHCI1394_IntEventSet,
2197                           OHCI1394_cycleInconsistent);
2198                 flush_writes(ohci);
2199                 break;
2200
2201         case CSR_BUS_TIME:
2202                 spin_lock_irqsave(&ohci->lock, flags);
2203                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2204                 spin_unlock_irqrestore(&ohci->lock, flags);
2205                 break;
2206
2207         case CSR_BUSY_TIMEOUT:
2208                 value = (value & 0xf) | ((value & 0xf) << 4) |
2209                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2210                 reg_write(ohci, OHCI1394_ATRetries, value);
2211                 flush_writes(ohci);
2212                 break;
2213
2214         case CSR_PRIORITY_BUDGET:
2215                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2216                 flush_writes(ohci);
2217                 break;
2218
2219         default:
2220                 WARN_ON(1);
2221                 break;
2222         }
2223 }
2224
2225 static void copy_iso_headers(struct iso_context *ctx, void *p)
2226 {
2227         int i = ctx->header_length;
2228
2229         if (i + ctx->base.header_size > PAGE_SIZE)
2230                 return;
2231
2232         /*
2233          * The iso header is byteswapped to little endian by
2234          * the controller, but the remaining header quadlets
2235          * are big endian.  We want to present all the headers
2236          * as big endian, so we have to swap the first quadlet.
2237          */
2238         if (ctx->base.header_size > 0)
2239                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2240         if (ctx->base.header_size > 4)
2241                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2242         if (ctx->base.header_size > 8)
2243                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2244         ctx->header_length += ctx->base.header_size;
2245 }
2246
2247 static int handle_ir_packet_per_buffer(struct context *context,
2248                                        struct descriptor *d,
2249                                        struct descriptor *last)
2250 {
2251         struct iso_context *ctx =
2252                 container_of(context, struct iso_context, context);
2253         struct descriptor *pd;
2254         __le32 *ir_header;
2255         void *p;
2256
2257         for (pd = d; pd <= last; pd++)
2258                 if (pd->transfer_status)
2259                         break;
2260         if (pd > last)
2261                 /* Descriptor(s) not done yet, stop iteration */
2262                 return 0;
2263
2264         p = last + 1;
2265         copy_iso_headers(ctx, p);
2266
2267         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2268                 ir_header = (__le32 *) p;
2269                 ctx->base.callback.sc(&ctx->base,
2270                                       le32_to_cpu(ir_header[0]) & 0xffff,
2271                                       ctx->header_length, ctx->header,
2272                                       ctx->base.callback_data);
2273                 ctx->header_length = 0;
2274         }
2275
2276         return 1;
2277 }
2278
2279 /* d == last because each descriptor block is only a single descriptor. */
2280 static int handle_ir_buffer_fill(struct context *context,
2281                                  struct descriptor *d,
2282                                  struct descriptor *last)
2283 {
2284         struct iso_context *ctx =
2285                 container_of(context, struct iso_context, context);
2286
2287         if (!last->transfer_status)
2288                 /* Descriptor(s) not done yet, stop iteration */
2289                 return 0;
2290
2291         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2292                 ctx->base.callback.mc(&ctx->base,
2293                                       le32_to_cpu(last->data_address) +
2294                                       le16_to_cpu(last->req_count) -
2295                                       le16_to_cpu(last->res_count),
2296                                       ctx->base.callback_data);
2297
2298         return 1;
2299 }
2300
2301 static int handle_it_packet(struct context *context,
2302                             struct descriptor *d,
2303                             struct descriptor *last)
2304 {
2305         struct iso_context *ctx =
2306                 container_of(context, struct iso_context, context);
2307         int i;
2308         struct descriptor *pd;
2309
2310         for (pd = d; pd <= last; pd++)
2311                 if (pd->transfer_status)
2312                         break;
2313         if (pd > last)
2314                 /* Descriptor(s) not done yet, stop iteration */
2315                 return 0;
2316
2317         i = ctx->header_length;
2318         if (i + 4 < PAGE_SIZE) {
2319                 /* Present this value as big-endian to match the receive code */
2320                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2321                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2322                                 le16_to_cpu(pd->res_count));
2323                 ctx->header_length += 4;
2324         }
2325         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2326                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2327                                       ctx->header_length, ctx->header,
2328                                       ctx->base.callback_data);
2329                 ctx->header_length = 0;
2330         }
2331         return 1;
2332 }
2333
2334 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2335 {
2336         u32 hi = channels >> 32, lo = channels;
2337
2338         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2339         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2340         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2341         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2342         mmiowb();
2343         ohci->mc_channels = channels;
2344 }
2345
2346 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2347                                 int type, int channel, size_t header_size)
2348 {
2349         struct fw_ohci *ohci = fw_ohci(card);
2350         struct iso_context *uninitialized_var(ctx);
2351         descriptor_callback_t uninitialized_var(callback);
2352         u64 *uninitialized_var(channels);
2353         u32 *uninitialized_var(mask), uninitialized_var(regs);
2354         unsigned long flags;
2355         int index, ret = -EBUSY;
2356
2357         spin_lock_irqsave(&ohci->lock, flags);
2358
2359         switch (type) {
2360         case FW_ISO_CONTEXT_TRANSMIT:
2361                 mask     = &ohci->it_context_mask;
2362                 callback = handle_it_packet;
2363                 index    = ffs(*mask) - 1;
2364                 if (index >= 0) {
2365                         *mask &= ~(1 << index);
2366                         regs = OHCI1394_IsoXmitContextBase(index);
2367                         ctx  = &ohci->it_context_list[index];
2368                 }
2369                 break;
2370
2371         case FW_ISO_CONTEXT_RECEIVE:
2372                 channels = &ohci->ir_context_channels;
2373                 mask     = &ohci->ir_context_mask;
2374                 callback = handle_ir_packet_per_buffer;
2375                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2376                 if (index >= 0) {
2377                         *channels &= ~(1ULL << channel);
2378                         *mask     &= ~(1 << index);
2379                         regs = OHCI1394_IsoRcvContextBase(index);
2380                         ctx  = &ohci->ir_context_list[index];
2381                 }
2382                 break;
2383
2384         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2385                 mask     = &ohci->ir_context_mask;
2386                 callback = handle_ir_buffer_fill;
2387                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2388                 if (index >= 0) {
2389                         ohci->mc_allocated = true;
2390                         *mask &= ~(1 << index);
2391                         regs = OHCI1394_IsoRcvContextBase(index);
2392                         ctx  = &ohci->ir_context_list[index];
2393                 }
2394                 break;
2395
2396         default:
2397                 index = -1;
2398                 ret = -ENOSYS;
2399         }
2400
2401         spin_unlock_irqrestore(&ohci->lock, flags);
2402
2403         if (index < 0)
2404                 return ERR_PTR(ret);
2405
2406         memset(ctx, 0, sizeof(*ctx));
2407         ctx->header_length = 0;
2408         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2409         if (ctx->header == NULL) {
2410                 ret = -ENOMEM;
2411                 goto out;
2412         }
2413         ret = context_init(&ctx->context, ohci, regs, callback);
2414         if (ret < 0)
2415                 goto out_with_header;
2416
2417         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2418                 set_multichannel_mask(ohci, 0);
2419
2420         return &ctx->base;
2421
2422  out_with_header:
2423         free_page((unsigned long)ctx->header);
2424  out:
2425         spin_lock_irqsave(&ohci->lock, flags);
2426
2427         switch (type) {
2428         case FW_ISO_CONTEXT_RECEIVE:
2429                 *channels |= 1ULL << channel;
2430                 break;
2431
2432         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2433                 ohci->mc_allocated = false;
2434                 break;
2435         }
2436         *mask |= 1 << index;
2437
2438         spin_unlock_irqrestore(&ohci->lock, flags);
2439
2440         return ERR_PTR(ret);
2441 }
2442
2443 static int ohci_start_iso(struct fw_iso_context *base,
2444                           s32 cycle, u32 sync, u32 tags)
2445 {
2446         struct iso_context *ctx = container_of(base, struct iso_context, base);
2447         struct fw_ohci *ohci = ctx->context.ohci;
2448         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2449         int index;
2450
2451         switch (ctx->base.type) {
2452         case FW_ISO_CONTEXT_TRANSMIT:
2453                 index = ctx - ohci->it_context_list;
2454                 match = 0;
2455                 if (cycle >= 0)
2456                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2457                                 (cycle & 0x7fff) << 16;
2458
2459                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2460                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2461                 context_run(&ctx->context, match);
2462                 break;
2463
2464         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2465                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2466                 /* fall through */
2467         case FW_ISO_CONTEXT_RECEIVE:
2468                 index = ctx - ohci->ir_context_list;
2469                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2470                 if (cycle >= 0) {
2471                         match |= (cycle & 0x07fff) << 12;
2472                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2473                 }
2474
2475                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2476                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2477                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2478                 context_run(&ctx->context, control);
2479                 break;
2480         }
2481
2482         return 0;
2483 }
2484
2485 static int ohci_stop_iso(struct fw_iso_context *base)
2486 {
2487         struct fw_ohci *ohci = fw_ohci(base->card);
2488         struct iso_context *ctx = container_of(base, struct iso_context, base);
2489         int index;
2490
2491         switch (ctx->base.type) {
2492         case FW_ISO_CONTEXT_TRANSMIT:
2493                 index = ctx - ohci->it_context_list;
2494                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2495                 break;
2496
2497         case FW_ISO_CONTEXT_RECEIVE:
2498         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2499                 index = ctx - ohci->ir_context_list;
2500                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2501                 break;
2502         }
2503         flush_writes(ohci);
2504         context_stop(&ctx->context);
2505
2506         return 0;
2507 }
2508
2509 static void ohci_free_iso_context(struct fw_iso_context *base)
2510 {
2511         struct fw_ohci *ohci = fw_ohci(base->card);
2512         struct iso_context *ctx = container_of(base, struct iso_context, base);
2513         unsigned long flags;
2514         int index;
2515
2516         ohci_stop_iso(base);
2517         context_release(&ctx->context);
2518         free_page((unsigned long)ctx->header);
2519
2520         spin_lock_irqsave(&ohci->lock, flags);
2521
2522         switch (base->type) {
2523         case FW_ISO_CONTEXT_TRANSMIT:
2524                 index = ctx - ohci->it_context_list;
2525                 ohci->it_context_mask |= 1 << index;
2526                 break;
2527
2528         case FW_ISO_CONTEXT_RECEIVE:
2529                 index = ctx - ohci->ir_context_list;
2530                 ohci->ir_context_mask |= 1 << index;
2531                 ohci->ir_context_channels |= 1ULL << base->channel;
2532                 break;
2533
2534         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2535                 index = ctx - ohci->ir_context_list;
2536                 ohci->ir_context_mask |= 1 << index;
2537                 ohci->ir_context_channels |= ohci->mc_channels;
2538                 ohci->mc_channels = 0;
2539                 ohci->mc_allocated = false;
2540                 break;
2541         }
2542
2543         spin_unlock_irqrestore(&ohci->lock, flags);
2544 }
2545
2546 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2547 {
2548         struct fw_ohci *ohci = fw_ohci(base->card);
2549         unsigned long flags;
2550         int ret;
2551
2552         switch (base->type) {
2553         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2554
2555                 spin_lock_irqsave(&ohci->lock, flags);
2556
2557                 /* Don't allow multichannel to grab other contexts' channels. */
2558                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2559                         *channels = ohci->ir_context_channels;
2560                         ret = -EBUSY;
2561                 } else {
2562                         set_multichannel_mask(ohci, *channels);
2563                         ret = 0;
2564                 }
2565
2566                 spin_unlock_irqrestore(&ohci->lock, flags);
2567
2568                 break;
2569         default:
2570                 ret = -EINVAL;
2571         }
2572
2573         return ret;
2574 }
2575
2576 static int queue_iso_transmit(struct iso_context *ctx,
2577                               struct fw_iso_packet *packet,
2578                               struct fw_iso_buffer *buffer,
2579                               unsigned long payload)
2580 {
2581         struct descriptor *d, *last, *pd;
2582         struct fw_iso_packet *p;
2583         __le32 *header;
2584         dma_addr_t d_bus, page_bus;
2585         u32 z, header_z, payload_z, irq;
2586         u32 payload_index, payload_end_index, next_page_index;
2587         int page, end_page, i, length, offset;
2588
2589         p = packet;
2590         payload_index = payload;
2591
2592         if (p->skip)
2593                 z = 1;
2594         else
2595                 z = 2;
2596         if (p->header_length > 0)
2597                 z++;
2598
2599         /* Determine the first page the payload isn't contained in. */
2600         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2601         if (p->payload_length > 0)
2602                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2603         else
2604                 payload_z = 0;
2605
2606         z += payload_z;
2607
2608         /* Get header size in number of descriptors. */
2609         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2610
2611         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2612         if (d == NULL)
2613                 return -ENOMEM;
2614
2615         if (!p->skip) {
2616                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2617                 d[0].req_count = cpu_to_le16(8);
2618                 /*
2619                  * Link the skip address to this descriptor itself.  This causes
2620                  * a context to skip a cycle whenever lost cycles or FIFO
2621                  * overruns occur, without dropping the data.  The application
2622                  * should then decide whether this is an error condition or not.
2623                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2624                  */
2625                 d[0].branch_address = cpu_to_le32(d_bus | z);
2626
2627                 header = (__le32 *) &d[1];
2628                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2629                                         IT_HEADER_TAG(p->tag) |
2630                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2631                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2632                                         IT_HEADER_SPEED(ctx->base.speed));
2633                 header[1] =
2634                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2635                                                           p->payload_length));
2636         }
2637
2638         if (p->header_length > 0) {
2639                 d[2].req_count    = cpu_to_le16(p->header_length);
2640                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2641                 memcpy(&d[z], p->header, p->header_length);
2642         }
2643
2644         pd = d + z - payload_z;
2645         payload_end_index = payload_index + p->payload_length;
2646         for (i = 0; i < payload_z; i++) {
2647                 page               = payload_index >> PAGE_SHIFT;
2648                 offset             = payload_index & ~PAGE_MASK;
2649                 next_page_index    = (page + 1) << PAGE_SHIFT;
2650                 length             =
2651                         min(next_page_index, payload_end_index) - payload_index;
2652                 pd[i].req_count    = cpu_to_le16(length);
2653
2654                 page_bus = page_private(buffer->pages[page]);
2655                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2656
2657                 payload_index += length;
2658         }
2659
2660         if (p->interrupt)
2661                 irq = DESCRIPTOR_IRQ_ALWAYS;
2662         else
2663                 irq = DESCRIPTOR_NO_IRQ;
2664
2665         last = z == 2 ? d : d + z - 1;
2666         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2667                                      DESCRIPTOR_STATUS |
2668                                      DESCRIPTOR_BRANCH_ALWAYS |
2669                                      irq);
2670
2671         context_append(&ctx->context, d, z, header_z);
2672
2673         return 0;
2674 }
2675
2676 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2677                                        struct fw_iso_packet *packet,
2678                                        struct fw_iso_buffer *buffer,
2679                                        unsigned long payload)
2680 {
2681         struct descriptor *d, *pd;
2682         dma_addr_t d_bus, page_bus;
2683         u32 z, header_z, rest;
2684         int i, j, length;
2685         int page, offset, packet_count, header_size, payload_per_buffer;
2686
2687         /*
2688          * The OHCI controller puts the isochronous header and trailer in the
2689          * buffer, so we need at least 8 bytes.
2690          */
2691         packet_count = packet->header_length / ctx->base.header_size;
2692         header_size  = max(ctx->base.header_size, (size_t)8);
2693
2694         /* Get header size in number of descriptors. */
2695         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2696         page     = payload >> PAGE_SHIFT;
2697         offset   = payload & ~PAGE_MASK;
2698         payload_per_buffer = packet->payload_length / packet_count;
2699
2700         for (i = 0; i < packet_count; i++) {
2701                 /* d points to the header descriptor */
2702                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2703                 d = context_get_descriptors(&ctx->context,
2704                                 z + header_z, &d_bus);
2705                 if (d == NULL)
2706                         return -ENOMEM;
2707
2708                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2709                                               DESCRIPTOR_INPUT_MORE);
2710                 if (packet->skip && i == 0)
2711                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2712                 d->req_count    = cpu_to_le16(header_size);
2713                 d->res_count    = d->req_count;
2714                 d->transfer_status = 0;
2715                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2716
2717                 rest = payload_per_buffer;
2718                 pd = d;
2719                 for (j = 1; j < z; j++) {
2720                         pd++;
2721                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2722                                                   DESCRIPTOR_INPUT_MORE);
2723
2724                         if (offset + rest < PAGE_SIZE)
2725                                 length = rest;
2726                         else
2727                                 length = PAGE_SIZE - offset;
2728                         pd->req_count = cpu_to_le16(length);
2729                         pd->res_count = pd->req_count;
2730                         pd->transfer_status = 0;
2731
2732                         page_bus = page_private(buffer->pages[page]);
2733                         pd->data_address = cpu_to_le32(page_bus + offset);
2734
2735                         offset = (offset + length) & ~PAGE_MASK;
2736                         rest -= length;
2737                         if (offset == 0)
2738                                 page++;
2739                 }
2740                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2741                                           DESCRIPTOR_INPUT_LAST |
2742                                           DESCRIPTOR_BRANCH_ALWAYS);
2743                 if (packet->interrupt && i == packet_count - 1)
2744                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2745
2746                 context_append(&ctx->context, d, z, header_z);
2747         }
2748
2749         return 0;
2750 }
2751
2752 static int queue_iso_buffer_fill(struct iso_context *ctx,
2753                                  struct fw_iso_packet *packet,
2754                                  struct fw_iso_buffer *buffer,
2755                                  unsigned long payload)
2756 {
2757         struct descriptor *d;
2758         dma_addr_t d_bus, page_bus;
2759         int page, offset, rest, z, i, length;
2760
2761         page   = payload >> PAGE_SHIFT;
2762         offset = payload & ~PAGE_MASK;
2763         rest   = packet->payload_length;
2764
2765         /* We need one descriptor for each page in the buffer. */
2766         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2767
2768         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2769                 return -EFAULT;
2770
2771         for (i = 0; i < z; i++) {
2772                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2773                 if (d == NULL)
2774                         return -ENOMEM;
2775
2776                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2777                                          DESCRIPTOR_BRANCH_ALWAYS);
2778                 if (packet->skip && i == 0)
2779                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2780                 if (packet->interrupt && i == z - 1)
2781                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2782
2783                 if (offset + rest < PAGE_SIZE)
2784                         length = rest;
2785                 else
2786                         length = PAGE_SIZE - offset;
2787                 d->req_count = cpu_to_le16(length);
2788                 d->res_count = d->req_count;
2789                 d->transfer_status = 0;
2790
2791                 page_bus = page_private(buffer->pages[page]);
2792                 d->data_address = cpu_to_le32(page_bus + offset);
2793
2794                 rest -= length;
2795                 offset = 0;
2796                 page++;
2797
2798                 context_append(&ctx->context, d, 1, 0);
2799         }
2800
2801         return 0;
2802 }
2803
2804 static int ohci_queue_iso(struct fw_iso_context *base,
2805                           struct fw_iso_packet *packet,
2806                           struct fw_iso_buffer *buffer,
2807                           unsigned long payload)
2808 {
2809         struct iso_context *ctx = container_of(base, struct iso_context, base);
2810         unsigned long flags;
2811         int ret = -ENOSYS;
2812
2813         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2814         switch (base->type) {
2815         case FW_ISO_CONTEXT_TRANSMIT:
2816                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2817                 break;
2818         case FW_ISO_CONTEXT_RECEIVE:
2819                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2820                 break;
2821         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2822                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2823                 break;
2824         }
2825         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2826
2827         return ret;
2828 }
2829
2830 static const struct fw_card_driver ohci_driver = {
2831         .enable                 = ohci_enable,
2832         .read_phy_reg           = ohci_read_phy_reg,
2833         .update_phy_reg         = ohci_update_phy_reg,
2834         .set_config_rom         = ohci_set_config_rom,
2835         .send_request           = ohci_send_request,
2836         .send_response          = ohci_send_response,
2837         .cancel_packet          = ohci_cancel_packet,
2838         .enable_phys_dma        = ohci_enable_phys_dma,
2839         .read_csr               = ohci_read_csr,
2840         .write_csr              = ohci_write_csr,
2841
2842         .allocate_iso_context   = ohci_allocate_iso_context,
2843         .free_iso_context       = ohci_free_iso_context,
2844         .set_iso_channels       = ohci_set_iso_channels,
2845         .queue_iso              = ohci_queue_iso,
2846         .start_iso              = ohci_start_iso,
2847         .stop_iso               = ohci_stop_iso,
2848 };
2849
2850 #ifdef CONFIG_PPC_PMAC
2851 static void pmac_ohci_on(struct pci_dev *dev)
2852 {
2853         if (machine_is(powermac)) {
2854                 struct device_node *ofn = pci_device_to_OF_node(dev);
2855
2856                 if (ofn) {
2857                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2858                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2859                 }
2860         }
2861 }
2862
2863 static void pmac_ohci_off(struct pci_dev *dev)
2864 {
2865         if (machine_is(powermac)) {
2866                 struct device_node *ofn = pci_device_to_OF_node(dev);
2867
2868                 if (ofn) {
2869                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2870                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2871                 }
2872         }
2873 }
2874 #else
2875 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2876 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2877 #endif /* CONFIG_PPC_PMAC */
2878
2879 static int __devinit pci_probe(struct pci_dev *dev,
2880                                const struct pci_device_id *ent)
2881 {
2882         struct fw_ohci *ohci;
2883         u32 bus_options, max_receive, link_speed, version;
2884         u64 guid;
2885         int i, err, n_ir, n_it;
2886         size_t size;
2887
2888         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2889         if (ohci == NULL) {
2890                 err = -ENOMEM;
2891                 goto fail;
2892         }
2893
2894         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2895
2896         pmac_ohci_on(dev);
2897
2898         err = pci_enable_device(dev);
2899         if (err) {
2900                 fw_error("Failed to enable OHCI hardware\n");
2901                 goto fail_free;
2902         }
2903
2904         pci_set_master(dev);
2905         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2906         pci_set_drvdata(dev, ohci);
2907
2908         spin_lock_init(&ohci->lock);
2909         mutex_init(&ohci->phy_reg_mutex);
2910
2911         tasklet_init(&ohci->bus_reset_tasklet,
2912                      bus_reset_tasklet, (unsigned long)ohci);
2913
2914         err = pci_request_region(dev, 0, ohci_driver_name);
2915         if (err) {
2916                 fw_error("MMIO resource unavailable\n");
2917                 goto fail_disable;
2918         }
2919
2920         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2921         if (ohci->registers == NULL) {
2922                 fw_error("Failed to remap registers\n");
2923                 err = -ENXIO;
2924                 goto fail_iomem;
2925         }
2926
2927         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2928                 if (ohci_quirks[i].vendor == dev->vendor &&
2929                     (ohci_quirks[i].device == dev->device ||
2930                      ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2931                         ohci->quirks = ohci_quirks[i].flags;
2932                         break;
2933                 }
2934         if (param_quirks)
2935                 ohci->quirks = param_quirks;
2936
2937         ar_context_init(&ohci->ar_request_ctx, ohci,
2938                         OHCI1394_AsReqRcvContextControlSet);
2939
2940         ar_context_init(&ohci->ar_response_ctx, ohci,
2941                         OHCI1394_AsRspRcvContextControlSet);
2942
2943         context_init(&ohci->at_request_ctx, ohci,
2944                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2945
2946         context_init(&ohci->at_response_ctx, ohci,
2947                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2948
2949         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2950         ohci->ir_context_channels = ~0ULL;
2951         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2952         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2953         n_ir = hweight32(ohci->ir_context_mask);
2954         size = sizeof(struct iso_context) * n_ir;
2955         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2956
2957         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2958         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2959         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2960         n_it = hweight32(ohci->it_context_mask);
2961         size = sizeof(struct iso_context) * n_it;
2962         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2963
2964         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2965                 err = -ENOMEM;
2966                 goto fail_contexts;
2967         }
2968
2969         /* self-id dma buffer allocation */
2970         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2971                                                SELF_ID_BUF_SIZE,
2972                                                &ohci->self_id_bus,
2973                                                GFP_KERNEL);
2974         if (ohci->self_id_cpu == NULL) {
2975                 err = -ENOMEM;
2976                 goto fail_contexts;
2977         }
2978
2979         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2980         max_receive = (bus_options >> 12) & 0xf;
2981         link_speed = bus_options & 0x7;
2982         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2983                 reg_read(ohci, OHCI1394_GUIDLo);
2984
2985         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2986         if (err)
2987                 goto fail_self_id;
2988
2989         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2990         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2991                   "%d IR + %d IT contexts, quirks 0x%x\n",
2992                   dev_name(&dev->dev), version >> 16, version & 0xff,
2993                   n_ir, n_it, ohci->quirks);
2994
2995         return 0;
2996
2997  fail_self_id:
2998         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2999                           ohci->self_id_cpu, ohci->self_id_bus);
3000  fail_contexts:
3001         kfree(ohci->ir_context_list);
3002         kfree(ohci->it_context_list);
3003         context_release(&ohci->at_response_ctx);
3004         context_release(&ohci->at_request_ctx);
3005         ar_context_release(&ohci->ar_response_ctx);
3006         ar_context_release(&ohci->ar_request_ctx);
3007         pci_iounmap(dev, ohci->registers);
3008  fail_iomem:
3009         pci_release_region(dev, 0);
3010  fail_disable:
3011         pci_disable_device(dev);
3012  fail_free:
3013         kfree(&ohci->card);
3014         pmac_ohci_off(dev);
3015  fail:
3016         if (err == -ENOMEM)
3017                 fw_error("Out of memory\n");
3018
3019         return err;
3020 }
3021
3022 static void pci_remove(struct pci_dev *dev)
3023 {
3024         struct fw_ohci *ohci;
3025
3026         ohci = pci_get_drvdata(dev);
3027         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3028         flush_writes(ohci);
3029         fw_core_remove_card(&ohci->card);
3030
3031         /*
3032          * FIXME: Fail all pending packets here, now that the upper
3033          * layers can't queue any more.
3034          */
3035
3036         software_reset(ohci);
3037         free_irq(dev->irq, ohci);
3038
3039         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3040                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3041                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3042         if (ohci->config_rom)
3043                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3044                                   ohci->config_rom, ohci->config_rom_bus);
3045         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3046                           ohci->self_id_cpu, ohci->self_id_bus);
3047         ar_context_release(&ohci->ar_request_ctx);
3048         ar_context_release(&ohci->ar_response_ctx);
3049         context_release(&ohci->at_request_ctx);
3050         context_release(&ohci->at_response_ctx);
3051         kfree(ohci->it_context_list);
3052         kfree(ohci->ir_context_list);
3053         pci_disable_msi(dev);
3054         pci_iounmap(dev, ohci->registers);
3055         pci_release_region(dev, 0);
3056         pci_disable_device(dev);
3057         kfree(&ohci->card);
3058         pmac_ohci_off(dev);
3059
3060         fw_notify("Removed fw-ohci device.\n");
3061 }
3062
3063 #ifdef CONFIG_PM
3064 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3065 {
3066         struct fw_ohci *ohci = pci_get_drvdata(dev);
3067         int err;
3068
3069         software_reset(ohci);
3070         free_irq(dev->irq, ohci);
3071         pci_disable_msi(dev);
3072         err = pci_save_state(dev);
3073         if (err) {
3074                 fw_error("pci_save_state failed\n");
3075                 return err;
3076         }
3077         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3078         if (err)
3079                 fw_error("pci_set_power_state failed with %d\n", err);
3080         pmac_ohci_off(dev);
3081
3082         return 0;
3083 }
3084
3085 static int pci_resume(struct pci_dev *dev)
3086 {
3087         struct fw_ohci *ohci = pci_get_drvdata(dev);
3088         int err;
3089
3090         pmac_ohci_on(dev);
3091         pci_set_power_state(dev, PCI_D0);
3092         pci_restore_state(dev);
3093         err = pci_enable_device(dev);
3094         if (err) {
3095                 fw_error("pci_enable_device failed\n");
3096                 return err;
3097         }
3098
3099         return ohci_enable(&ohci->card, NULL, 0);
3100 }
3101 #endif
3102
3103 static const struct pci_device_id pci_table[] = {
3104         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3105         { }
3106 };
3107
3108 MODULE_DEVICE_TABLE(pci, pci_table);
3109
3110 static struct pci_driver fw_ohci_pci_driver = {
3111         .name           = ohci_driver_name,
3112         .id_table       = pci_table,
3113         .probe          = pci_probe,
3114         .remove         = pci_remove,
3115 #ifdef CONFIG_PM
3116         .resume         = pci_resume,
3117         .suspend        = pci_suspend,
3118 #endif
3119 };
3120
3121 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3122 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3123 MODULE_LICENSE("GPL");
3124
3125 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3126 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3127 MODULE_ALIAS("ohci1394");
3128 #endif
3129
3130 static int __init fw_ohci_init(void)
3131 {
3132         return pci_register_driver(&fw_ohci_pci_driver);
3133 }
3134
3135 static void __exit fw_ohci_cleanup(void)
3136 {
3137         pci_unregister_driver(&fw_ohci_pci_driver);
3138 }
3139
3140 module_init(fw_ohci_init);
3141 module_exit(fw_ohci_cleanup);