1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
14 #include <linux/errno.h>
15 #include <linux/delay.h>
16 #include <linux/mutex.h>
17 #include <linux/slab.h>
18 #include <linux/types.h>
19 #include <linux/qcom_scm.h>
20 #include <linux/arm-smccc.h>
21 #include <linux/dma-mapping.h>
25 #define QCOM_SCM_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
27 #define MAX_QCOM_SCM_ARGS 10
28 #define MAX_QCOM_SCM_RETS 3
30 #define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
31 (((a) & 0x3) << 4) | \
32 (((b) & 0x3) << 6) | \
33 (((c) & 0x3) << 8) | \
34 (((d) & 0x3) << 10) | \
35 (((e) & 0x3) << 12) | \
36 (((f) & 0x3) << 14) | \
37 (((g) & 0x3) << 16) | \
38 (((h) & 0x3) << 18) | \
39 (((i) & 0x3) << 20) | \
40 (((j) & 0x3) << 22) | \
43 #define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
46 * struct qcom_scm_desc
47 * @arginfo: Metadata describing the arguments in args[]
48 * @args: The array of arguments for the secure syscall
49 * @res: The values returned by the secure syscall
51 struct qcom_scm_desc {
53 u64 args[MAX_QCOM_SCM_ARGS];
56 static u64 qcom_smccc_convention = -1;
57 static DEFINE_MUTEX(qcom_scm_lock);
59 #define QCOM_SCM_EBUSY_WAIT_MS 30
60 #define QCOM_SCM_EBUSY_MAX_RETRY 20
62 #define N_EXT_QCOM_SCM_ARGS 7
63 #define FIRST_EXT_ARG_IDX 3
64 #define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
67 * qcom_scm_call() - Invoke a syscall in the secure world
69 * @svc_id: service identifier
70 * @cmd_id: command identifier
71 * @desc: Descriptor structure containing arguments and return values
73 * Sends a command to the SCM and waits for the command to finish processing.
74 * This should *only* be called in pre-emptible context.
76 static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
77 const struct qcom_scm_desc *desc,
78 struct arm_smccc_res *res)
80 int arglen = desc->arginfo & 0xf;
81 int retry_count = 0, i;
82 u32 fn_id = QCOM_SCM_FNID(svc_id, cmd_id);
83 u64 cmd, x5 = desc->args[FIRST_EXT_ARG_IDX];
84 dma_addr_t args_phys = 0;
85 void *args_virt = NULL;
88 if (unlikely(arglen > N_REGISTER_ARGS)) {
89 alloc_len = N_EXT_QCOM_SCM_ARGS * sizeof(u64);
90 args_virt = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
95 if (qcom_smccc_convention == ARM_SMCCC_SMC_32) {
96 __le32 *args = args_virt;
98 for (i = 0; i < N_EXT_QCOM_SCM_ARGS; i++)
99 args[i] = cpu_to_le32(desc->args[i +
102 __le64 *args = args_virt;
104 for (i = 0; i < N_EXT_QCOM_SCM_ARGS; i++)
105 args[i] = cpu_to_le64(desc->args[i +
109 args_phys = dma_map_single(dev, args_virt, alloc_len,
112 if (dma_mapping_error(dev, args_phys)) {
121 mutex_lock(&qcom_scm_lock);
123 cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL,
124 qcom_smccc_convention,
125 ARM_SMCCC_OWNER_SIP, fn_id);
128 arm_smccc_smc(cmd, desc->arginfo, desc->args[0],
129 desc->args[1], desc->args[2], x5, 0, 0,
131 } while (res->a0 == QCOM_SCM_INTERRUPTED);
133 mutex_unlock(&qcom_scm_lock);
135 if (res->a0 == QCOM_SCM_V2_EBUSY) {
136 if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
138 msleep(QCOM_SCM_EBUSY_WAIT_MS);
140 } while (res->a0 == QCOM_SCM_V2_EBUSY);
143 dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
148 return qcom_scm_remap_error(res->a0);
154 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
155 * @entry: Entry point function for the cpus
156 * @cpus: The cpumask of cpus that will use the entry point
158 * Set the cold boot address of the cpus. Any cpu outside the supported
159 * range would be removed from the cpu present mask.
161 int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
167 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
168 * @dev: Device pointer
169 * @entry: Entry point function for the cpus
170 * @cpus: The cpumask of cpus that will use the entry point
172 * Set the Linux entry point for the SCM to transfer control to when coming
173 * out of a power down. CPU power down may be executed on cpuidle or hotplug.
175 int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
176 const cpumask_t *cpus)
182 * qcom_scm_cpu_power_down() - Power down the cpu
183 * @flags - Flags to flush cache
185 * This is an end point to power down cpu. If there was a pending interrupt,
186 * the control would return from this function, otherwise, the cpu jumps to the
187 * warm boot entry point set for this cpu upon reset.
189 void __qcom_scm_cpu_power_down(u32 flags)
193 int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
196 struct qcom_scm_desc desc = {0};
197 struct arm_smccc_res res;
199 desc.arginfo = QCOM_SCM_ARGS(1);
200 desc.args[0] = QCOM_SCM_FNID(svc_id, cmd_id) |
201 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
203 ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD,
206 return ret ? : res.a1;
209 int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
210 u32 req_cnt, u32 *resp)
213 struct qcom_scm_desc desc = {0};
214 struct arm_smccc_res res;
216 if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
219 desc.args[0] = req[0].addr;
220 desc.args[1] = req[0].val;
221 desc.args[2] = req[1].addr;
222 desc.args[3] = req[1].val;
223 desc.args[4] = req[2].addr;
224 desc.args[5] = req[2].val;
225 desc.args[6] = req[3].addr;
226 desc.args[7] = req[3].val;
227 desc.args[8] = req[4].addr;
228 desc.args[9] = req[4].val;
229 desc.arginfo = QCOM_SCM_ARGS(10);
231 ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP, &desc,
238 void __qcom_scm_init(void)
241 struct arm_smccc_res res;
242 u32 function = QCOM_SCM_FNID(QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD);
244 /* First try a SMC64 call */
245 cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64,
246 ARM_SMCCC_OWNER_SIP, function);
248 arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)),
249 0, 0, 0, 0, 0, &res);
251 if (!res.a0 && res.a1)
252 qcom_smccc_convention = ARM_SMCCC_SMC_64;
254 qcom_smccc_convention = ARM_SMCCC_SMC_32;