2 * Driver for basic memory-mapped GPIO controllers.
4 * Copyright 2008 MontaVista Software, Inc.
5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
14 * ..The simplest form of a GPIO controller that the driver supports is``
15 * `.just a single "data" register, where GPIO state can be read and/or `
16 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
19 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
20 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
21 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
22 `....trivial..'~`.```.```
24 * .```````~~~~`..`.``.``.
25 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
26 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
27 * . register the device with -be`. .with a pair of set/clear-bit registers ,
28 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
29 * ``.`.``...``` ```.. output pins are also supported.`
30 * ^^ `````.`````````.,``~``~``~~``````
32 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
33 * .. The expectation is that in at least some cases . ,-~~~-,
34 * .this will be used with roll-your-own ASIC/FPGA .` \ /
35 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
36 * ..````````......``````````` \o_
40 * ...`````~~`.....``.`..........``````.`.``.```........``.
41 * ` 8, 16, 32 and 64 bits registers are supported, and``.
42 * . the number of GPIOs is determined by the width of ~
43 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
47 #include <linux/init.h>
48 #include <linux/bug.h>
49 #include <linux/kernel.h>
50 #include <linux/module.h>
51 #include <linux/spinlock.h>
52 #include <linux/compiler.h>
53 #include <linux/types.h>
54 #include <linux/errno.h>
55 #include <linux/log2.h>
56 #include <linux/ioport.h>
58 #include <linux/gpio.h>
59 #include <linux/slab.h>
60 #include <linux/platform_device.h>
61 #include <linux/mod_devicetable.h>
62 #include <linux/basic_mmio_gpio.h>
67 unsigned long (*read_reg)(void __iomem *reg);
68 void (*write_reg)(void __iomem *reg, unsigned long data);
70 void __iomem *reg_dat;
71 void __iomem *reg_set;
72 void __iomem *reg_clr;
73 void __iomem *reg_dir;
75 /* Number of bits (GPIOs): <register width> * 8. */
79 * Some GPIO controllers work with the big-endian bits notation,
80 * e.g. in a 8-bits register, GPIO7 is the least significant bit.
82 unsigned long (*pin2mask)(struct bgpio_chip *bgc, unsigned int pin);
85 * Used to lock bgpio_chip->data. Also, this is needed to keep
86 * shadowed and real data registers writes together.
90 /* Shadowed data register to clear/set bits safely. */
93 /* Shadowed direction registers to clear/set direction safely. */
97 static struct bgpio_chip *to_bgpio_chip(struct gpio_chip *gc)
99 return container_of(gc, struct bgpio_chip, gc);
102 static void bgpio_write8(void __iomem *reg, unsigned long data)
107 static unsigned long bgpio_read8(void __iomem *reg)
112 static void bgpio_write16(void __iomem *reg, unsigned long data)
117 static unsigned long bgpio_read16(void __iomem *reg)
122 static void bgpio_write32(void __iomem *reg, unsigned long data)
127 static unsigned long bgpio_read32(void __iomem *reg)
132 #if BITS_PER_LONG >= 64
133 static void bgpio_write64(void __iomem *reg, unsigned long data)
138 static unsigned long bgpio_read64(void __iomem *reg)
142 #endif /* BITS_PER_LONG >= 64 */
144 static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
149 static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
152 return 1 << (bgc->bits - 1 - pin);
155 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
157 struct bgpio_chip *bgc = to_bgpio_chip(gc);
159 return bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio);
162 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
164 struct bgpio_chip *bgc = to_bgpio_chip(gc);
165 unsigned long mask = bgc->pin2mask(bgc, gpio);
168 spin_lock_irqsave(&bgc->lock, flags);
175 bgc->write_reg(bgc->reg_dat, bgc->data);
177 spin_unlock_irqrestore(&bgc->lock, flags);
180 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
183 struct bgpio_chip *bgc = to_bgpio_chip(gc);
184 unsigned long mask = bgc->pin2mask(bgc, gpio);
187 bgc->write_reg(bgc->reg_set, mask);
189 bgc->write_reg(bgc->reg_clr, mask);
192 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
194 struct bgpio_chip *bgc = to_bgpio_chip(gc);
195 unsigned long mask = bgc->pin2mask(bgc, gpio);
198 spin_lock_irqsave(&bgc->lock, flags);
205 bgc->write_reg(bgc->reg_set, bgc->data);
207 spin_unlock_irqrestore(&bgc->lock, flags);
210 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
215 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
218 gc->set(gc, gpio, val);
223 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
225 struct bgpio_chip *bgc = to_bgpio_chip(gc);
228 spin_lock_irqsave(&bgc->lock, flags);
230 bgc->dir &= ~bgc->pin2mask(bgc, gpio);
231 bgc->write_reg(bgc->reg_dir, bgc->dir);
233 spin_unlock_irqrestore(&bgc->lock, flags);
238 static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
240 struct bgpio_chip *bgc = to_bgpio_chip(gc);
243 gc->set(gc, gpio, val);
245 spin_lock_irqsave(&bgc->lock, flags);
247 bgc->dir |= bgc->pin2mask(bgc, gpio);
248 bgc->write_reg(bgc->reg_dir, bgc->dir);
250 spin_unlock_irqrestore(&bgc->lock, flags);
255 static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
257 struct bgpio_chip *bgc = to_bgpio_chip(gc);
260 spin_lock_irqsave(&bgc->lock, flags);
262 bgc->dir |= bgc->pin2mask(bgc, gpio);
263 bgc->write_reg(bgc->reg_dir, bgc->dir);
265 spin_unlock_irqrestore(&bgc->lock, flags);
270 static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
272 struct bgpio_chip *bgc = to_bgpio_chip(gc);
275 gc->set(gc, gpio, val);
277 spin_lock_irqsave(&bgc->lock, flags);
279 bgc->dir &= ~bgc->pin2mask(bgc, gpio);
280 bgc->write_reg(bgc->reg_dir, bgc->dir);
282 spin_unlock_irqrestore(&bgc->lock, flags);
287 static void __iomem *bgpio_request_and_map(struct device *dev,
288 struct resource *res)
290 if (!devm_request_mem_region(dev, res->start, resource_size(res),
291 res->name ?: "mmio_gpio"))
294 return devm_ioremap(dev, res->start, resource_size(res));
297 static int bgpio_setup_accessors(struct platform_device *pdev,
298 struct bgpio_chip *bgc)
300 const struct platform_device_id *platid = platform_get_device_id(pdev);
304 bgc->read_reg = bgpio_read8;
305 bgc->write_reg = bgpio_write8;
308 bgc->read_reg = bgpio_read16;
309 bgc->write_reg = bgpio_write16;
312 bgc->read_reg = bgpio_read32;
313 bgc->write_reg = bgpio_write32;
315 #if BITS_PER_LONG >= 64
317 bgc->read_reg = bgpio_read64;
318 bgc->write_reg = bgpio_write64;
320 #endif /* BITS_PER_LONG >= 64 */
322 dev_err(&pdev->dev, "unsupported data width %u bits\n",
327 bgc->pin2mask = strcmp(platid->name, "basic-mmio-gpio-be") ?
328 bgpio_pin2mask : bgpio_pin2mask_be;
334 * Create the device and allocate the resources. For setting GPIO's there are
335 * three supported configurations:
337 * - single input/output register resource (named "dat").
338 * - set/clear pair (named "set" and "clr").
339 * - single output register resource and single input resource ("set" and
342 * For the single output register, this drives a 1 by setting a bit and a zero
343 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
344 * in the set register and clears it by setting a bit in the clear register.
345 * The configuration is detected by which resources are present.
347 * For setting the GPIO direction, there are three supported configurations:
349 * - simple bidirection GPIO that requires no configuration.
350 * - an output direction register (named "dirout") where a 1 bit
351 * indicates the GPIO is an output.
352 * - an input direction register (named "dirin") where a 1 bit indicates
353 * the GPIO is an input.
355 static int bgpio_setup_io(struct platform_device *pdev,
356 struct bgpio_chip *bgc)
358 struct resource *res_set;
359 struct resource *res_clr;
360 struct resource *res_dat;
361 resource_size_t dat_sz;
363 res_dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
367 dat_sz = resource_size(res_dat);
368 if (!is_power_of_2(dat_sz))
371 bgc->bits = dat_sz * 8;
372 if (bgc->bits > BITS_PER_LONG)
375 bgc->reg_dat = bgpio_request_and_map(&pdev->dev, res_dat);
379 res_set = platform_get_resource_byname(pdev, IORESOURCE_MEM, "set");
380 res_clr = platform_get_resource_byname(pdev, IORESOURCE_MEM, "clr");
381 if (res_set && res_clr) {
382 if (resource_size(res_set) != resource_size(res_clr) ||
383 resource_size(res_set) != resource_size(res_dat))
386 bgc->reg_set = bgpio_request_and_map(&pdev->dev, res_set);
387 bgc->reg_clr = bgpio_request_and_map(&pdev->dev, res_clr);
388 if (!bgc->reg_set || !bgc->reg_clr)
391 bgc->gc.set = bgpio_set_with_clear;
392 } else if (res_set && !res_clr) {
393 if (resource_size(res_set) != resource_size(res_dat))
396 bgc->reg_set = bgpio_request_and_map(&pdev->dev, res_set);
400 bgc->gc.set = bgpio_set_set;
402 bgc->gc.set = bgpio_set;
405 bgc->gc.get = bgpio_get;
410 static int bgpio_setup_direction(struct platform_device *pdev,
411 struct bgpio_chip *bgc)
413 struct resource *res_dirout;
414 struct resource *res_dirin;
416 res_dirout = platform_get_resource_byname(pdev, IORESOURCE_MEM,
418 res_dirin = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirin");
419 if (res_dirout && res_dirin) {
421 } else if (res_dirout) {
422 bgc->reg_dir = bgpio_request_and_map(&pdev->dev, res_dirout);
425 bgc->gc.direction_output = bgpio_dir_out;
426 bgc->gc.direction_input = bgpio_dir_in;
427 } else if (res_dirin) {
428 bgc->reg_dir = bgpio_request_and_map(&pdev->dev, res_dirin);
431 bgc->gc.direction_output = bgpio_dir_out_inv;
432 bgc->gc.direction_input = bgpio_dir_in_inv;
434 bgc->gc.direction_output = bgpio_simple_dir_out;
435 bgc->gc.direction_input = bgpio_simple_dir_in;
441 static int __devinit bgpio_probe(struct platform_device *pdev)
443 struct device *dev = &pdev->dev;
444 struct bgpio_pdata *pdata = dev_get_platdata(dev);
445 struct bgpio_chip *bgc;
449 bgc = devm_kzalloc(dev, sizeof(*bgc), GFP_KERNEL);
453 ret = bgpio_setup_io(pdev, bgc);
459 bgc->gc.base = pdata->base;
460 if (pdata->ngpio > 0)
461 ngpio = pdata->ngpio;
466 ret = bgpio_setup_accessors(pdev, bgc);
470 spin_lock_init(&bgc->lock);
471 ret = bgpio_setup_direction(pdev, bgc);
475 bgc->data = bgc->read_reg(bgc->reg_dat);
477 bgc->gc.ngpio = ngpio;
479 bgc->gc.label = dev_name(dev);
481 platform_set_drvdata(pdev, bgc);
483 ret = gpiochip_add(&bgc->gc);
485 dev_err(dev, "gpiochip_add() failed: %d\n", ret);
490 static int __devexit bgpio_remove(struct platform_device *pdev)
492 struct bgpio_chip *bgc = platform_get_drvdata(pdev);
494 return gpiochip_remove(&bgc->gc);
497 static const struct platform_device_id bgpio_id_table[] = {
498 { "basic-mmio-gpio", },
499 { "basic-mmio-gpio-be", },
502 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
504 static struct platform_driver bgpio_driver = {
506 .name = "basic-mmio-gpio",
508 .id_table = bgpio_id_table,
509 .probe = bgpio_probe,
510 .remove = __devexit_p(bgpio_remove),
513 static int __init bgpio_init(void)
515 return platform_driver_register(&bgpio_driver);
517 module_init(bgpio_init);
519 static void __exit bgpio_exit(void)
521 platform_driver_unregister(&bgpio_driver);
523 module_exit(bgpio_exit);
525 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
526 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
527 MODULE_LICENSE("GPL");