2 * AMD CS5535/CS5536 GPIO driver
3 * Copyright (C) 2006 Advanced Micro Devices, Inc.
4 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/spinlock.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/gpio.h>
17 #include <linux/cs5535.h>
20 #define DRV_NAME "cs5535-gpio"
25 * 31-29,23 : reserved (always mask out)
37 * If a mask was not specified, allow all except
38 * reserved and Power Button
40 #define GPIO_DEFAULT_MASK 0x0F7FFFFF
42 static ulong mask = GPIO_DEFAULT_MASK;
43 module_param_named(mask, mask, ulong, 0444);
44 MODULE_PARM_DESC(mask, "GPIO channel mask.");
46 static struct cs5535_gpio_chip {
47 struct gpio_chip chip;
55 * The CS5535/CS5536 GPIOs support a number of extra features not defined
56 * by the gpio_chip API, so these are exported. For a full list of the
57 * registers, see include/linux/cs5535.h.
60 static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
63 unsigned long addr = chip->base + 0x80 + reg;
66 * According to the CS5536 errata (#36), after suspend
67 * a write to the high bank GPIO register will clear all
68 * non-selected bits; the recommended workaround is a
69 * read-modify-write operation.
71 * Don't apply this errata to the edge status GPIOs, as writing
72 * to their lower bits will clear them.
74 if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
76 val |= (inl(addr) & 0xffff); /* ignore the high bits */
78 val |= (inl(addr) ^ (val >> 16));
83 static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
87 /* low bank register */
88 outl(1 << offset, chip->base + reg);
90 /* high bank register */
91 errata_outl(chip, 1 << (offset - 16), reg);
94 void cs5535_gpio_set(unsigned offset, unsigned int reg)
96 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
99 spin_lock_irqsave(&chip->lock, flags);
100 __cs5535_gpio_set(chip, offset, reg);
101 spin_unlock_irqrestore(&chip->lock, flags);
103 EXPORT_SYMBOL_GPL(cs5535_gpio_set);
105 static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
109 /* low bank register */
110 outl(1 << (offset + 16), chip->base + reg);
112 /* high bank register */
113 errata_outl(chip, 1 << offset, reg);
116 void cs5535_gpio_clear(unsigned offset, unsigned int reg)
118 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
121 spin_lock_irqsave(&chip->lock, flags);
122 __cs5535_gpio_clear(chip, offset, reg);
123 spin_unlock_irqrestore(&chip->lock, flags);
125 EXPORT_SYMBOL_GPL(cs5535_gpio_clear);
127 int cs5535_gpio_isset(unsigned offset, unsigned int reg)
129 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
133 spin_lock_irqsave(&chip->lock, flags);
135 /* low bank register */
136 val = inl(chip->base + reg);
138 /* high bank register */
139 val = inl(chip->base + 0x80 + reg);
142 spin_unlock_irqrestore(&chip->lock, flags);
144 return (val & (1 << offset)) ? 1 : 0;
146 EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
148 int cs5535_gpio_set_irq(unsigned group, unsigned irq)
152 if (group > 7 || irq > 15)
155 rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
157 lo &= ~(0xF << (group * 4));
158 lo |= (irq & 0xF) << (group * 4);
160 wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
163 EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
165 void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
167 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
168 uint32_t shift = (offset % 8) * 4;
174 else if (offset >= 16)
176 else if (offset >= 8)
181 spin_lock_irqsave(&chip->lock, flags);
182 val = inl(chip->base + offset);
184 /* Clear whatever was there before */
185 val &= ~(0xF << shift);
187 /* Set the new value */
188 val |= ((pair & 7) << shift);
190 /* Set the PME bit if this is a PME event */
192 val |= (1 << (shift + 3));
194 outl(val, chip->base + offset);
195 spin_unlock_irqrestore(&chip->lock, flags);
197 EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);
200 * Generic gpio_chip API support.
203 static int chip_gpio_request(struct gpio_chip *c, unsigned offset)
205 struct cs5535_gpio_chip *chip = (struct cs5535_gpio_chip *) c;
208 spin_lock_irqsave(&chip->lock, flags);
210 /* check if this pin is available */
211 if ((mask & (1 << offset)) == 0) {
212 dev_info(&chip->pdev->dev,
213 "pin %u is not available (check mask)\n", offset);
214 spin_unlock_irqrestore(&chip->lock, flags);
218 /* disable output aux 1 & 2 on this pin */
219 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX1);
220 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX2);
222 /* disable input aux 1 on this pin */
223 __cs5535_gpio_clear(chip, offset, GPIO_INPUT_AUX1);
225 spin_unlock_irqrestore(&chip->lock, flags);
230 static int chip_gpio_get(struct gpio_chip *chip, unsigned offset)
232 return cs5535_gpio_isset(offset, GPIO_READ_BACK);
235 static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
238 cs5535_gpio_set(offset, GPIO_OUTPUT_VAL);
240 cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL);
243 static int chip_direction_input(struct gpio_chip *c, unsigned offset)
245 struct cs5535_gpio_chip *chip = (struct cs5535_gpio_chip *) c;
248 spin_lock_irqsave(&chip->lock, flags);
249 __cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
250 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_ENABLE);
251 spin_unlock_irqrestore(&chip->lock, flags);
256 static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
258 struct cs5535_gpio_chip *chip = (struct cs5535_gpio_chip *) c;
261 spin_lock_irqsave(&chip->lock, flags);
263 __cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
264 __cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE);
266 __cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL);
268 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_VAL);
270 spin_unlock_irqrestore(&chip->lock, flags);
275 static const char * const cs5535_gpio_names[] = {
276 "GPIO0", "GPIO1", "GPIO2", "GPIO3",
277 "GPIO4", "GPIO5", "GPIO6", "GPIO7",
278 "GPIO8", "GPIO9", "GPIO10", "GPIO11",
279 "GPIO12", "GPIO13", "GPIO14", "GPIO15",
280 "GPIO16", "GPIO17", "GPIO18", "GPIO19",
281 "GPIO20", "GPIO21", "GPIO22", NULL,
282 "GPIO24", "GPIO25", "GPIO26", "GPIO27",
283 "GPIO28", NULL, NULL, NULL,
286 static struct cs5535_gpio_chip cs5535_gpio_chip = {
288 .owner = THIS_MODULE,
293 .names = cs5535_gpio_names,
294 .request = chip_gpio_request,
296 .get = chip_gpio_get,
297 .set = chip_gpio_set,
299 .direction_input = chip_direction_input,
300 .direction_output = chip_direction_output,
304 static int __init cs5535_gpio_probe(struct pci_dev *pdev,
305 const struct pci_device_id *pci_id)
308 ulong mask_orig = mask;
310 /* There are two ways to get the GPIO base address; one is by
311 * fetching it from MSR_LBAR_GPIO, the other is by reading the
312 * PCI BAR info. The latter method is easier (especially across
313 * different architectures), so we'll stick with that for now. If
314 * it turns out to be unreliable in the face of crappy BIOSes, we
315 * can always go back to using MSRs.. */
317 err = pci_enable_device_io(pdev);
319 dev_err(&pdev->dev, "can't enable device IO\n");
323 err = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
325 dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
329 /* set up the driver-specific struct */
330 cs5535_gpio_chip.base = pci_resource_start(pdev, GPIO_BAR);
331 cs5535_gpio_chip.pdev = pdev;
332 spin_lock_init(&cs5535_gpio_chip.lock);
334 dev_info(&pdev->dev, "allocated PCI BAR #%d: base 0x%llx\n", GPIO_BAR,
335 (unsigned long long) cs5535_gpio_chip.base);
337 /* mask out reserved pins */
340 /* do not allow pin 28, Power Button, as there's special handling
341 * in the PMC needed. (note 12, p. 48) */
344 if (mask_orig != mask)
345 dev_info(&pdev->dev, "mask changed from 0x%08lX to 0x%08lX\n",
348 /* finally, register with the generic GPIO API */
349 err = gpiochip_add(&cs5535_gpio_chip.chip);
353 dev_info(&pdev->dev, DRV_NAME ": GPIO support successfully loaded.\n");
357 pci_release_region(pdev, GPIO_BAR);
362 static void __exit cs5535_gpio_remove(struct pci_dev *pdev)
366 err = gpiochip_remove(&cs5535_gpio_chip.chip);
369 dev_err(&pdev->dev, "unable to remove gpio_chip?\n");
371 pci_release_region(pdev, GPIO_BAR);
374 static struct pci_device_id cs5535_gpio_pci_tbl[] = {
375 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
376 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
379 MODULE_DEVICE_TABLE(pci, cs5535_gpio_pci_tbl);
382 * We can't use the standard PCI driver registration stuff here, since
383 * that allows only one driver to bind to each PCI device (and we want
384 * multiple drivers to be able to bind to the device). Instead, manually
385 * scan for the PCI device, request a single region, and keep track of the
386 * devices that we're using.
389 static int __init cs5535_gpio_scan_pci(void)
391 struct pci_dev *pdev;
395 for (i = 0; i < ARRAY_SIZE(cs5535_gpio_pci_tbl); i++) {
396 pdev = pci_get_device(cs5535_gpio_pci_tbl[i].vendor,
397 cs5535_gpio_pci_tbl[i].device, NULL);
399 err = cs5535_gpio_probe(pdev, &cs5535_gpio_pci_tbl[i]);
403 /* we only support a single CS5535/6 southbridge */
411 static void __exit cs5535_gpio_free_pci(void)
413 cs5535_gpio_remove(cs5535_gpio_chip.pdev);
414 pci_dev_put(cs5535_gpio_chip.pdev);
417 static int __init cs5535_gpio_init(void)
419 return cs5535_gpio_scan_pci();
422 static void __exit cs5535_gpio_exit(void)
424 cs5535_gpio_free_pci();
427 module_init(cs5535_gpio_init);
428 module_exit(cs5535_gpio_exit);
430 MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
431 MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
432 MODULE_LICENSE("GPL");