2 * Atheros AR71XX/AR724X/AR913X GPIO API support
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <linux/gpio/driver.h>
16 #include <linux/platform_data/gpio-ath79.h>
17 #include <linux/of_device.h>
19 #include <asm/mach-ath79/ar71xx_regs.h>
21 struct ath79_gpio_ctrl {
22 struct gpio_chip chip;
27 #define to_ath79_gpio_ctrl(c) container_of(c, struct ath79_gpio_ctrl, chip)
29 static void ath79_gpio_set_value(struct gpio_chip *chip,
30 unsigned gpio, int value)
32 struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
35 __raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_SET);
37 __raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_CLEAR);
40 static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
42 struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
44 return (__raw_readl(ctrl->base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
47 static int ath79_gpio_direction_input(struct gpio_chip *chip,
50 struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
53 spin_lock_irqsave(&ctrl->lock, flags);
56 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset),
57 ctrl->base + AR71XX_GPIO_REG_OE);
59 spin_unlock_irqrestore(&ctrl->lock, flags);
64 static int ath79_gpio_direction_output(struct gpio_chip *chip,
65 unsigned offset, int value)
67 struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
70 spin_lock_irqsave(&ctrl->lock, flags);
73 __raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
75 __raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);
78 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset),
79 ctrl->base + AR71XX_GPIO_REG_OE);
81 spin_unlock_irqrestore(&ctrl->lock, flags);
86 static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
88 struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
91 spin_lock_irqsave(&ctrl->lock, flags);
94 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset),
95 ctrl->base + AR71XX_GPIO_REG_OE);
97 spin_unlock_irqrestore(&ctrl->lock, flags);
102 static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
105 struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
108 spin_lock_irqsave(&ctrl->lock, flags);
111 __raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
113 __raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);
116 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & BIT(offset),
117 ctrl->base + AR71XX_GPIO_REG_OE);
119 spin_unlock_irqrestore(&ctrl->lock, flags);
124 static const struct gpio_chip ath79_gpio_chip = {
126 .get = ath79_gpio_get_value,
127 .set = ath79_gpio_set_value,
128 .direction_input = ath79_gpio_direction_input,
129 .direction_output = ath79_gpio_direction_output,
133 static const struct of_device_id ath79_gpio_of_match[] = {
134 { .compatible = "qca,ar7100-gpio" },
135 { .compatible = "qca,ar9340-gpio" },
139 static int ath79_gpio_probe(struct platform_device *pdev)
141 struct ath79_gpio_platform_data *pdata = pdev->dev.platform_data;
142 struct device_node *np = pdev->dev.of_node;
143 struct ath79_gpio_ctrl *ctrl;
144 struct resource *res;
145 u32 ath79_gpio_count;
149 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
154 err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
156 dev_err(&pdev->dev, "ngpios property is not valid\n");
159 if (ath79_gpio_count >= 32) {
160 dev_err(&pdev->dev, "ngpios must be less than 32\n");
163 oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
165 ath79_gpio_count = pdata->ngpios;
166 oe_inverted = pdata->oe_inverted;
168 dev_err(&pdev->dev, "No DT node or platform data found\n");
172 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
173 ctrl->base = devm_ioremap_nocache(
174 &pdev->dev, res->start, resource_size(res));
178 spin_lock_init(&ctrl->lock);
179 memcpy(&ctrl->chip, &ath79_gpio_chip, sizeof(ctrl->chip));
180 ctrl->chip.dev = &pdev->dev;
181 ctrl->chip.ngpio = ath79_gpio_count;
183 ctrl->chip.direction_input = ar934x_gpio_direction_input;
184 ctrl->chip.direction_output = ar934x_gpio_direction_output;
187 err = gpiochip_add(&ctrl->chip);
190 "cannot add AR71xx GPIO chip, error=%d", err);
197 static struct platform_driver ath79_gpio_driver = {
199 .name = "ath79-gpio",
200 .of_match_table = ath79_gpio_of_match,
202 .probe = ath79_gpio_probe,
205 module_platform_driver(ath79_gpio_driver);