2 * Copyright (C) 2012-2013 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/module.h>
21 #include <linux/irqdomain.h>
22 #include <linux/irqchip/chained_irq.h>
24 #define BCM_GPIO_PASSWD 0x00a5a501
25 #define GPIO_PER_BANK 32
26 #define GPIO_MAX_BANK_NUM 8
28 #define GPIO_BANK(gpio) ((gpio) >> 5)
29 #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
31 #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
32 #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
33 #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
34 #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
35 #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
36 #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
37 #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
38 #define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2))
39 #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
41 #define GPIO_GPPWR_OFFSET 0x00000520
43 #define GPIO_GPCTR0_DBR_SHIFT 5
44 #define GPIO_GPCTR0_DBR_MASK 0x000001e0
46 #define GPIO_GPCTR0_ITR_SHIFT 3
47 #define GPIO_GPCTR0_ITR_MASK 0x00000018
48 #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
49 #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
50 #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
52 #define GPIO_GPCTR0_IOTR_MASK 0x00000001
53 #define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
54 #define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
56 #define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
58 #define LOCK_CODE 0xffffffff
59 #define UNLOCK_CODE 0x00000000
61 struct bcm_kona_gpio {
62 void __iomem *reg_base;
65 struct gpio_chip gpio_chip;
66 struct irq_domain *irq_domain;
67 struct bcm_kona_gpio_bank *banks;
68 struct platform_device *pdev;
71 struct bcm_kona_gpio_bank {
74 /* Used in the interrupt handler */
75 struct bcm_kona_gpio *kona_gpio;
78 static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
80 return container_of(chip, struct bcm_kona_gpio, gpio_chip);
83 static void bcm_kona_gpio_set_lockcode_bank(void __iomem *reg_base,
84 int bank_id, int lockcode)
86 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
87 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
90 static inline void bcm_kona_gpio_lock_bank(void __iomem *reg_base, int bank_id)
92 bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, LOCK_CODE);
95 static inline void bcm_kona_gpio_unlock_bank(void __iomem *reg_base,
98 bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, UNLOCK_CODE);
101 static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
103 struct bcm_kona_gpio *kona_gpio;
104 void __iomem *reg_base;
105 int bank_id = GPIO_BANK(gpio);
106 int bit = GPIO_BIT(gpio);
110 kona_gpio = to_kona_gpio(chip);
111 reg_base = kona_gpio->reg_base;
112 spin_lock_irqsave(&kona_gpio->lock, flags);
113 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
115 /* determine the GPIO pin direction */
116 val = readl(reg_base + GPIO_CONTROL(gpio));
117 val &= GPIO_GPCTR0_IOTR_MASK;
119 /* this function only applies to output pin */
120 if (GPIO_GPCTR0_IOTR_CMD_INPUT == val)
123 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
125 val = readl(reg_base + reg_offset);
127 writel(val, reg_base + reg_offset);
130 bcm_kona_gpio_lock_bank(reg_base, bank_id);
131 spin_unlock_irqrestore(&kona_gpio->lock, flags);
134 static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
136 struct bcm_kona_gpio *kona_gpio;
137 void __iomem *reg_base;
138 int bank_id = GPIO_BANK(gpio);
139 int bit = GPIO_BIT(gpio);
143 kona_gpio = to_kona_gpio(chip);
144 reg_base = kona_gpio->reg_base;
145 spin_lock_irqsave(&kona_gpio->lock, flags);
146 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
148 /* determine the GPIO pin direction */
149 val = readl(reg_base + GPIO_CONTROL(gpio));
150 val &= GPIO_GPCTR0_IOTR_MASK;
152 /* read the GPIO bank status */
153 reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
154 GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
155 val = readl(reg_base + reg_offset);
157 bcm_kona_gpio_lock_bank(reg_base, bank_id);
158 spin_unlock_irqrestore(&kona_gpio->lock, flags);
160 /* return the specified bit status */
161 return !!(val & bit);
164 static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
166 struct bcm_kona_gpio *kona_gpio;
167 void __iomem *reg_base;
170 int bank_id = GPIO_BANK(gpio);
172 kona_gpio = to_kona_gpio(chip);
173 reg_base = kona_gpio->reg_base;
174 spin_lock_irqsave(&kona_gpio->lock, flags);
175 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
177 val = readl(reg_base + GPIO_CONTROL(gpio));
178 val &= ~GPIO_GPCTR0_IOTR_MASK;
179 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
180 writel(val, reg_base + GPIO_CONTROL(gpio));
182 bcm_kona_gpio_lock_bank(reg_base, bank_id);
183 spin_unlock_irqrestore(&kona_gpio->lock, flags);
188 static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
189 unsigned gpio, int value)
191 struct bcm_kona_gpio *kona_gpio;
192 void __iomem *reg_base;
193 int bank_id = GPIO_BANK(gpio);
194 int bit = GPIO_BIT(gpio);
198 kona_gpio = to_kona_gpio(chip);
199 reg_base = kona_gpio->reg_base;
200 spin_lock_irqsave(&kona_gpio->lock, flags);
201 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
203 val = readl(reg_base + GPIO_CONTROL(gpio));
204 val &= ~GPIO_GPCTR0_IOTR_MASK;
205 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
206 writel(val, reg_base + GPIO_CONTROL(gpio));
207 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
209 val = readl(reg_base + reg_offset);
211 writel(val, reg_base + reg_offset);
213 bcm_kona_gpio_lock_bank(reg_base, bank_id);
214 spin_unlock_irqrestore(&kona_gpio->lock, flags);
219 static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
221 struct bcm_kona_gpio *kona_gpio;
223 kona_gpio = to_kona_gpio(chip);
224 if (gpio >= kona_gpio->gpio_chip.ngpio)
226 return irq_create_mapping(kona_gpio->irq_domain, gpio);
229 static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
232 struct bcm_kona_gpio *kona_gpio;
233 void __iomem *reg_base;
236 int bank_id = GPIO_BANK(gpio);
238 kona_gpio = to_kona_gpio(chip);
239 reg_base = kona_gpio->reg_base;
240 /* debounce must be 1-128ms (or 0) */
241 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
242 dev_err(chip->dev, "Debounce value %u not in range\n",
247 /* calculate debounce bit value */
252 res = fls(debounce) - 1;
253 /* Check if MSB-1 is set (round up or down) */
254 if (res > 0 && (debounce & BIT(res - 1)))
258 /* spin lock for read-modify-write of the GPIO register */
259 spin_lock_irqsave(&kona_gpio->lock, flags);
260 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
262 val = readl(reg_base + GPIO_CONTROL(gpio));
263 val &= ~GPIO_GPCTR0_DBR_MASK;
266 /* disable debounce */
267 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
269 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
270 (res << GPIO_GPCTR0_DBR_SHIFT);
273 writel(val, reg_base + GPIO_CONTROL(gpio));
275 bcm_kona_gpio_lock_bank(reg_base, bank_id);
276 spin_unlock_irqrestore(&kona_gpio->lock, flags);
281 static struct gpio_chip template_chip = {
282 .label = "bcm-kona-gpio",
283 .direction_input = bcm_kona_gpio_direction_input,
284 .get = bcm_kona_gpio_get,
285 .direction_output = bcm_kona_gpio_direction_output,
286 .set = bcm_kona_gpio_set,
287 .set_debounce = bcm_kona_gpio_set_debounce,
288 .to_irq = bcm_kona_gpio_to_irq,
292 static void bcm_kona_gpio_irq_ack(struct irq_data *d)
294 struct bcm_kona_gpio *kona_gpio;
295 void __iomem *reg_base;
297 int bank_id = GPIO_BANK(gpio);
298 int bit = GPIO_BIT(gpio);
302 kona_gpio = irq_data_get_irq_chip_data(d);
303 reg_base = kona_gpio->reg_base;
304 spin_lock_irqsave(&kona_gpio->lock, flags);
305 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
307 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
309 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
311 bcm_kona_gpio_lock_bank(reg_base, bank_id);
312 spin_unlock_irqrestore(&kona_gpio->lock, flags);
315 static void bcm_kona_gpio_irq_mask(struct irq_data *d)
317 struct bcm_kona_gpio *kona_gpio;
318 void __iomem *reg_base;
320 int bank_id = GPIO_BANK(gpio);
321 int bit = GPIO_BIT(gpio);
325 kona_gpio = irq_data_get_irq_chip_data(d);
326 reg_base = kona_gpio->reg_base;
327 spin_lock_irqsave(&kona_gpio->lock, flags);
328 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
330 val = readl(reg_base + GPIO_INT_MASK(bank_id));
332 writel(val, reg_base + GPIO_INT_MASK(bank_id));
334 bcm_kona_gpio_lock_bank(reg_base, bank_id);
335 spin_unlock_irqrestore(&kona_gpio->lock, flags);
338 static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
340 struct bcm_kona_gpio *kona_gpio;
341 void __iomem *reg_base;
343 int bank_id = GPIO_BANK(gpio);
344 int bit = GPIO_BIT(gpio);
348 kona_gpio = irq_data_get_irq_chip_data(d);
349 reg_base = kona_gpio->reg_base;
350 spin_lock_irqsave(&kona_gpio->lock, flags);
351 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
353 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
355 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
357 bcm_kona_gpio_lock_bank(reg_base, bank_id);
358 spin_unlock_irqrestore(&kona_gpio->lock, flags);
361 static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
363 struct bcm_kona_gpio *kona_gpio;
364 void __iomem *reg_base;
369 int bank_id = GPIO_BANK(gpio);
371 kona_gpio = irq_data_get_irq_chip_data(d);
372 reg_base = kona_gpio->reg_base;
373 switch (type & IRQ_TYPE_SENSE_MASK) {
374 case IRQ_TYPE_EDGE_RISING:
375 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
378 case IRQ_TYPE_EDGE_FALLING:
379 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
382 case IRQ_TYPE_EDGE_BOTH:
383 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
386 case IRQ_TYPE_LEVEL_HIGH:
387 case IRQ_TYPE_LEVEL_LOW:
388 /* BCM GPIO doesn't support level triggering */
390 dev_err(kona_gpio->gpio_chip.dev,
391 "Invalid BCM GPIO irq type 0x%x\n", type);
395 spin_lock_irqsave(&kona_gpio->lock, flags);
396 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
398 val = readl(reg_base + GPIO_CONTROL(gpio));
399 val &= ~GPIO_GPCTR0_ITR_MASK;
400 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
401 writel(val, reg_base + GPIO_CONTROL(gpio));
403 bcm_kona_gpio_lock_bank(reg_base, bank_id);
404 spin_unlock_irqrestore(&kona_gpio->lock, flags);
409 static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
411 void __iomem *reg_base;
414 struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq);
415 struct irq_chip *chip = irq_desc_get_chip(desc);
417 chained_irq_enter(chip, desc);
420 * For bank interrupts, we can't use chip_data to store the kona_gpio
421 * pointer, since GIC needs it for its own purposes. Therefore, we get
422 * our pointer from the bank structure.
424 reg_base = bank->kona_gpio->reg_base;
426 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
428 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
429 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
430 for_each_set_bit(bit, &sta, 32) {
431 int hwirq = GPIO_PER_BANK * bank_id + bit;
433 irq_find_mapping(bank->kona_gpio->irq_domain,
436 * Clear interrupt before handler is called so we don't
437 * miss any interrupt occurred during executing them.
439 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
440 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
441 /* Invoke interrupt handler */
442 generic_handle_irq(child_irq);
446 bcm_kona_gpio_lock_bank(reg_base, bank_id);
448 chained_irq_exit(chip, desc);
451 static struct irq_chip bcm_gpio_irq_chip = {
452 .name = "bcm-kona-gpio",
453 .irq_ack = bcm_kona_gpio_irq_ack,
454 .irq_mask = bcm_kona_gpio_irq_mask,
455 .irq_unmask = bcm_kona_gpio_irq_unmask,
456 .irq_set_type = bcm_kona_gpio_irq_set_type,
459 static struct __initconst of_device_id bcm_kona_gpio_of_match[] = {
460 { .compatible = "brcm,kona-gpio" },
464 MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
467 * This lock class tells lockdep that GPIO irqs are in a different
468 * category than their parents, so it won't report false recursion.
470 static struct lock_class_key gpio_lock_class;
472 static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
473 irq_hw_number_t hwirq)
477 ret = irq_set_chip_data(irq, d->host_data);
480 irq_set_lockdep_class(irq, &gpio_lock_class);
481 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
483 set_irq_flags(irq, IRQF_VALID);
485 irq_set_noprobe(irq);
491 static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
493 irq_set_chip_and_handler(irq, NULL, NULL);
494 irq_set_chip_data(irq, NULL);
497 static struct irq_domain_ops bcm_kona_irq_ops = {
498 .map = bcm_kona_gpio_irq_map,
499 .unmap = bcm_kona_gpio_irq_unmap,
500 .xlate = irq_domain_xlate_twocell,
503 static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
505 void __iomem *reg_base;
508 reg_base = kona_gpio->reg_base;
509 /* disable interrupts and clear status */
510 for (i = 0; i < kona_gpio->num_bank; i++) {
511 bcm_kona_gpio_unlock_bank(reg_base, i);
512 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
513 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
514 bcm_kona_gpio_lock_bank(reg_base, i);
518 static int bcm_kona_gpio_probe(struct platform_device *pdev)
520 struct device *dev = &pdev->dev;
521 const struct of_device_id *match;
522 struct resource *res;
523 struct bcm_kona_gpio_bank *bank;
524 struct bcm_kona_gpio *kona_gpio;
525 struct gpio_chip *chip;
529 match = of_match_device(bcm_kona_gpio_of_match, dev);
531 dev_err(dev, "Failed to find gpio controller\n");
535 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
539 kona_gpio->gpio_chip = template_chip;
540 chip = &kona_gpio->gpio_chip;
541 kona_gpio->num_bank = of_irq_count(dev->of_node);
542 if (kona_gpio->num_bank == 0) {
543 dev_err(dev, "Couldn't determine # GPIO banks\n");
546 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
547 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
551 kona_gpio->banks = devm_kzalloc(dev,
552 kona_gpio->num_bank *
553 sizeof(*kona_gpio->banks), GFP_KERNEL);
554 if (!kona_gpio->banks)
557 kona_gpio->pdev = pdev;
558 platform_set_drvdata(pdev, kona_gpio);
559 chip->of_node = dev->of_node;
560 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
562 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
566 if (!kona_gpio->irq_domain) {
567 dev_err(dev, "Couldn't allocate IRQ domain\n");
571 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
572 kona_gpio->reg_base = devm_ioremap_resource(dev, res);
573 if (IS_ERR(kona_gpio->reg_base)) {
578 for (i = 0; i < kona_gpio->num_bank; i++) {
579 bank = &kona_gpio->banks[i];
581 bank->irq = platform_get_irq(pdev, i);
582 bank->kona_gpio = kona_gpio;
584 dev_err(dev, "Couldn't get IRQ for bank %d", i);
590 dev_info(&pdev->dev, "Setting up Kona GPIO at 0x%p (phys %#x)\n",
591 kona_gpio->reg_base, res->start);
593 bcm_kona_gpio_reset(kona_gpio);
595 ret = gpiochip_add(chip);
597 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
600 for (i = 0; i < chip->ngpio; i++) {
601 int irq = bcm_kona_gpio_to_irq(chip, i);
602 irq_set_lockdep_class(irq, &gpio_lock_class);
603 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip,
606 set_irq_flags(irq, IRQF_VALID);
608 irq_set_noprobe(irq);
611 for (i = 0; i < kona_gpio->num_bank; i++) {
612 bank = &kona_gpio->banks[i];
613 irq_set_chained_handler(bank->irq, bcm_kona_gpio_irq_handler);
614 irq_set_handler_data(bank->irq, bank);
617 spin_lock_init(&kona_gpio->lock);
622 irq_domain_remove(kona_gpio->irq_domain);
627 static struct platform_driver bcm_kona_gpio_driver = {
629 .name = "bcm-kona-gpio",
630 .owner = THIS_MODULE,
631 .of_match_table = bcm_kona_gpio_of_match,
633 .probe = bcm_kona_gpio_probe,
636 module_platform_driver(bcm_kona_gpio_driver);
638 MODULE_AUTHOR("Broadcom");
639 MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
640 MODULE_LICENSE("GPL v2");