2 * Generic driver for memory-mapped GPIO controllers.
4 * Copyright 2008 MontaVista Software, Inc.
5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
14 * ..The simplest form of a GPIO controller that the driver supports is``
15 * `.just a single "data" register, where GPIO state can be read and/or `
16 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
19 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
20 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
21 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
22 `....trivial..'~`.```.```
24 * .```````~~~~`..`.``.``.
25 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
26 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
27 * . register the device with -be`. .with a pair of set/clear-bit registers ,
28 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
29 * ``.`.``...``` ```.. output pins are also supported.`
30 * ^^ `````.`````````.,``~``~``~~``````
32 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
33 * .. The expectation is that in at least some cases . ,-~~~-,
34 * .this will be used with roll-your-own ASIC/FPGA .` \ /
35 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
36 * ..````````......``````````` \o_
40 * ...`````~~`.....``.`..........``````.`.``.```........``.
41 * ` 8, 16, 32 and 64 bits registers are supported, and``.
42 * . the number of GPIOs is determined by the width of ~
43 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
47 #include <linux/init.h>
48 #include <linux/err.h>
49 #include <linux/bug.h>
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/spinlock.h>
53 #include <linux/compiler.h>
54 #include <linux/types.h>
55 #include <linux/errno.h>
56 #include <linux/log2.h>
57 #include <linux/ioport.h>
59 #include <linux/gpio.h>
60 #include <linux/slab.h>
61 #include <linux/platform_device.h>
62 #include <linux/mod_devicetable.h>
63 #include <linux/basic_mmio_gpio.h>
65 static void bgpio_write8(void __iomem *reg, unsigned long data)
70 static unsigned long bgpio_read8(void __iomem *reg)
75 static void bgpio_write16(void __iomem *reg, unsigned long data)
80 static unsigned long bgpio_read16(void __iomem *reg)
85 static void bgpio_write32(void __iomem *reg, unsigned long data)
90 static unsigned long bgpio_read32(void __iomem *reg)
95 #if BITS_PER_LONG >= 64
96 static void bgpio_write64(void __iomem *reg, unsigned long data)
101 static unsigned long bgpio_read64(void __iomem *reg)
105 #endif /* BITS_PER_LONG >= 64 */
107 static void bgpio_write16be(void __iomem *reg, unsigned long data)
109 iowrite16be(data, reg);
112 static unsigned long bgpio_read16be(void __iomem *reg)
114 return ioread16be(reg);
117 static void bgpio_write32be(void __iomem *reg, unsigned long data)
119 iowrite32be(data, reg);
122 static unsigned long bgpio_read32be(void __iomem *reg)
124 return ioread32be(reg);
127 static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
132 static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
135 return 1 << (bgc->bits - 1 - pin);
138 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
140 struct bgpio_chip *bgc = to_bgpio_chip(gc);
142 return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
145 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
147 struct bgpio_chip *bgc = to_bgpio_chip(gc);
148 unsigned long mask = bgc->pin2mask(bgc, gpio);
151 spin_lock_irqsave(&bgc->lock, flags);
158 bgc->write_reg(bgc->reg_dat, bgc->data);
160 spin_unlock_irqrestore(&bgc->lock, flags);
163 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
166 struct bgpio_chip *bgc = to_bgpio_chip(gc);
167 unsigned long mask = bgc->pin2mask(bgc, gpio);
170 bgc->write_reg(bgc->reg_set, mask);
172 bgc->write_reg(bgc->reg_clr, mask);
175 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
177 struct bgpio_chip *bgc = to_bgpio_chip(gc);
178 unsigned long mask = bgc->pin2mask(bgc, gpio);
181 spin_lock_irqsave(&bgc->lock, flags);
188 bgc->write_reg(bgc->reg_set, bgc->data);
190 spin_unlock_irqrestore(&bgc->lock, flags);
193 static void bgpio_multiple_get_masks(struct bgpio_chip *bgc,
194 unsigned long *mask, unsigned long *bits,
195 unsigned long *set_mask,
196 unsigned long *clear_mask)
203 for (i = 0; i < bgc->bits; i++) {
206 if (__test_and_clear_bit(i, mask)) {
207 if (test_bit(i, bits))
208 *set_mask |= bgc->pin2mask(bgc, i);
210 *clear_mask |= bgc->pin2mask(bgc, i);
215 static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc,
221 unsigned long set_mask, clear_mask;
223 spin_lock_irqsave(&bgc->lock, flags);
225 bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
227 bgc->data |= set_mask;
228 bgc->data &= ~clear_mask;
230 bgc->write_reg(reg, bgc->data);
232 spin_unlock_irqrestore(&bgc->lock, flags);
235 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
238 struct bgpio_chip *bgc = to_bgpio_chip(gc);
240 bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat);
243 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
246 struct bgpio_chip *bgc = to_bgpio_chip(gc);
248 bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set);
251 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
255 struct bgpio_chip *bgc = to_bgpio_chip(gc);
256 unsigned long set_mask, clear_mask;
258 bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
261 bgc->write_reg(bgc->reg_set, set_mask);
263 bgc->write_reg(bgc->reg_clr, clear_mask);
266 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
271 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
274 gc->set(gc, gpio, val);
279 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
281 struct bgpio_chip *bgc = to_bgpio_chip(gc);
284 spin_lock_irqsave(&bgc->lock, flags);
286 bgc->dir &= ~bgc->pin2mask(bgc, gpio);
287 bgc->write_reg(bgc->reg_dir, bgc->dir);
289 spin_unlock_irqrestore(&bgc->lock, flags);
294 static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
296 struct bgpio_chip *bgc = to_bgpio_chip(gc);
299 gc->set(gc, gpio, val);
301 spin_lock_irqsave(&bgc->lock, flags);
303 bgc->dir |= bgc->pin2mask(bgc, gpio);
304 bgc->write_reg(bgc->reg_dir, bgc->dir);
306 spin_unlock_irqrestore(&bgc->lock, flags);
311 static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
313 struct bgpio_chip *bgc = to_bgpio_chip(gc);
316 spin_lock_irqsave(&bgc->lock, flags);
318 bgc->dir |= bgc->pin2mask(bgc, gpio);
319 bgc->write_reg(bgc->reg_dir, bgc->dir);
321 spin_unlock_irqrestore(&bgc->lock, flags);
326 static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
328 struct bgpio_chip *bgc = to_bgpio_chip(gc);
331 gc->set(gc, gpio, val);
333 spin_lock_irqsave(&bgc->lock, flags);
335 bgc->dir &= ~bgc->pin2mask(bgc, gpio);
336 bgc->write_reg(bgc->reg_dir, bgc->dir);
338 spin_unlock_irqrestore(&bgc->lock, flags);
343 static int bgpio_setup_accessors(struct device *dev,
344 struct bgpio_chip *bgc,
351 bgc->read_reg = bgpio_read8;
352 bgc->write_reg = bgpio_write8;
356 bgc->read_reg = bgpio_read16be;
357 bgc->write_reg = bgpio_write16be;
359 bgc->read_reg = bgpio_read16;
360 bgc->write_reg = bgpio_write16;
365 bgc->read_reg = bgpio_read32be;
366 bgc->write_reg = bgpio_write32be;
368 bgc->read_reg = bgpio_read32;
369 bgc->write_reg = bgpio_write32;
372 #if BITS_PER_LONG >= 64
376 "64 bit big endian byte order unsupported\n");
379 bgc->read_reg = bgpio_read64;
380 bgc->write_reg = bgpio_write64;
383 #endif /* BITS_PER_LONG >= 64 */
385 dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
389 bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
395 * Create the device and allocate the resources. For setting GPIO's there are
396 * three supported configurations:
398 * - single input/output register resource (named "dat").
399 * - set/clear pair (named "set" and "clr").
400 * - single output register resource and single input resource ("set" and
403 * For the single output register, this drives a 1 by setting a bit and a zero
404 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
405 * in the set register and clears it by setting a bit in the clear register.
406 * The configuration is detected by which resources are present.
408 * For setting the GPIO direction, there are three supported configurations:
410 * - simple bidirection GPIO that requires no configuration.
411 * - an output direction register (named "dirout") where a 1 bit
412 * indicates the GPIO is an output.
413 * - an input direction register (named "dirin") where a 1 bit indicates
414 * the GPIO is an input.
416 static int bgpio_setup_io(struct bgpio_chip *bgc,
429 bgc->gc.set = bgpio_set_with_clear;
430 bgc->gc.set_multiple = bgpio_set_multiple_with_clear;
431 } else if (set && !clr) {
433 bgc->gc.set = bgpio_set_set;
434 bgc->gc.set_multiple = bgpio_set_multiple_set;
436 bgc->gc.set = bgpio_set;
437 bgc->gc.set_multiple = bgpio_set_multiple;
440 bgc->gc.get = bgpio_get;
445 static int bgpio_setup_direction(struct bgpio_chip *bgc,
446 void __iomem *dirout,
449 if (dirout && dirin) {
452 bgc->reg_dir = dirout;
453 bgc->gc.direction_output = bgpio_dir_out;
454 bgc->gc.direction_input = bgpio_dir_in;
456 bgc->reg_dir = dirin;
457 bgc->gc.direction_output = bgpio_dir_out_inv;
458 bgc->gc.direction_input = bgpio_dir_in_inv;
460 bgc->gc.direction_output = bgpio_simple_dir_out;
461 bgc->gc.direction_input = bgpio_simple_dir_in;
467 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
469 if (gpio_pin < chip->ngpio)
475 int bgpio_remove(struct bgpio_chip *bgc)
477 gpiochip_remove(&bgc->gc);
480 EXPORT_SYMBOL_GPL(bgpio_remove);
482 int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
483 unsigned long sz, void __iomem *dat, void __iomem *set,
484 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
489 if (!is_power_of_2(sz))
493 if (bgc->bits > BITS_PER_LONG)
496 spin_lock_init(&bgc->lock);
498 bgc->gc.label = dev_name(dev);
500 bgc->gc.ngpio = bgc->bits;
501 bgc->gc.request = bgpio_request;
503 ret = bgpio_setup_io(bgc, dat, set, clr);
507 ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
508 flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
512 ret = bgpio_setup_direction(bgc, dirout, dirin);
516 bgc->data = bgc->read_reg(bgc->reg_dat);
517 if (bgc->gc.set == bgpio_set_set &&
518 !(flags & BGPIOF_UNREADABLE_REG_SET))
519 bgc->data = bgc->read_reg(bgc->reg_set);
520 if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
521 bgc->dir = bgc->read_reg(bgc->reg_dir);
525 EXPORT_SYMBOL_GPL(bgpio_init);
527 #ifdef CONFIG_GPIO_GENERIC_PLATFORM
529 static void __iomem *bgpio_map(struct platform_device *pdev,
531 resource_size_t sane_sz,
534 struct device *dev = &pdev->dev;
536 resource_size_t start;
542 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
546 sz = resource_size(r);
553 if (!devm_request_mem_region(dev, start, sz, r->name)) {
558 ret = devm_ioremap(dev, start, sz);
567 static int bgpio_pdev_probe(struct platform_device *pdev)
569 struct device *dev = &pdev->dev;
574 void __iomem *dirout;
577 unsigned long flags = pdev->id_entry->driver_data;
579 struct bgpio_chip *bgc;
580 struct bgpio_pdata *pdata = dev_get_platdata(dev);
582 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
586 sz = resource_size(r);
588 dat = bgpio_map(pdev, "dat", sz, &err);
590 return err ? err : -EINVAL;
592 set = bgpio_map(pdev, "set", sz, &err);
596 clr = bgpio_map(pdev, "clr", sz, &err);
600 dirout = bgpio_map(pdev, "dirout", sz, &err);
604 dirin = bgpio_map(pdev, "dirin", sz, &err);
608 bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
612 err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
618 bgc->gc.label = pdata->label;
619 bgc->gc.base = pdata->base;
620 if (pdata->ngpio > 0)
621 bgc->gc.ngpio = pdata->ngpio;
624 platform_set_drvdata(pdev, bgc);
626 return gpiochip_add(&bgc->gc);
629 static int bgpio_pdev_remove(struct platform_device *pdev)
631 struct bgpio_chip *bgc = platform_get_drvdata(pdev);
633 return bgpio_remove(bgc);
636 static const struct platform_device_id bgpio_id_table[] = {
638 .name = "basic-mmio-gpio",
641 .name = "basic-mmio-gpio-be",
642 .driver_data = BGPIOF_BIG_ENDIAN,
646 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
648 static struct platform_driver bgpio_driver = {
650 .name = "basic-mmio-gpio",
652 .id_table = bgpio_id_table,
653 .probe = bgpio_pdev_probe,
654 .remove = bgpio_pdev_remove,
657 module_platform_driver(bgpio_driver);
659 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
661 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
662 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
663 MODULE_LICENSE("GPL");