2 * Moorestown platform Langwell chip GPIO driver
4 * Copyright (c) 2008, 2009, 2013, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * Moorestown platform Langwell chip.
22 * Medfield platform Penwell chip.
23 * Clovertrail platform Cloverview chip.
24 * Merrifield platform Tangier chip.
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/platform_device.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/stddef.h>
33 #include <linux/interrupt.h>
34 #include <linux/init.h>
35 #include <linux/irq.h>
37 #include <linux/gpio.h>
38 #include <linux/slab.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/irqdomain.h>
42 #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
43 #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
46 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
47 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
48 * registers to control them, so we only define the order here instead of a
49 * structure, to get a bit offset for a pin (use GPDR as an example):
54 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
56 * so the bit of reg_addr is to control pin offset's GPDR feature
60 GPLR = 0, /* pin level read-only */
61 GPDR, /* pin direction */
64 GRER, /* rising edge detect */
65 GFER, /* falling edge detect */
66 GEDR, /* edge detect result */
67 GAFR, /* alt function */
70 /* intel_mid gpio driver data */
71 struct intel_mid_gpio_ddata {
72 u16 ngpio; /* number of gpio pins */
73 u32 gplr_offset; /* offset of first GPLR register from base */
74 u32 flis_base; /* base address of FLIS registers */
75 u32 flis_len; /* length of FLIS registers */
76 u32 (*get_flis_offset)(int gpio);
77 u32 chip_irq_type; /* chip interrupt type */
80 struct intel_mid_gpio {
81 struct gpio_chip chip;
82 void __iomem *reg_base;
85 struct irq_domain *domain;
88 #define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)
90 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
91 enum GPIO_REG reg_type)
93 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
94 unsigned nreg = chip->ngpio / 32;
97 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
100 static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
101 enum GPIO_REG reg_type)
103 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
104 unsigned nreg = chip->ngpio / 32;
105 u8 reg = offset / 16;
107 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
110 static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
112 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
113 u32 value = readl(gafr);
114 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
117 value &= ~(3 << shift);
123 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
125 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
127 return readl(gplr) & BIT(offset % 32);
130 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
132 void __iomem *gpsr, *gpcr;
135 gpsr = gpio_reg(chip, offset, GPSR);
136 writel(BIT(offset % 32), gpsr);
138 gpcr = gpio_reg(chip, offset, GPCR);
139 writel(BIT(offset % 32), gpcr);
143 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
145 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
146 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
151 pm_runtime_get(&priv->pdev->dev);
153 spin_lock_irqsave(&priv->lock, flags);
155 value &= ~BIT(offset % 32);
157 spin_unlock_irqrestore(&priv->lock, flags);
160 pm_runtime_put(&priv->pdev->dev);
165 static int intel_gpio_direction_output(struct gpio_chip *chip,
166 unsigned offset, int value)
168 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
169 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
172 intel_gpio_set(chip, offset, value);
175 pm_runtime_get(&priv->pdev->dev);
177 spin_lock_irqsave(&priv->lock, flags);
179 value |= BIT(offset % 32);
181 spin_unlock_irqrestore(&priv->lock, flags);
184 pm_runtime_put(&priv->pdev->dev);
189 static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
191 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
192 return irq_create_mapping(priv->domain, offset);
195 static int intel_mid_irq_type(struct irq_data *d, unsigned type)
197 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
198 u32 gpio = irqd_to_hwirq(d);
201 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
202 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
204 if (gpio >= priv->chip.ngpio)
208 pm_runtime_get(&priv->pdev->dev);
210 spin_lock_irqsave(&priv->lock, flags);
211 if (type & IRQ_TYPE_EDGE_RISING)
212 value = readl(grer) | BIT(gpio % 32);
214 value = readl(grer) & (~BIT(gpio % 32));
217 if (type & IRQ_TYPE_EDGE_FALLING)
218 value = readl(gfer) | BIT(gpio % 32);
220 value = readl(gfer) & (~BIT(gpio % 32));
222 spin_unlock_irqrestore(&priv->lock, flags);
225 pm_runtime_put(&priv->pdev->dev);
230 static void intel_mid_irq_unmask(struct irq_data *d)
234 static void intel_mid_irq_mask(struct irq_data *d)
238 static unsigned int intel_mid_irq_startup(struct irq_data *d)
240 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
242 if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d)))
243 dev_err(priv->chip.dev,
244 "unable to lock HW IRQ %lu for IRQ\n",
246 intel_mid_irq_unmask(d);
250 static void intel_mid_irq_shutdown(struct irq_data *d)
252 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
254 intel_mid_irq_mask(d);
255 gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d));
258 static struct irq_chip intel_mid_irqchip = {
259 .name = "INTEL_MID-GPIO",
260 .irq_mask = intel_mid_irq_mask,
261 .irq_unmask = intel_mid_irq_unmask,
262 .irq_set_type = intel_mid_irq_type,
263 .irq_startup = intel_mid_irq_startup,
264 .irq_shutdown = intel_mid_irq_shutdown,
267 static const struct intel_mid_gpio_ddata gpio_lincroft = {
271 static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
273 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
276 static const struct intel_mid_gpio_ddata gpio_penwell_core = {
278 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
281 static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
283 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
286 static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
288 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
291 static const struct intel_mid_gpio_ddata gpio_tangier = {
294 .flis_base = 0xff0c0000,
296 .get_flis_offset = NULL,
297 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
300 static const struct pci_device_id intel_gpio_ids[] = {
303 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
304 .driver_data = (kernel_ulong_t)&gpio_lincroft,
308 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
309 .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
313 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
314 .driver_data = (kernel_ulong_t)&gpio_penwell_core,
318 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
319 .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
322 /* Cloverview Core */
323 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
324 .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
328 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
329 .driver_data = (kernel_ulong_t)&gpio_tangier,
333 MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
335 static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
337 struct irq_data *data = irq_desc_get_irq_data(desc);
338 struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
339 struct irq_chip *chip = irq_data_get_irq_chip(data);
340 u32 base, gpio, mask;
341 unsigned long pending;
344 /* check GPIO controller to check which pin triggered the interrupt */
345 for (base = 0; base < priv->chip.ngpio; base += 32) {
346 gedr = gpio_reg(&priv->chip, base, GEDR);
347 while ((pending = readl(gedr))) {
348 gpio = __ffs(pending);
350 /* Clear before handling so we can't lose an edge */
352 generic_handle_irq(irq_find_mapping(priv->domain,
360 static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
365 for (base = 0; base < priv->chip.ngpio; base += 32) {
366 /* Clear the rising-edge detect register */
367 reg = gpio_reg(&priv->chip, base, GRER);
369 /* Clear the falling-edge detect register */
370 reg = gpio_reg(&priv->chip, base, GFER);
372 /* Clear the edge detect status register */
373 reg = gpio_reg(&priv->chip, base, GEDR);
378 static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
379 irq_hw_number_t hwirq)
381 struct intel_mid_gpio *priv = d->host_data;
383 irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq);
384 irq_set_chip_data(irq, priv);
385 irq_set_irq_type(irq, IRQ_TYPE_NONE);
390 static const struct irq_domain_ops intel_gpio_irq_ops = {
391 .map = intel_gpio_irq_map,
392 .xlate = irq_domain_xlate_twocell,
395 static int intel_gpio_runtime_idle(struct device *dev)
397 pm_schedule_suspend(dev, 500);
401 static const struct dev_pm_ops intel_gpio_pm_ops = {
402 SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
405 static int intel_gpio_probe(struct pci_dev *pdev,
406 const struct pci_device_id *id)
409 struct intel_mid_gpio *priv;
413 struct intel_mid_gpio_ddata *ddata =
414 (struct intel_mid_gpio_ddata *)id->driver_data;
416 retval = pcim_enable_device(pdev);
420 retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
422 dev_err(&pdev->dev, "I/O memory mapping error\n");
426 base = pcim_iomap_table(pdev)[1];
428 irq_base = readl(base);
429 gpio_base = readl(sizeof(u32) + base);
431 /* release the IO mapping, since we already get the info from bar1 */
432 pcim_iounmap_regions(pdev, 1 << 1);
434 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
436 dev_err(&pdev->dev, "can't allocate chip data\n");
440 priv->reg_base = pcim_iomap_table(pdev)[0];
441 priv->chip.label = dev_name(&pdev->dev);
442 priv->chip.dev = &pdev->dev;
443 priv->chip.request = intel_gpio_request;
444 priv->chip.direction_input = intel_gpio_direction_input;
445 priv->chip.direction_output = intel_gpio_direction_output;
446 priv->chip.get = intel_gpio_get;
447 priv->chip.set = intel_gpio_set;
448 priv->chip.to_irq = intel_gpio_to_irq;
449 priv->chip.base = gpio_base;
450 priv->chip.ngpio = ddata->ngpio;
451 priv->chip.can_sleep = false;
454 spin_lock_init(&priv->lock);
456 priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
457 irq_base, &intel_gpio_irq_ops, priv);
461 pci_set_drvdata(pdev, priv);
462 retval = gpiochip_add(&priv->chip);
464 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
468 intel_mid_irq_init_hw(priv);
470 irq_set_handler_data(pdev->irq, priv);
471 irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);
473 pm_runtime_put_noidle(&pdev->dev);
474 pm_runtime_allow(&pdev->dev);
479 static struct pci_driver intel_gpio_driver = {
480 .name = "intel_mid_gpio",
481 .id_table = intel_gpio_ids,
482 .probe = intel_gpio_probe,
484 .pm = &intel_gpio_pm_ops,
488 static int __init intel_gpio_init(void)
490 return pci_register_driver(&intel_gpio_driver);
493 device_initcall(intel_gpio_init);