2 * Moorestown platform Langwell chip GPIO driver
4 * Copyright (c) 2008 - 2009, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * Moorestown platform Langwell chip.
22 * Medfield platform Penwell chip.
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/kernel.h>
30 #include <linux/delay.h>
31 #include <linux/stddef.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/irq.h>
36 #include <linux/gpio.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
41 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
42 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
43 * registers to control them, so we only define the order here instead of a
44 * structure, to get a bit offset for a pin (use GPDR as an example):
49 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
51 * so the bit of reg_addr is to control pin offset's GPDR feature
55 GPLR = 0, /* pin level read-only */
56 GPDR, /* pin direction */
59 GRER, /* rising edge detect */
60 GFER, /* falling edge detect */
61 GEDR, /* edge detect result */
62 GAFR, /* alt function */
66 struct gpio_chip chip;
73 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
74 enum GPIO_REG reg_type)
76 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
77 unsigned nreg = chip->ngpio / 32;
81 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
85 static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
86 enum GPIO_REG reg_type)
88 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
89 unsigned nreg = chip->ngpio / 32;
93 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
97 static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
99 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
100 u32 value = readl(gafr);
101 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
104 value &= ~(3 << shift);
110 static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
112 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
114 return readl(gplr) & BIT(offset % 32);
117 static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
119 void __iomem *gpsr, *gpcr;
122 gpsr = gpio_reg(chip, offset, GPSR);
123 writel(BIT(offset % 32), gpsr);
125 gpcr = gpio_reg(chip, offset, GPCR);
126 writel(BIT(offset % 32), gpcr);
130 static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
132 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
133 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
138 pm_runtime_get(&lnw->pdev->dev);
140 spin_lock_irqsave(&lnw->lock, flags);
142 value &= ~BIT(offset % 32);
144 spin_unlock_irqrestore(&lnw->lock, flags);
147 pm_runtime_put(&lnw->pdev->dev);
152 static int lnw_gpio_direction_output(struct gpio_chip *chip,
153 unsigned offset, int value)
155 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
156 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
159 lnw_gpio_set(chip, offset, value);
162 pm_runtime_get(&lnw->pdev->dev);
164 spin_lock_irqsave(&lnw->lock, flags);
166 value |= BIT(offset % 32);
168 spin_unlock_irqrestore(&lnw->lock, flags);
171 pm_runtime_put(&lnw->pdev->dev);
176 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
178 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
179 return lnw->irq_base + offset;
182 static int lnw_irq_type(struct irq_data *d, unsigned type)
184 struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
185 u32 gpio = d->irq - lnw->irq_base;
188 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
189 void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
191 if (gpio >= lnw->chip.ngpio)
195 pm_runtime_get(&lnw->pdev->dev);
197 spin_lock_irqsave(&lnw->lock, flags);
198 if (type & IRQ_TYPE_EDGE_RISING)
199 value = readl(grer) | BIT(gpio % 32);
201 value = readl(grer) & (~BIT(gpio % 32));
204 if (type & IRQ_TYPE_EDGE_FALLING)
205 value = readl(gfer) | BIT(gpio % 32);
207 value = readl(gfer) & (~BIT(gpio % 32));
209 spin_unlock_irqrestore(&lnw->lock, flags);
212 pm_runtime_put(&lnw->pdev->dev);
217 static void lnw_irq_unmask(struct irq_data *d)
221 static void lnw_irq_mask(struct irq_data *d)
225 static struct irq_chip lnw_irqchip = {
227 .irq_mask = lnw_irq_mask,
228 .irq_unmask = lnw_irq_unmask,
229 .irq_set_type = lnw_irq_type,
232 static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
233 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
234 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
235 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
238 MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
240 static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
242 struct irq_data *data = irq_desc_get_irq_data(desc);
243 struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
244 struct irq_chip *chip = irq_data_get_irq_chip(data);
245 u32 base, gpio, mask;
246 unsigned long pending;
249 /* check GPIO controller to check which pin triggered the interrupt */
250 for (base = 0; base < lnw->chip.ngpio; base += 32) {
251 gedr = gpio_reg(&lnw->chip, base, GEDR);
252 pending = readl(gedr);
254 gpio = __ffs(pending);
257 /* Clear before handling so we can't lose an edge */
259 generic_handle_irq(lnw->irq_base + base + gpio);
267 static int lnw_gpio_runtime_resume(struct device *dev)
272 static int lnw_gpio_runtime_suspend(struct device *dev)
277 static int lnw_gpio_runtime_idle(struct device *dev)
279 int err = pm_schedule_suspend(dev, 500);
288 #define lnw_gpio_runtime_suspend NULL
289 #define lnw_gpio_runtime_resume NULL
290 #define lnw_gpio_runtime_idle NULL
293 static const struct dev_pm_ops lnw_gpio_pm_ops = {
294 .runtime_suspend = lnw_gpio_runtime_suspend,
295 .runtime_resume = lnw_gpio_runtime_resume,
296 .runtime_idle = lnw_gpio_runtime_idle,
299 static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
300 const struct pci_device_id *id)
304 resource_size_t start, len;
305 struct lnw_gpio *lnw;
310 retval = pci_enable_device(pdev);
314 retval = pci_request_regions(pdev, "langwell_gpio");
316 dev_err(&pdev->dev, "error requesting resources\n");
319 /* get the irq_base from bar1 */
320 start = pci_resource_start(pdev, 1);
321 len = pci_resource_len(pdev, 1);
322 base = ioremap_nocache(start, len);
324 dev_err(&pdev->dev, "error mapping bar1\n");
327 irq_base = *(u32 *)base;
328 gpio_base = *((u32 *)base + 1);
329 /* release the IO mapping, since we already get the info from bar1 */
331 /* get the register base from bar0 */
332 start = pci_resource_start(pdev, 0);
333 len = pci_resource_len(pdev, 0);
334 base = ioremap_nocache(start, len);
336 dev_err(&pdev->dev, "error mapping bar0\n");
341 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
343 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
347 lnw->reg_base = base;
348 lnw->irq_base = irq_base;
349 lnw->chip.label = dev_name(&pdev->dev);
350 lnw->chip.request = lnw_gpio_request;
351 lnw->chip.direction_input = lnw_gpio_direction_input;
352 lnw->chip.direction_output = lnw_gpio_direction_output;
353 lnw->chip.get = lnw_gpio_get;
354 lnw->chip.set = lnw_gpio_set;
355 lnw->chip.to_irq = lnw_gpio_to_irq;
356 lnw->chip.base = gpio_base;
357 lnw->chip.ngpio = id->driver_data;
358 lnw->chip.can_sleep = 0;
360 pci_set_drvdata(pdev, lnw);
361 retval = gpiochip_add(&lnw->chip);
363 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
366 irq_set_handler_data(pdev->irq, lnw);
367 irq_set_chained_handler(pdev->irq, lnw_irq_handler);
368 for (i = 0; i < lnw->chip.ngpio; i++) {
369 irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
370 handle_simple_irq, "demux");
371 irq_set_chip_data(i + lnw->irq_base, lnw);
374 spin_lock_init(&lnw->lock);
376 pm_runtime_put_noidle(&pdev->dev);
377 pm_runtime_allow(&pdev->dev);
385 pci_release_regions(pdev);
387 pci_disable_device(pdev);
392 static struct pci_driver lnw_gpio_driver = {
393 .name = "langwell_gpio",
394 .id_table = lnw_gpio_ids,
395 .probe = lnw_gpio_probe,
397 .pm = &lnw_gpio_pm_ops,
402 static int __devinit wp_gpio_probe(struct platform_device *pdev)
404 struct lnw_gpio *lnw;
405 struct gpio_chip *gc;
409 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
413 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
416 "can't allocate whitneypoint_gpio chip data\n");
419 lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
420 if (lnw->reg_base == NULL) {
424 spin_lock_init(&lnw->lock);
426 gc->label = dev_name(&pdev->dev);
427 gc->owner = THIS_MODULE;
428 gc->direction_input = lnw_gpio_direction_input;
429 gc->direction_output = lnw_gpio_direction_output;
430 gc->get = lnw_gpio_get;
431 gc->set = lnw_gpio_set;
436 retval = gpiochip_add(gc);
438 dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
442 platform_set_drvdata(pdev, lnw);
445 iounmap(lnw->reg_base);
451 static int __devexit wp_gpio_remove(struct platform_device *pdev)
453 struct lnw_gpio *lnw = platform_get_drvdata(pdev);
455 err = gpiochip_remove(&lnw->chip);
457 dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
458 iounmap(lnw->reg_base);
460 platform_set_drvdata(pdev, NULL);
464 static struct platform_driver wp_gpio_driver = {
465 .probe = wp_gpio_probe,
466 .remove = __devexit_p(wp_gpio_remove),
469 .owner = THIS_MODULE,
473 static int __init lnw_gpio_init(void)
476 ret = pci_register_driver(&lnw_gpio_driver);
479 ret = platform_driver_register(&wp_gpio_driver);
481 pci_unregister_driver(&lnw_gpio_driver);
485 device_initcall(lnw_gpio_init);