2 * GPIOs on MPC512x/8349/8572/8610 and compatible
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/gpio.h>
20 #include <linux/slab.h>
21 #include <linux/irq.h>
23 #define MPC8XXX_GPIO_PINS 32
31 #define GPIO_ICR2 0x18
33 struct mpc8xxx_gpio_chip {
34 struct of_mm_gpio_chip mm_gc;
38 * shadowed data register to be able to clear/set output pins in
39 * open drain mode safely
42 struct irq_domain *irq;
44 const void *of_dev_id_data;
47 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
49 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
52 static inline struct mpc8xxx_gpio_chip *
53 to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
55 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
58 static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
60 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
62 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
65 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
66 * defined as output cannot be determined by reading GPDAT register,
67 * so we use shadow data register instead. The status of input pins
68 * is determined by reading GPDAT register.
70 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
73 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
74 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
75 u32 out_mask, out_shadow;
77 out_mask = in_be32(mm->regs + GPIO_DIR);
79 val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
80 out_shadow = mpc8xxx_gc->data & out_mask;
82 return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
85 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
89 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
92 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
94 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
95 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
98 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
101 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
103 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
105 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
107 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
110 static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
111 unsigned long *mask, unsigned long *bits)
113 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
114 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
118 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
120 for (i = 0; i < gc->ngpio; i++) {
123 if (__test_and_clear_bit(i, mask)) {
124 if (test_bit(i, bits))
125 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
127 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
131 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
133 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
136 static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
138 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
139 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
142 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
144 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
146 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
151 static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
153 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
154 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
157 mpc8xxx_gpio_set(gc, gpio, val);
159 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
161 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
163 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
168 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
170 /* GPIO 28..31 are input only on MPC5121 */
174 return mpc8xxx_gpio_dir_out(gc, gpio, val);
177 static int mpc5125_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
179 /* GPIO 0..3 are input only on MPC5125 */
183 return mpc8xxx_gpio_dir_out(gc, gpio, val);
186 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
188 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
189 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
191 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
192 return irq_create_mapping(mpc8xxx_gc->irq, offset);
197 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
199 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
200 struct irq_chip *chip = irq_desc_get_chip(desc);
201 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
204 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
206 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
209 chip->irq_eoi(&desc->irq_data);
212 static void mpc8xxx_irq_unmask(struct irq_data *d)
214 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
215 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
218 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
220 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
222 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
225 static void mpc8xxx_irq_mask(struct irq_data *d)
227 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
228 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
231 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
233 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
235 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
238 static void mpc8xxx_irq_ack(struct irq_data *d)
240 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
241 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
243 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
246 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
248 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
249 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
253 case IRQ_TYPE_EDGE_FALLING:
254 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
255 setbits32(mm->regs + GPIO_ICR,
256 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
257 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
260 case IRQ_TYPE_EDGE_BOTH:
261 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
262 clrbits32(mm->regs + GPIO_ICR,
263 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
264 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
274 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
276 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
277 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
278 unsigned long gpio = irqd_to_hwirq(d);
284 reg = mm->regs + GPIO_ICR;
285 shift = (15 - gpio) * 2;
287 reg = mm->regs + GPIO_ICR2;
288 shift = (15 - (gpio % 16)) * 2;
292 case IRQ_TYPE_EDGE_FALLING:
293 case IRQ_TYPE_LEVEL_LOW:
294 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
295 clrsetbits_be32(reg, 3 << shift, 2 << shift);
296 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
299 case IRQ_TYPE_EDGE_RISING:
300 case IRQ_TYPE_LEVEL_HIGH:
301 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
302 clrsetbits_be32(reg, 3 << shift, 1 << shift);
303 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
306 case IRQ_TYPE_EDGE_BOTH:
307 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
308 clrbits32(reg, 3 << shift);
309 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
319 static struct irq_chip mpc8xxx_irq_chip = {
320 .name = "mpc8xxx-gpio",
321 .irq_unmask = mpc8xxx_irq_unmask,
322 .irq_mask = mpc8xxx_irq_mask,
323 .irq_ack = mpc8xxx_irq_ack,
324 /* this might get overwritten in mpc8xxx_probe() */
325 .irq_set_type = mpc8xxx_irq_set_type,
328 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
329 irq_hw_number_t hwirq)
331 irq_set_chip_data(irq, h->host_data);
332 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
337 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
338 .map = mpc8xxx_gpio_irq_map,
339 .xlate = irq_domain_xlate_twocell,
342 struct mpc8xxx_gpio_devtype {
343 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
344 int (*gpio_get)(struct gpio_chip *, unsigned int);
345 int (*irq_set_type)(struct irq_data *, unsigned int);
348 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
349 .gpio_dir_out = mpc5121_gpio_dir_out,
350 .irq_set_type = mpc512x_irq_set_type,
353 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
354 .gpio_dir_out = mpc5125_gpio_dir_out,
355 .irq_set_type = mpc512x_irq_set_type,
358 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
359 .gpio_get = mpc8572_gpio_get,
362 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
363 .gpio_dir_out = mpc8xxx_gpio_dir_out,
364 .gpio_get = mpc8xxx_gpio_get,
365 .irq_set_type = mpc8xxx_irq_set_type,
368 static const struct of_device_id mpc8xxx_gpio_ids[] = {
369 { .compatible = "fsl,mpc8349-gpio", },
370 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
371 { .compatible = "fsl,mpc8610-gpio", },
372 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
373 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
374 { .compatible = "fsl,pq3-gpio", },
375 { .compatible = "fsl,qoriq-gpio", },
379 static int mpc8xxx_probe(struct platform_device *pdev)
381 struct device_node *np = pdev->dev.of_node;
382 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
383 struct of_mm_gpio_chip *mm_gc;
384 struct gpio_chip *gc;
385 const struct of_device_id *id;
386 const struct mpc8xxx_gpio_devtype *devtype =
387 of_device_get_match_data(&pdev->dev);
390 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
394 platform_set_drvdata(pdev, mpc8xxx_gc);
396 raw_spin_lock_init(&mpc8xxx_gc->lock);
398 mm_gc = &mpc8xxx_gc->mm_gc;
401 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
402 gc->ngpio = MPC8XXX_GPIO_PINS;
403 gc->direction_input = mpc8xxx_gpio_dir_in;
406 devtype = &mpc8xxx_gpio_devtype_default;
409 * It's assumed that only a single type of gpio controller is available
410 * on the current machine, so overwriting global data is fine.
412 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
414 gc->direction_output = devtype->gpio_dir_out ?: mpc8xxx_gpio_dir_out;
415 gc->get = devtype->gpio_get ?: mpc8xxx_gpio_get;
416 gc->set = mpc8xxx_gpio_set;
417 gc->set_multiple = mpc8xxx_gpio_set_multiple;
418 gc->to_irq = mpc8xxx_gpio_to_irq;
420 ret = of_mm_gpiochip_add(np, mm_gc);
424 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
425 if (mpc8xxx_gc->irqn == NO_IRQ)
428 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
429 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
430 if (!mpc8xxx_gc->irq)
433 id = of_match_node(mpc8xxx_gpio_ids, np);
435 mpc8xxx_gc->of_dev_id_data = id->data;
437 /* ack and mask all irqs */
438 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
439 out_be32(mm_gc->regs + GPIO_IMR, 0);
441 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
442 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
447 static int mpc8xxx_remove(struct platform_device *pdev)
449 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
451 if (mpc8xxx_gc->irq) {
452 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
453 irq_domain_remove(mpc8xxx_gc->irq);
456 of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
461 static struct platform_driver mpc8xxx_plat_driver = {
462 .probe = mpc8xxx_probe,
463 .remove = mpc8xxx_remove,
465 .name = "gpio-mpc8xxx",
466 .of_match_table = mpc8xxx_gpio_ids,
470 static int __init mpc8xxx_init(void)
472 return platform_driver_register(&mpc8xxx_plat_driver);
475 arch_initcall(mpc8xxx_init);