2 * GPIOs on MPC512x/8349/8572/8610 and compatible
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/gpio.h>
20 #include <linux/slab.h>
21 #include <linux/irq.h>
23 #define MPC8XXX_GPIO_PINS 32
31 #define GPIO_ICR2 0x18
33 struct mpc8xxx_gpio_chip {
34 struct of_mm_gpio_chip mm_gc;
38 * shadowed data register to be able to clear/set output pins in
39 * open drain mode safely
42 struct irq_domain *irq;
44 const void *of_dev_id_data;
47 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
49 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
52 static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
54 struct mpc8xxx_gpio_chip *mpc8xxx_gc =
55 container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
57 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
60 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
61 * defined as output cannot be determined by reading GPDAT register,
62 * so we use shadow data register instead. The status of input pins
63 * is determined by reading GPDAT register.
65 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
68 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
69 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
70 u32 out_mask, out_shadow;
72 out_mask = in_be32(mm->regs + GPIO_DIR);
74 val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
75 out_shadow = mpc8xxx_gc->data & out_mask;
77 return !!((val | out_shadow) & mpc8xxx_gpio2mask(gpio));
80 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
82 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
84 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
87 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
89 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
90 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
93 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
96 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
98 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
100 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
102 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
105 static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
106 unsigned long *mask, unsigned long *bits)
108 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
109 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
113 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
115 for (i = 0; i < gc->ngpio; i++) {
118 if (__test_and_clear_bit(i, mask)) {
119 if (test_bit(i, bits))
120 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
122 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
126 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
128 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
131 static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
133 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
134 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
137 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
139 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
141 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
146 static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
148 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
149 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
152 mpc8xxx_gpio_set(gc, gpio, val);
154 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
156 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
158 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
163 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
165 /* GPIO 28..31 are input only on MPC5121 */
169 return mpc8xxx_gpio_dir_out(gc, gpio, val);
172 static int mpc5125_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
174 /* GPIO 0..3 are input only on MPC5125 */
178 return mpc8xxx_gpio_dir_out(gc, gpio, val);
181 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
183 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
185 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
186 return irq_create_mapping(mpc8xxx_gc->irq, offset);
191 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
193 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
194 struct irq_chip *chip = irq_desc_get_chip(desc);
195 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
198 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
200 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
203 chip->irq_eoi(&desc->irq_data);
206 static void mpc8xxx_irq_unmask(struct irq_data *d)
208 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
209 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
212 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
214 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
216 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
219 static void mpc8xxx_irq_mask(struct irq_data *d)
221 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
222 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
225 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
227 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
229 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
232 static void mpc8xxx_irq_ack(struct irq_data *d)
234 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
235 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
237 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
240 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
242 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
243 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
247 case IRQ_TYPE_EDGE_FALLING:
248 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
249 setbits32(mm->regs + GPIO_ICR,
250 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
251 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
254 case IRQ_TYPE_EDGE_BOTH:
255 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
256 clrbits32(mm->regs + GPIO_ICR,
257 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
258 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
268 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
270 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
271 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
272 unsigned long gpio = irqd_to_hwirq(d);
278 reg = mm->regs + GPIO_ICR;
279 shift = (15 - gpio) * 2;
281 reg = mm->regs + GPIO_ICR2;
282 shift = (15 - (gpio % 16)) * 2;
286 case IRQ_TYPE_EDGE_FALLING:
287 case IRQ_TYPE_LEVEL_LOW:
288 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
289 clrsetbits_be32(reg, 3 << shift, 2 << shift);
290 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
293 case IRQ_TYPE_EDGE_RISING:
294 case IRQ_TYPE_LEVEL_HIGH:
295 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
296 clrsetbits_be32(reg, 3 << shift, 1 << shift);
297 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
300 case IRQ_TYPE_EDGE_BOTH:
301 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
302 clrbits32(reg, 3 << shift);
303 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
313 static struct irq_chip mpc8xxx_irq_chip = {
314 .name = "mpc8xxx-gpio",
315 .irq_unmask = mpc8xxx_irq_unmask,
316 .irq_mask = mpc8xxx_irq_mask,
317 .irq_ack = mpc8xxx_irq_ack,
318 /* this might get overwritten in mpc8xxx_probe() */
319 .irq_set_type = mpc8xxx_irq_set_type,
322 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
323 irq_hw_number_t hwirq)
325 irq_set_chip_data(irq, h->host_data);
326 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
331 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
332 .map = mpc8xxx_gpio_irq_map,
333 .xlate = irq_domain_xlate_twocell,
336 struct mpc8xxx_gpio_devtype {
337 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
338 int (*gpio_get)(struct gpio_chip *, unsigned int);
339 int (*irq_set_type)(struct irq_data *, unsigned int);
342 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
343 .gpio_dir_out = mpc5121_gpio_dir_out,
344 .irq_set_type = mpc512x_irq_set_type,
347 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
348 .gpio_dir_out = mpc5125_gpio_dir_out,
349 .irq_set_type = mpc512x_irq_set_type,
352 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
353 .gpio_get = mpc8572_gpio_get,
356 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
357 .gpio_dir_out = mpc8xxx_gpio_dir_out,
358 .gpio_get = mpc8xxx_gpio_get,
359 .irq_set_type = mpc8xxx_irq_set_type,
362 static const struct of_device_id mpc8xxx_gpio_ids[] = {
363 { .compatible = "fsl,mpc8349-gpio", },
364 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
365 { .compatible = "fsl,mpc8610-gpio", },
366 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
367 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
368 { .compatible = "fsl,pq3-gpio", },
369 { .compatible = "fsl,qoriq-gpio", },
373 static int mpc8xxx_probe(struct platform_device *pdev)
375 struct device_node *np = pdev->dev.of_node;
376 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
377 struct of_mm_gpio_chip *mm_gc;
378 struct gpio_chip *gc;
379 const struct of_device_id *id;
380 const struct mpc8xxx_gpio_devtype *devtype =
381 of_device_get_match_data(&pdev->dev);
384 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
388 platform_set_drvdata(pdev, mpc8xxx_gc);
390 raw_spin_lock_init(&mpc8xxx_gc->lock);
392 mm_gc = &mpc8xxx_gc->mm_gc;
395 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
396 gc->ngpio = MPC8XXX_GPIO_PINS;
397 gc->direction_input = mpc8xxx_gpio_dir_in;
400 devtype = &mpc8xxx_gpio_devtype_default;
403 * It's assumed that only a single type of gpio controller is available
404 * on the current machine, so overwriting global data is fine.
406 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
408 gc->direction_output = devtype->gpio_dir_out ?: mpc8xxx_gpio_dir_out;
409 gc->get = devtype->gpio_get ?: mpc8xxx_gpio_get;
410 gc->set = mpc8xxx_gpio_set;
411 gc->set_multiple = mpc8xxx_gpio_set_multiple;
412 gc->to_irq = mpc8xxx_gpio_to_irq;
414 ret = of_mm_gpiochip_add_data(np, mm_gc, mpc8xxx_gc);
418 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
419 if (mpc8xxx_gc->irqn == NO_IRQ)
422 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
423 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
424 if (!mpc8xxx_gc->irq)
427 id = of_match_node(mpc8xxx_gpio_ids, np);
429 mpc8xxx_gc->of_dev_id_data = id->data;
431 /* ack and mask all irqs */
432 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
433 out_be32(mm_gc->regs + GPIO_IMR, 0);
435 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
436 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
441 static int mpc8xxx_remove(struct platform_device *pdev)
443 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
445 if (mpc8xxx_gc->irq) {
446 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
447 irq_domain_remove(mpc8xxx_gc->irq);
450 of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
455 static struct platform_driver mpc8xxx_plat_driver = {
456 .probe = mpc8xxx_probe,
457 .remove = mpc8xxx_remove,
459 .name = "gpio-mpc8xxx",
460 .of_match_table = mpc8xxx_gpio_ids,
464 static int __init mpc8xxx_init(void)
466 return platform_driver_register(&mpc8xxx_plat_driver);
469 arch_initcall(mpc8xxx_init);