2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/err.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/irqdomain.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/gpio.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32 #include <linux/basic_mmio_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/module.h>
36 #include <linux/bug.h>
38 enum mxc_gpio_hwtype {
39 IMX1_GPIO, /* runs on i.mx1 */
40 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
41 IMX31_GPIO, /* runs on i.mx31 */
42 IMX35_GPIO, /* runs on all other i.mx */
45 /* device type dependent stuff */
46 struct mxc_gpio_hwdata {
61 struct mxc_gpio_port {
62 struct list_head node;
66 struct irq_domain *domain;
67 struct bgpio_chip bgc;
71 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
79 .edge_sel_reg = -EINVAL,
86 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
94 .edge_sel_reg = -EINVAL,
101 static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
109 .edge_sel_reg = 0x1c,
116 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
117 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
119 #define GPIO_DR (mxc_gpio_hwdata->dr_reg)
120 #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
121 #define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
122 #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
123 #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
124 #define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
125 #define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
126 #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
128 #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
129 #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
130 #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
131 #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
132 #define GPIO_INT_BOTH_EDGES 0x4
134 static const struct platform_device_id mxc_gpio_devtype[] = {
137 .driver_data = IMX1_GPIO,
139 .name = "imx21-gpio",
140 .driver_data = IMX21_GPIO,
142 .name = "imx31-gpio",
143 .driver_data = IMX31_GPIO,
145 .name = "imx35-gpio",
146 .driver_data = IMX35_GPIO,
152 static const struct of_device_id mxc_gpio_dt_ids[] = {
153 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
154 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
155 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
156 { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
161 * MX2 has one interrupt *for all* gpio ports. The list is used
162 * to save the references to all ports, so that mx2_gpio_irq_handler
163 * can walk through all interrupt status registers.
165 static LIST_HEAD(mxc_gpio_ports);
167 /* Note: This driver assumes 32 GPIOs are handled in one register */
169 static int gpio_set_irq_type(struct irq_data *d, u32 type)
171 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
172 struct mxc_gpio_port *port = gc->private;
174 u32 gpio_idx = d->hwirq;
175 u32 gpio = port->bgc.gc.base + gpio_idx;
177 void __iomem *reg = port->base;
179 port->both_edges &= ~(1 << gpio_idx);
181 case IRQ_TYPE_EDGE_RISING:
182 edge = GPIO_INT_RISE_EDGE;
184 case IRQ_TYPE_EDGE_FALLING:
185 edge = GPIO_INT_FALL_EDGE;
187 case IRQ_TYPE_EDGE_BOTH:
188 if (GPIO_EDGE_SEL >= 0) {
189 edge = GPIO_INT_BOTH_EDGES;
191 val = gpio_get_value(gpio);
193 edge = GPIO_INT_LOW_LEV;
194 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
196 edge = GPIO_INT_HIGH_LEV;
197 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
199 port->both_edges |= 1 << gpio_idx;
202 case IRQ_TYPE_LEVEL_LOW:
203 edge = GPIO_INT_LOW_LEV;
205 case IRQ_TYPE_LEVEL_HIGH:
206 edge = GPIO_INT_HIGH_LEV;
212 if (GPIO_EDGE_SEL >= 0) {
213 val = readl(port->base + GPIO_EDGE_SEL);
214 if (edge == GPIO_INT_BOTH_EDGES)
215 writel(val | (1 << gpio_idx),
216 port->base + GPIO_EDGE_SEL);
218 writel(val & ~(1 << gpio_idx),
219 port->base + GPIO_EDGE_SEL);
222 if (edge != GPIO_INT_BOTH_EDGES) {
223 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
224 bit = gpio_idx & 0xf;
225 val = readl(reg) & ~(0x3 << (bit << 1));
226 writel(val | (edge << (bit << 1)), reg);
229 writel(1 << gpio_idx, port->base + GPIO_ISR);
234 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
236 void __iomem *reg = port->base;
240 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
243 edge = (val >> (bit << 1)) & 3;
244 val &= ~(0x3 << (bit << 1));
245 if (edge == GPIO_INT_HIGH_LEV) {
246 edge = GPIO_INT_LOW_LEV;
247 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
248 } else if (edge == GPIO_INT_LOW_LEV) {
249 edge = GPIO_INT_HIGH_LEV;
250 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
252 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
256 writel(val | (edge << (bit << 1)), reg);
259 /* handle 32 interrupts in one status register */
260 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
262 while (irq_stat != 0) {
263 int irqoffset = fls(irq_stat) - 1;
265 if (port->both_edges & (1 << irqoffset))
266 mxc_flip_edge(port, irqoffset);
268 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
270 irq_stat &= ~(1 << irqoffset);
274 /* MX1 and MX3 has one interrupt *per* gpio port */
275 static void mx3_gpio_irq_handler(struct irq_desc *desc)
278 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
279 struct irq_chip *chip = irq_desc_get_chip(desc);
281 chained_irq_enter(chip, desc);
283 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
285 mxc_gpio_irq_handler(port, irq_stat);
287 chained_irq_exit(chip, desc);
290 /* MX2 has one interrupt *for all* gpio ports */
291 static void mx2_gpio_irq_handler(struct irq_desc *desc)
293 u32 irq_msk, irq_stat;
294 struct mxc_gpio_port *port;
295 struct irq_chip *chip = irq_desc_get_chip(desc);
297 chained_irq_enter(chip, desc);
299 /* walk through all interrupt status registers */
300 list_for_each_entry(port, &mxc_gpio_ports, node) {
301 irq_msk = readl(port->base + GPIO_IMR);
305 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
307 mxc_gpio_irq_handler(port, irq_stat);
309 chained_irq_exit(chip, desc);
313 * Set interrupt number "irq" in the GPIO as a wake-up source.
314 * While system is running, all registered GPIO interrupts need to have
315 * wake-up enabled. When system is suspended, only selected GPIO interrupts
316 * need to have wake-up enabled.
317 * @param irq interrupt source number
318 * @param enable enable as wake-up if equal to non-zero
319 * @return This function returns 0 on success.
321 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
323 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
324 struct mxc_gpio_port *port = gc->private;
325 u32 gpio_idx = d->hwirq;
328 if (port->irq_high && (gpio_idx >= 16))
329 enable_irq_wake(port->irq_high);
331 enable_irq_wake(port->irq);
333 if (port->irq_high && (gpio_idx >= 16))
334 disable_irq_wake(port->irq_high);
336 disable_irq_wake(port->irq);
342 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
344 struct irq_chip_generic *gc;
345 struct irq_chip_type *ct;
347 gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
348 port->base, handle_level_irq);
354 ct->chip.irq_ack = irq_gc_ack_set_bit;
355 ct->chip.irq_mask = irq_gc_mask_clr_bit;
356 ct->chip.irq_unmask = irq_gc_mask_set_bit;
357 ct->chip.irq_set_type = gpio_set_irq_type;
358 ct->chip.irq_set_wake = gpio_set_wake_irq;
359 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
360 ct->regs.ack = GPIO_ISR;
361 ct->regs.mask = GPIO_IMR;
363 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
369 static void mxc_gpio_get_hw(struct platform_device *pdev)
371 const struct of_device_id *of_id =
372 of_match_device(mxc_gpio_dt_ids, &pdev->dev);
373 enum mxc_gpio_hwtype hwtype;
376 pdev->id_entry = of_id->data;
377 hwtype = pdev->id_entry->driver_data;
379 if (mxc_gpio_hwtype) {
381 * The driver works with a reasonable presupposition,
382 * that is all gpio ports must be the same type when
383 * running on one soc.
385 BUG_ON(mxc_gpio_hwtype != hwtype);
389 if (hwtype == IMX35_GPIO)
390 mxc_gpio_hwdata = &imx35_gpio_hwdata;
391 else if (hwtype == IMX31_GPIO)
392 mxc_gpio_hwdata = &imx31_gpio_hwdata;
394 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
396 mxc_gpio_hwtype = hwtype;
399 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
401 struct bgpio_chip *bgc = to_bgpio_chip(gc);
402 struct mxc_gpio_port *port =
403 container_of(bgc, struct mxc_gpio_port, bgc);
405 return irq_find_mapping(port->domain, offset);
408 static int mxc_gpio_probe(struct platform_device *pdev)
410 struct device_node *np = pdev->dev.of_node;
411 struct mxc_gpio_port *port;
412 struct resource *iores;
416 mxc_gpio_get_hw(pdev);
418 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
422 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
423 port->base = devm_ioremap_resource(&pdev->dev, iores);
424 if (IS_ERR(port->base))
425 return PTR_ERR(port->base);
427 port->irq_high = platform_get_irq(pdev, 1);
428 port->irq = platform_get_irq(pdev, 0);
432 /* disable the interrupt and clear the status */
433 writel(0, port->base + GPIO_IMR);
434 writel(~0, port->base + GPIO_ISR);
436 if (mxc_gpio_hwtype == IMX21_GPIO) {
438 * Setup one handler for all GPIO interrupts. Actually setting
439 * the handler is needed only once, but doing it for every port
440 * is more robust and easier.
442 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
444 /* setup one handler for each entry */
445 irq_set_chained_handler_and_data(port->irq,
446 mx3_gpio_irq_handler, port);
447 if (port->irq_high > 0)
448 /* setup handler for GPIO 16 to 31 */
449 irq_set_chained_handler_and_data(port->irq_high,
450 mx3_gpio_irq_handler,
454 err = bgpio_init(&port->bgc, &pdev->dev, 4,
455 port->base + GPIO_PSR,
456 port->base + GPIO_DR, NULL,
457 port->base + GPIO_GDIR, NULL,
458 BGPIOF_READ_OUTPUT_REG_SET);
462 port->bgc.gc.to_irq = mxc_gpio_to_irq;
463 port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
466 err = gpiochip_add(&port->bgc.gc);
468 goto out_bgpio_remove;
470 irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
473 goto out_gpiochip_remove;
476 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
477 &irq_domain_simple_ops, NULL);
480 goto out_irqdesc_free;
483 /* gpio-mxc can be a generic irq chip */
484 err = mxc_gpio_init_gc(port, irq_base);
486 goto out_irqdomain_remove;
488 list_add_tail(&port->node, &mxc_gpio_ports);
492 out_irqdomain_remove:
493 irq_domain_remove(port->domain);
495 irq_free_descs(irq_base, 32);
497 gpiochip_remove(&port->bgc.gc);
499 bgpio_remove(&port->bgc);
501 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
505 static struct platform_driver mxc_gpio_driver = {
508 .of_match_table = mxc_gpio_dt_ids,
510 .probe = mxc_gpio_probe,
511 .id_table = mxc_gpio_devtype,
514 static int __init gpio_mxc_init(void)
516 return platform_driver_register(&mxc_gpio_driver);
518 postcore_initcall(gpio_mxc_init);
520 MODULE_AUTHOR("Freescale Semiconductor, "
521 "Daniel Mack <danielncaiaq.de>, "
522 "Juergen Beisert <kernel@pengutronix.de>");
523 MODULE_DESCRIPTION("Freescale MXC GPIO");
524 MODULE_LICENSE("GPL");