2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/slab.h>
27 #include <asm/mach/irq.h>
29 #include <plat/pincfg.h>
30 #include <plat/gpio-nomadik.h>
33 * The GPIO module in the Nomadik family of Systems-on-Chip is an
34 * AMBA device, managing 32 pins and alternate functions. The logic block
35 * is currently used in the Nomadik and ux500.
37 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
40 #define NMK_GPIO_PER_CHIP 32
42 struct nmk_gpio_chip {
43 struct gpio_chip chip;
47 unsigned int parent_irq;
48 int secondary_parent_irq;
49 u32 (*get_secondary_status)(unsigned int bank);
50 void (*set_ioforce)(bool enable);
53 /* Keep track of configured edges */
65 static struct nmk_gpio_chip *
66 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
68 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
70 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
72 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
73 unsigned offset, int gpio_mode)
75 u32 bit = 1 << offset;
78 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
79 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
80 if (gpio_mode & NMK_GPIO_ALT_A)
82 if (gpio_mode & NMK_GPIO_ALT_B)
84 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
85 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
88 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
89 unsigned offset, enum nmk_gpio_slpm mode)
91 u32 bit = 1 << offset;
94 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
95 if (mode == NMK_GPIO_SLPM_NOCHANGE)
99 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
102 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
103 unsigned offset, enum nmk_gpio_pull pull)
105 u32 bit = 1 << offset;
108 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
109 if (pull == NMK_GPIO_PULL_NONE) {
111 nmk_chip->pull_up &= ~bit;
116 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
118 if (pull == NMK_GPIO_PULL_UP) {
119 nmk_chip->pull_up |= bit;
120 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
121 } else if (pull == NMK_GPIO_PULL_DOWN) {
122 nmk_chip->pull_up &= ~bit;
123 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
127 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
128 unsigned offset, bool lowemi)
130 u32 bit = BIT(offset);
131 bool enabled = nmk_chip->lowemi & bit;
133 if (lowemi == enabled)
137 nmk_chip->lowemi |= bit;
139 nmk_chip->lowemi &= ~bit;
141 writel_relaxed(nmk_chip->lowemi,
142 nmk_chip->addr + NMK_GPIO_LOWEMI);
145 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
148 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
151 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
152 unsigned offset, int val)
155 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
157 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
160 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
161 unsigned offset, int val)
163 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
164 __nmk_gpio_set_output(nmk_chip, offset, val);
167 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
168 unsigned offset, int gpio_mode,
171 u32 rwimsc = nmk_chip->rwimsc;
172 u32 fwimsc = nmk_chip->fwimsc;
174 if (glitch && nmk_chip->set_ioforce) {
175 u32 bit = BIT(offset);
177 /* Prevent spurious wakeups */
178 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
179 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
181 nmk_chip->set_ioforce(true);
184 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
186 if (glitch && nmk_chip->set_ioforce) {
187 nmk_chip->set_ioforce(false);
189 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
190 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
195 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
197 u32 falling = nmk_chip->fimsc & BIT(offset);
198 u32 rising = nmk_chip->rimsc & BIT(offset);
199 int gpio = nmk_chip->chip.base + offset;
200 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
201 struct irq_data *d = irq_get_irq_data(irq);
203 if (!rising && !falling)
206 if (!d || !irqd_irq_disabled(d))
210 nmk_chip->rimsc &= ~BIT(offset);
211 writel_relaxed(nmk_chip->rimsc,
212 nmk_chip->addr + NMK_GPIO_RIMSC);
216 nmk_chip->fimsc &= ~BIT(offset);
217 writel_relaxed(nmk_chip->fimsc,
218 nmk_chip->addr + NMK_GPIO_FIMSC);
221 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
224 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
225 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
227 static const char *afnames[] = {
228 [NMK_GPIO_ALT_GPIO] = "GPIO",
229 [NMK_GPIO_ALT_A] = "A",
230 [NMK_GPIO_ALT_B] = "B",
231 [NMK_GPIO_ALT_C] = "C"
233 static const char *pullnames[] = {
234 [NMK_GPIO_PULL_NONE] = "none",
235 [NMK_GPIO_PULL_UP] = "up",
236 [NMK_GPIO_PULL_DOWN] = "down",
237 [3] /* illegal */ = "??"
239 static const char *slpmnames[] = {
240 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
241 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
244 int pin = PIN_NUM(cfg);
245 int pull = PIN_PULL(cfg);
246 int af = PIN_ALT(cfg);
247 int slpm = PIN_SLPM(cfg);
248 int output = PIN_DIR(cfg);
249 int val = PIN_VAL(cfg);
250 bool glitch = af == NMK_GPIO_ALT_C;
252 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
253 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
254 output ? "output " : "input",
255 output ? (val ? "high" : "low") : "");
258 int slpm_pull = PIN_SLPM_PULL(cfg);
259 int slpm_output = PIN_SLPM_DIR(cfg);
260 int slpm_val = PIN_SLPM_VAL(cfg);
262 af = NMK_GPIO_ALT_GPIO;
265 * The SLPM_* values are normal values + 1 to allow zero to
266 * mean "same as normal".
269 pull = slpm_pull - 1;
271 output = slpm_output - 1;
275 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
277 slpm_pull ? pullnames[pull] : "same",
278 slpm_output ? (output ? "output" : "input") : "same",
279 slpm_val ? (val ? "high" : "low") : "same");
283 __nmk_gpio_make_output(nmk_chip, offset, val);
285 __nmk_gpio_make_input(nmk_chip, offset);
286 __nmk_gpio_set_pull(nmk_chip, offset, pull);
289 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
292 * If the pin is switching to altfunc, and there was an interrupt
293 * installed on it which has been lazy disabled, actually mask the
294 * interrupt to prevent spurious interrupts that would occur while the
295 * pin is under control of the peripheral. Only SKE does this.
297 if (af != NMK_GPIO_ALT_GPIO)
298 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
301 * If we've backed up the SLPM registers (glitch workaround), modify
302 * the backups since they will be restored.
305 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
306 slpmregs[nmk_chip->bank] |= BIT(offset);
308 slpmregs[nmk_chip->bank] &= ~BIT(offset);
310 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
312 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
316 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
317 * - Save SLPM registers
318 * - Set SLPM=0 for the IOs you want to switch and others to 1
319 * - Configure the GPIO registers for the IOs that are being switched
321 * - Modify the AFLSA/B registers for the IOs that are being switched
323 * - Restore SLPM registers
324 * - Any spurious wake up event during switch sequence to be ignored and
327 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
331 for (i = 0; i < NUM_BANKS; i++) {
332 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
333 unsigned int temp = slpm[i];
338 clk_enable(chip->clk);
340 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
341 writel(temp, chip->addr + NMK_GPIO_SLPC);
345 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
349 for (i = 0; i < NUM_BANKS; i++) {
350 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
355 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
357 clk_disable(chip->clk);
361 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
363 static unsigned int slpm[NUM_BANKS];
369 for (i = 0; i < num; i++) {
370 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
376 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
379 memset(slpm, 0xff, sizeof(slpm));
381 for (i = 0; i < num; i++) {
382 int pin = PIN_NUM(cfgs[i]);
383 int offset = pin % NMK_GPIO_PER_CHIP;
385 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
386 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
389 nmk_gpio_glitch_slpm_init(slpm);
392 for (i = 0; i < num; i++) {
393 struct nmk_gpio_chip *nmk_chip;
394 int pin = PIN_NUM(cfgs[i]);
396 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
402 clk_enable(nmk_chip->clk);
403 spin_lock(&nmk_chip->lock);
404 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
405 cfgs[i], sleep, glitch ? slpm : NULL);
406 spin_unlock(&nmk_chip->lock);
407 clk_disable(nmk_chip->clk);
411 nmk_gpio_glitch_slpm_restore(slpm);
413 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
419 * nmk_config_pin - configure a pin's mux attributes
420 * @cfg: pin confguration
422 * Configures a pin's mode (alternate function or GPIO), its pull up status,
423 * and its sleep mode based on the specified configuration. The @cfg is
424 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
425 * are constructed using, and can be further enhanced with, the macros in
428 * If a pin's mode is set to GPIO, it is configured as an input to avoid
429 * side-effects. The gpio can be manipulated later using standard GPIO API
432 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
434 return __nmk_config_pins(&cfg, 1, sleep);
436 EXPORT_SYMBOL(nmk_config_pin);
439 * nmk_config_pins - configure several pins at once
440 * @cfgs: array of pin configurations
441 * @num: number of elments in the array
443 * Configures several pins using nmk_config_pin(). Refer to that function for
444 * further information.
446 int nmk_config_pins(pin_cfg_t *cfgs, int num)
448 return __nmk_config_pins(cfgs, num, false);
450 EXPORT_SYMBOL(nmk_config_pins);
452 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
454 return __nmk_config_pins(cfgs, num, true);
456 EXPORT_SYMBOL(nmk_config_pins_sleep);
459 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
461 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
463 * This register is actually in the pinmux layer, not the GPIO block itself.
464 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
465 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
466 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
467 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
468 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
469 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
471 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
472 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
473 * entered) regardless of the altfunction selected. Also wake-up detection is
476 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
477 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
478 * (for altfunction GPIO) or respective on-chip peripherals (for other
479 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
481 * Note that enable_irq_wake() will automatically enable wakeup detection.
483 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
485 struct nmk_gpio_chip *nmk_chip;
488 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
492 clk_enable(nmk_chip->clk);
493 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
494 spin_lock(&nmk_chip->lock);
496 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
498 spin_unlock(&nmk_chip->lock);
499 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
500 clk_disable(nmk_chip->clk);
506 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
508 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
510 * Enables/disables pull up/down on a specified pin. This only takes effect if
511 * the pin is configured as an input (either explicitly or by the alternate
514 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
515 * configured as an input. Otherwise, due to the way the controller registers
516 * work, this function will change the value output on the pin.
518 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
520 struct nmk_gpio_chip *nmk_chip;
523 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
527 clk_enable(nmk_chip->clk);
528 spin_lock_irqsave(&nmk_chip->lock, flags);
529 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
530 spin_unlock_irqrestore(&nmk_chip->lock, flags);
531 clk_disable(nmk_chip->clk);
538 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
540 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
541 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
543 * Sets the mode of the specified pin to one of the alternate functions or
546 int nmk_gpio_set_mode(int gpio, int gpio_mode)
548 struct nmk_gpio_chip *nmk_chip;
551 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
555 clk_enable(nmk_chip->clk);
556 spin_lock_irqsave(&nmk_chip->lock, flags);
557 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
558 spin_unlock_irqrestore(&nmk_chip->lock, flags);
559 clk_disable(nmk_chip->clk);
563 EXPORT_SYMBOL(nmk_gpio_set_mode);
565 int nmk_gpio_get_mode(int gpio)
567 struct nmk_gpio_chip *nmk_chip;
568 u32 afunc, bfunc, bit;
570 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
574 bit = 1 << (gpio - nmk_chip->chip.base);
576 clk_enable(nmk_chip->clk);
578 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
579 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
581 clk_disable(nmk_chip->clk);
583 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
585 EXPORT_SYMBOL(nmk_gpio_get_mode);
589 static inline int nmk_gpio_get_bitmask(int gpio)
591 return 1 << (gpio % 32);
594 static void nmk_gpio_irq_ack(struct irq_data *d)
597 struct nmk_gpio_chip *nmk_chip;
599 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
600 nmk_chip = irq_data_get_irq_chip_data(d);
604 clk_enable(nmk_chip->clk);
605 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
606 clk_disable(nmk_chip->clk);
609 enum nmk_gpio_irq_type {
614 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
615 int gpio, enum nmk_gpio_irq_type which,
618 u32 bitmask = nmk_gpio_get_bitmask(gpio);
624 if (which == NORMAL) {
625 rimscreg = NMK_GPIO_RIMSC;
626 fimscreg = NMK_GPIO_FIMSC;
627 rimscval = &nmk_chip->rimsc;
628 fimscval = &nmk_chip->fimsc;
630 rimscreg = NMK_GPIO_RWIMSC;
631 fimscreg = NMK_GPIO_FWIMSC;
632 rimscval = &nmk_chip->rwimsc;
633 fimscval = &nmk_chip->fwimsc;
636 /* we must individually set/clear the two edges */
637 if (nmk_chip->edge_rising & bitmask) {
639 *rimscval |= bitmask;
641 *rimscval &= ~bitmask;
642 writel(*rimscval, nmk_chip->addr + rimscreg);
644 if (nmk_chip->edge_falling & bitmask) {
646 *fimscval |= bitmask;
648 *fimscval &= ~bitmask;
649 writel(*fimscval, nmk_chip->addr + fimscreg);
653 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
657 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
658 * disabled, since setting SLPM to 1 increases power consumption, and
659 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
661 if (nmk_chip->sleepmode && on) {
662 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
663 NMK_GPIO_SLPM_WAKEUP_ENABLE);
666 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
669 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
672 struct nmk_gpio_chip *nmk_chip;
676 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
677 nmk_chip = irq_data_get_irq_chip_data(d);
678 bitmask = nmk_gpio_get_bitmask(gpio);
682 clk_enable(nmk_chip->clk);
683 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
684 spin_lock(&nmk_chip->lock);
686 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
688 if (!(nmk_chip->real_wake & bitmask))
689 __nmk_gpio_set_wake(nmk_chip, gpio, enable);
691 spin_unlock(&nmk_chip->lock);
692 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
693 clk_disable(nmk_chip->clk);
698 static void nmk_gpio_irq_mask(struct irq_data *d)
700 nmk_gpio_irq_maskunmask(d, false);
703 static void nmk_gpio_irq_unmask(struct irq_data *d)
705 nmk_gpio_irq_maskunmask(d, true);
708 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
710 struct nmk_gpio_chip *nmk_chip;
715 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
716 nmk_chip = irq_data_get_irq_chip_data(d);
719 bitmask = nmk_gpio_get_bitmask(gpio);
721 clk_enable(nmk_chip->clk);
722 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
723 spin_lock(&nmk_chip->lock);
725 if (irqd_irq_disabled(d))
726 __nmk_gpio_set_wake(nmk_chip, gpio, on);
729 nmk_chip->real_wake |= bitmask;
731 nmk_chip->real_wake &= ~bitmask;
733 spin_unlock(&nmk_chip->lock);
734 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
735 clk_disable(nmk_chip->clk);
740 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
742 bool enabled = !irqd_irq_disabled(d);
743 bool wake = irqd_is_wakeup_set(d);
745 struct nmk_gpio_chip *nmk_chip;
749 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
750 nmk_chip = irq_data_get_irq_chip_data(d);
751 bitmask = nmk_gpio_get_bitmask(gpio);
755 if (type & IRQ_TYPE_LEVEL_HIGH)
757 if (type & IRQ_TYPE_LEVEL_LOW)
760 clk_enable(nmk_chip->clk);
761 spin_lock_irqsave(&nmk_chip->lock, flags);
764 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
767 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
769 nmk_chip->edge_rising &= ~bitmask;
770 if (type & IRQ_TYPE_EDGE_RISING)
771 nmk_chip->edge_rising |= bitmask;
773 nmk_chip->edge_falling &= ~bitmask;
774 if (type & IRQ_TYPE_EDGE_FALLING)
775 nmk_chip->edge_falling |= bitmask;
778 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
781 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
783 spin_unlock_irqrestore(&nmk_chip->lock, flags);
784 clk_disable(nmk_chip->clk);
789 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
791 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
793 clk_enable(nmk_chip->clk);
794 nmk_gpio_irq_unmask(d);
798 static void nmk_gpio_irq_shutdown(struct irq_data *d)
800 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
802 nmk_gpio_irq_mask(d);
803 clk_disable(nmk_chip->clk);
806 static struct irq_chip nmk_gpio_irq_chip = {
807 .name = "Nomadik-GPIO",
808 .irq_ack = nmk_gpio_irq_ack,
809 .irq_mask = nmk_gpio_irq_mask,
810 .irq_unmask = nmk_gpio_irq_unmask,
811 .irq_set_type = nmk_gpio_irq_set_type,
812 .irq_set_wake = nmk_gpio_irq_set_wake,
813 .irq_startup = nmk_gpio_irq_startup,
814 .irq_shutdown = nmk_gpio_irq_shutdown,
817 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
820 struct nmk_gpio_chip *nmk_chip;
821 struct irq_chip *host_chip = irq_get_chip(irq);
822 unsigned int first_irq;
824 chained_irq_enter(host_chip, desc);
826 nmk_chip = irq_get_handler_data(irq);
827 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
829 int bit = __ffs(status);
831 generic_handle_irq(first_irq + bit);
835 chained_irq_exit(host_chip, desc);
838 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
840 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
843 clk_enable(nmk_chip->clk);
844 status = readl(nmk_chip->addr + NMK_GPIO_IS);
845 clk_disable(nmk_chip->clk);
847 __nmk_gpio_irq_handler(irq, desc, status);
850 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
851 struct irq_desc *desc)
853 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
854 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
856 __nmk_gpio_irq_handler(irq, desc, status);
859 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
861 unsigned int first_irq;
864 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
865 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
866 irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
868 set_irq_flags(i, IRQF_VALID);
869 irq_set_chip_data(i, nmk_chip);
870 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
873 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
874 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
876 if (nmk_chip->secondary_parent_irq >= 0) {
877 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
878 nmk_gpio_secondary_irq_handler);
879 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
886 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
888 struct nmk_gpio_chip *nmk_chip =
889 container_of(chip, struct nmk_gpio_chip, chip);
891 clk_enable(nmk_chip->clk);
893 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
895 clk_disable(nmk_chip->clk);
900 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
902 struct nmk_gpio_chip *nmk_chip =
903 container_of(chip, struct nmk_gpio_chip, chip);
904 u32 bit = 1 << offset;
907 clk_enable(nmk_chip->clk);
909 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
911 clk_disable(nmk_chip->clk);
916 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
919 struct nmk_gpio_chip *nmk_chip =
920 container_of(chip, struct nmk_gpio_chip, chip);
922 clk_enable(nmk_chip->clk);
924 __nmk_gpio_set_output(nmk_chip, offset, val);
926 clk_disable(nmk_chip->clk);
929 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
932 struct nmk_gpio_chip *nmk_chip =
933 container_of(chip, struct nmk_gpio_chip, chip);
935 clk_enable(nmk_chip->clk);
937 __nmk_gpio_make_output(nmk_chip, offset, val);
939 clk_disable(nmk_chip->clk);
944 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
946 struct nmk_gpio_chip *nmk_chip =
947 container_of(chip, struct nmk_gpio_chip, chip);
949 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
952 #ifdef CONFIG_DEBUG_FS
954 #include <linux/seq_file.h>
956 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
960 unsigned gpio = chip->base;
962 struct nmk_gpio_chip *nmk_chip =
963 container_of(chip, struct nmk_gpio_chip, chip);
964 const char *modes[] = {
965 [NMK_GPIO_ALT_GPIO] = "gpio",
966 [NMK_GPIO_ALT_A] = "altA",
967 [NMK_GPIO_ALT_B] = "altB",
968 [NMK_GPIO_ALT_C] = "altC",
971 clk_enable(nmk_chip->clk);
973 for (i = 0; i < chip->ngpio; i++, gpio++) {
974 const char *label = gpiochip_is_requested(chip, i);
978 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
979 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
980 mode = nmk_gpio_get_mode(gpio);
981 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
982 gpio, label ?: "(none)",
983 is_out ? "out" : "in ",
985 ? (chip->get(chip, i) ? "hi" : "lo")
987 (mode < 0) ? "unknown" : modes[mode],
988 pull ? "pull" : "none");
990 if (label && !is_out) {
991 int irq = gpio_to_irq(gpio);
992 struct irq_desc *desc = irq_to_desc(irq);
994 /* This races with request_irq(), set_irq_type(),
995 * and set_irq_wake() ... but those are "rare".
997 if (irq >= 0 && desc->action) {
999 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1001 if (nmk_chip->edge_rising & bitmask)
1002 trigger = "edge-rising";
1003 else if (nmk_chip->edge_falling & bitmask)
1004 trigger = "edge-falling";
1006 trigger = "edge-undefined";
1008 seq_printf(s, " irq-%d %s%s",
1010 irqd_is_wakeup_set(&desc->irq_data)
1015 seq_printf(s, "\n");
1018 clk_disable(nmk_chip->clk);
1022 #define nmk_gpio_dbg_show NULL
1025 /* This structure is replicated for each GPIO block allocated at probe time */
1026 static struct gpio_chip nmk_gpio_template = {
1027 .direction_input = nmk_gpio_make_input,
1028 .get = nmk_gpio_get_input,
1029 .direction_output = nmk_gpio_make_output,
1030 .set = nmk_gpio_set_output,
1031 .to_irq = nmk_gpio_to_irq,
1032 .dbg_show = nmk_gpio_dbg_show,
1036 void nmk_gpio_clocks_enable(void)
1040 for (i = 0; i < NUM_BANKS; i++) {
1041 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1046 clk_enable(chip->clk);
1050 void nmk_gpio_clocks_disable(void)
1054 for (i = 0; i < NUM_BANKS; i++) {
1055 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1060 clk_disable(chip->clk);
1065 * Called from the suspend/resume path to only keep the real wakeup interrupts
1066 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1067 * and not the rest of the interrupts which we needed to have as wakeups for
1070 * PM ops are not used since this needs to be done at the end, after all the
1071 * other drivers are done with their suspend callbacks.
1073 void nmk_gpio_wakeups_suspend(void)
1077 for (i = 0; i < NUM_BANKS; i++) {
1078 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1083 clk_enable(chip->clk);
1085 writel(chip->rwimsc & chip->real_wake,
1086 chip->addr + NMK_GPIO_RWIMSC);
1087 writel(chip->fwimsc & chip->real_wake,
1088 chip->addr + NMK_GPIO_FWIMSC);
1090 clk_disable(chip->clk);
1094 void nmk_gpio_wakeups_resume(void)
1098 for (i = 0; i < NUM_BANKS; i++) {
1099 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1104 clk_enable(chip->clk);
1106 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1107 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1109 clk_disable(chip->clk);
1114 * Read the pull up/pull down status.
1115 * A bit set in 'pull_up' means that pull up
1116 * is selected if pull is enabled in PDIS register.
1117 * Note: only pull up/down set via this driver can
1118 * be detected due to HW limitations.
1120 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1122 if (gpio_bank < NUM_BANKS) {
1123 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1128 *pull_up = chip->pull_up;
1132 static int __devinit nmk_gpio_probe(struct platform_device *dev)
1134 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1135 struct device_node *np = dev->dev.of_node;
1136 struct nmk_gpio_chip *nmk_chip;
1137 struct gpio_chip *chip;
1138 struct resource *res;
1145 if (!pdata && !np) {
1146 dev_err(&dev->dev, "No platform data or device tree found\n");
1151 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
1155 if (of_get_property(np, "supports-sleepmode", NULL))
1156 pdata->supports_sleepmode = true;
1158 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1159 dev_err(&dev->dev, "gpio-bank property not found\n");
1164 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1165 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1168 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1174 irq = platform_get_irq(dev, 0);
1180 secondary_irq = platform_get_irq(dev, 1);
1181 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1186 if (request_mem_region(res->start, resource_size(res),
1187 dev_name(&dev->dev)) == NULL) {
1192 base = ioremap(res->start, resource_size(res));
1198 clk = clk_get(&dev->dev, NULL);
1204 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
1211 * The virt address in nmk_chip->addr is in the nomadik register space,
1212 * so we can simply convert the resource address, without remapping
1214 nmk_chip->bank = dev->id;
1215 nmk_chip->clk = clk;
1216 nmk_chip->addr = base;
1217 nmk_chip->chip = nmk_gpio_template;
1218 nmk_chip->parent_irq = irq;
1219 nmk_chip->secondary_parent_irq = secondary_irq;
1220 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1221 nmk_chip->set_ioforce = pdata->set_ioforce;
1222 nmk_chip->sleepmode = pdata->supports_sleepmode;
1223 spin_lock_init(&nmk_chip->lock);
1225 chip = &nmk_chip->chip;
1226 chip->base = pdata->first_gpio;
1227 chip->ngpio = pdata->num_gpio;
1228 chip->label = pdata->name ?: dev_name(&dev->dev);
1229 chip->dev = &dev->dev;
1230 chip->owner = THIS_MODULE;
1232 clk_enable(nmk_chip->clk);
1233 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1234 clk_disable(nmk_chip->clk);
1238 ret = gpiochip_add(&nmk_chip->chip);
1242 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1244 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1246 platform_set_drvdata(dev, nmk_chip);
1248 nmk_gpio_init_irq(nmk_chip);
1250 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1262 release_mem_region(res->start, resource_size(res));
1264 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1265 pdata->first_gpio, pdata->first_gpio+31);
1273 static const struct of_device_id nmk_gpio_match[] = {
1274 { .compatible = "st,nomadik-gpio", },
1278 static struct platform_driver nmk_gpio_driver = {
1280 .owner = THIS_MODULE,
1282 .of_match_table = nmk_gpio_match,
1284 .probe = nmk_gpio_probe,
1287 static int __init nmk_gpio_init(void)
1289 return platform_driver_register(&nmk_gpio_driver);
1292 core_initcall(nmk_gpio_init);
1294 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1295 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1296 MODULE_LICENSE("GPL");