2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
35 u16 virtual_irq_start;
37 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
42 u32 enabled_non_wakeup_gpios;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
50 struct gpio_chip chip;
60 #ifdef CONFIG_ARCH_OMAP3
61 struct omap3_gpio_regs {
74 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
78 * TODO: Cleanup gpio_bank usage as it is having information
79 * related to all instances of the device
81 static struct gpio_bank *gpio_bank;
83 /* TODO: Analyze removing gpio_bank_count usage from driver code */
86 static inline struct gpio_bank *get_gpio_bank(int gpio)
88 if (cpu_is_omap15xx()) {
89 if (OMAP_GPIO_IS_MPUIO(gpio))
93 if (cpu_is_omap16xx()) {
94 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[1 + (gpio >> 4)];
98 if (cpu_is_omap7xx()) {
99 if (OMAP_GPIO_IS_MPUIO(gpio))
100 return &gpio_bank[0];
101 return &gpio_bank[1 + (gpio >> 5)];
103 if (cpu_is_omap24xx())
104 return &gpio_bank[gpio >> 5];
105 if (cpu_is_omap34xx() || cpu_is_omap44xx())
106 return &gpio_bank[gpio >> 5];
111 static inline int get_gpio_index(int gpio)
113 if (cpu_is_omap7xx())
115 if (cpu_is_omap24xx())
117 if (cpu_is_omap34xx() || cpu_is_omap44xx())
122 static inline int gpio_valid(int gpio)
126 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
127 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
131 if (cpu_is_omap15xx() && gpio < 16)
133 if ((cpu_is_omap16xx()) && gpio < 64)
135 if (cpu_is_omap7xx() && gpio < 192)
137 if (cpu_is_omap2420() && gpio < 128)
139 if (cpu_is_omap2430() && gpio < 160)
141 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
146 static int check_gpio(int gpio)
148 if (unlikely(gpio_valid(gpio) < 0)) {
149 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
156 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158 void __iomem *reg = bank->base;
161 switch (bank->method) {
162 #ifdef CONFIG_ARCH_OMAP1
164 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
167 #ifdef CONFIG_ARCH_OMAP15XX
168 case METHOD_GPIO_1510:
169 reg += OMAP1510_GPIO_DIR_CONTROL;
172 #ifdef CONFIG_ARCH_OMAP16XX
173 case METHOD_GPIO_1610:
174 reg += OMAP1610_GPIO_DIRECTION;
177 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
178 case METHOD_GPIO_7XX:
179 reg += OMAP7XX_GPIO_DIR_CONTROL;
182 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
183 case METHOD_GPIO_24XX:
184 reg += OMAP24XX_GPIO_OE;
187 #if defined(CONFIG_ARCH_OMAP4)
188 case METHOD_GPIO_44XX:
189 reg += OMAP4_GPIO_OE;
196 l = __raw_readl(reg);
201 __raw_writel(l, reg);
204 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
206 void __iomem *reg = bank->base;
209 switch (bank->method) {
210 #ifdef CONFIG_ARCH_OMAP1
212 reg += OMAP_MPUIO_OUTPUT / bank->stride;
213 l = __raw_readl(reg);
220 #ifdef CONFIG_ARCH_OMAP15XX
221 case METHOD_GPIO_1510:
222 reg += OMAP1510_GPIO_DATA_OUTPUT;
223 l = __raw_readl(reg);
230 #ifdef CONFIG_ARCH_OMAP16XX
231 case METHOD_GPIO_1610:
233 reg += OMAP1610_GPIO_SET_DATAOUT;
235 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
239 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
240 case METHOD_GPIO_7XX:
241 reg += OMAP7XX_GPIO_DATA_OUTPUT;
242 l = __raw_readl(reg);
249 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
250 case METHOD_GPIO_24XX:
252 reg += OMAP24XX_GPIO_SETDATAOUT;
254 reg += OMAP24XX_GPIO_CLEARDATAOUT;
258 #ifdef CONFIG_ARCH_OMAP4
259 case METHOD_GPIO_44XX:
261 reg += OMAP4_GPIO_SETDATAOUT;
263 reg += OMAP4_GPIO_CLEARDATAOUT;
271 __raw_writel(l, reg);
274 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
278 if (check_gpio(gpio) < 0)
281 switch (bank->method) {
282 #ifdef CONFIG_ARCH_OMAP1
284 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
287 #ifdef CONFIG_ARCH_OMAP15XX
288 case METHOD_GPIO_1510:
289 reg += OMAP1510_GPIO_DATA_INPUT;
292 #ifdef CONFIG_ARCH_OMAP16XX
293 case METHOD_GPIO_1610:
294 reg += OMAP1610_GPIO_DATAIN;
297 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
298 case METHOD_GPIO_7XX:
299 reg += OMAP7XX_GPIO_DATA_INPUT;
302 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
303 case METHOD_GPIO_24XX:
304 reg += OMAP24XX_GPIO_DATAIN;
307 #ifdef CONFIG_ARCH_OMAP4
308 case METHOD_GPIO_44XX:
309 reg += OMAP4_GPIO_DATAIN;
315 return (__raw_readl(reg)
316 & (1 << get_gpio_index(gpio))) != 0;
319 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
323 if (check_gpio(gpio) < 0)
327 switch (bank->method) {
328 #ifdef CONFIG_ARCH_OMAP1
330 reg += OMAP_MPUIO_OUTPUT / bank->stride;
333 #ifdef CONFIG_ARCH_OMAP15XX
334 case METHOD_GPIO_1510:
335 reg += OMAP1510_GPIO_DATA_OUTPUT;
338 #ifdef CONFIG_ARCH_OMAP16XX
339 case METHOD_GPIO_1610:
340 reg += OMAP1610_GPIO_DATAOUT;
343 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
344 case METHOD_GPIO_7XX:
345 reg += OMAP7XX_GPIO_DATA_OUTPUT;
348 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
349 case METHOD_GPIO_24XX:
350 reg += OMAP24XX_GPIO_DATAOUT;
353 #ifdef CONFIG_ARCH_OMAP4
354 case METHOD_GPIO_44XX:
355 reg += OMAP4_GPIO_DATAOUT;
362 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
365 #define MOD_REG_BIT(reg, bit_mask, set) \
367 int l = __raw_readl(base + reg); \
368 if (set) l |= bit_mask; \
369 else l &= ~bit_mask; \
370 __raw_writel(l, base + reg); \
374 * _set_gpio_debounce - low level gpio debounce time
375 * @bank: the gpio bank we're acting upon
376 * @gpio: the gpio number on this @gpio
377 * @debounce: debounce time to use
379 * OMAP's debounce time is in 31us steps so we need
380 * to convert and round up to the closest unit.
382 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
385 void __iomem *reg = bank->base;
389 if (!bank->dbck_flag)
394 else if (debounce > 7936)
397 debounce = (debounce / 0x1f) - 1;
399 l = 1 << get_gpio_index(gpio);
401 if (bank->method == METHOD_GPIO_44XX)
402 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406 __raw_writel(debounce, reg);
409 if (bank->method == METHOD_GPIO_44XX)
410 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414 val = __raw_readl(reg);
418 clk_enable(bank->dbck);
421 clk_disable(bank->dbck);
423 bank->dbck_enable_mask = val;
425 __raw_writel(val, reg);
428 #ifdef CONFIG_ARCH_OMAP2PLUS
429 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
432 void __iomem *base = bank->base;
433 u32 gpio_bit = 1 << gpio;
435 if (cpu_is_omap44xx()) {
436 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
437 trigger & IRQ_TYPE_LEVEL_LOW);
438 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
439 trigger & IRQ_TYPE_LEVEL_HIGH);
440 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
441 trigger & IRQ_TYPE_EDGE_RISING);
442 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
443 trigger & IRQ_TYPE_EDGE_FALLING);
445 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
446 trigger & IRQ_TYPE_LEVEL_LOW);
447 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
448 trigger & IRQ_TYPE_LEVEL_HIGH);
449 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
450 trigger & IRQ_TYPE_EDGE_RISING);
451 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
452 trigger & IRQ_TYPE_EDGE_FALLING);
454 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
455 if (cpu_is_omap44xx()) {
456 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
460 * GPIO wakeup request can only be generated on edge
463 if (trigger & IRQ_TYPE_EDGE_BOTH)
464 __raw_writel(1 << gpio, bank->base
465 + OMAP24XX_GPIO_SETWKUENA);
467 __raw_writel(1 << gpio, bank->base
468 + OMAP24XX_GPIO_CLEARWKUENA);
471 /* This part needs to be executed always for OMAP34xx */
472 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
474 * Log the edge gpio and manually trigger the IRQ
475 * after resume if the input level changes
476 * to avoid irq lost during PER RET/OFF mode
477 * Applies for omap2 non-wakeup gpio and all omap3 gpios
479 if (trigger & IRQ_TYPE_EDGE_BOTH)
480 bank->enabled_non_wakeup_gpios |= gpio_bit;
482 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
485 if (cpu_is_omap44xx()) {
487 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
488 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
491 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
492 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
497 #ifdef CONFIG_ARCH_OMAP1
499 * This only applies to chips that can't do both rising and falling edge
500 * detection at once. For all other chips, this function is a noop.
502 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
504 void __iomem *reg = bank->base;
507 switch (bank->method) {
509 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
511 #ifdef CONFIG_ARCH_OMAP15XX
512 case METHOD_GPIO_1510:
513 reg += OMAP1510_GPIO_INT_CONTROL;
516 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
517 case METHOD_GPIO_7XX:
518 reg += OMAP7XX_GPIO_INT_CONTROL;
525 l = __raw_readl(reg);
531 __raw_writel(l, reg);
535 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
537 void __iomem *reg = bank->base;
540 switch (bank->method) {
541 #ifdef CONFIG_ARCH_OMAP1
543 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
544 l = __raw_readl(reg);
545 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
546 bank->toggle_mask |= 1 << gpio;
547 if (trigger & IRQ_TYPE_EDGE_RISING)
549 else if (trigger & IRQ_TYPE_EDGE_FALLING)
555 #ifdef CONFIG_ARCH_OMAP15XX
556 case METHOD_GPIO_1510:
557 reg += OMAP1510_GPIO_INT_CONTROL;
558 l = __raw_readl(reg);
559 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
560 bank->toggle_mask |= 1 << gpio;
561 if (trigger & IRQ_TYPE_EDGE_RISING)
563 else if (trigger & IRQ_TYPE_EDGE_FALLING)
569 #ifdef CONFIG_ARCH_OMAP16XX
570 case METHOD_GPIO_1610:
572 reg += OMAP1610_GPIO_EDGE_CTRL2;
574 reg += OMAP1610_GPIO_EDGE_CTRL1;
576 l = __raw_readl(reg);
577 l &= ~(3 << (gpio << 1));
578 if (trigger & IRQ_TYPE_EDGE_RISING)
579 l |= 2 << (gpio << 1);
580 if (trigger & IRQ_TYPE_EDGE_FALLING)
581 l |= 1 << (gpio << 1);
583 /* Enable wake-up during idle for dynamic tick */
584 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
586 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
589 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
590 case METHOD_GPIO_7XX:
591 reg += OMAP7XX_GPIO_INT_CONTROL;
592 l = __raw_readl(reg);
593 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
594 bank->toggle_mask |= 1 << gpio;
595 if (trigger & IRQ_TYPE_EDGE_RISING)
597 else if (trigger & IRQ_TYPE_EDGE_FALLING)
603 #ifdef CONFIG_ARCH_OMAP2PLUS
604 case METHOD_GPIO_24XX:
605 case METHOD_GPIO_44XX:
606 set_24xx_gpio_triggering(bank, gpio, trigger);
612 __raw_writel(l, reg);
618 static int gpio_irq_type(struct irq_data *d, unsigned type)
620 struct gpio_bank *bank;
625 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
626 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
628 gpio = d->irq - IH_GPIO_BASE;
630 if (check_gpio(gpio) < 0)
633 if (type & ~IRQ_TYPE_SENSE_MASK)
636 /* OMAP1 allows only only edge triggering */
637 if (!cpu_class_is_omap2()
638 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
641 bank = irq_data_get_irq_chip_data(d);
642 spin_lock_irqsave(&bank->lock, flags);
643 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
644 spin_unlock_irqrestore(&bank->lock, flags);
646 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
647 __irq_set_handler_locked(d->irq, handle_level_irq);
648 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
649 __irq_set_handler_locked(d->irq, handle_edge_irq);
654 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
656 void __iomem *reg = bank->base;
658 switch (bank->method) {
659 #ifdef CONFIG_ARCH_OMAP15XX
660 case METHOD_GPIO_1510:
661 reg += OMAP1510_GPIO_INT_STATUS;
664 #ifdef CONFIG_ARCH_OMAP16XX
665 case METHOD_GPIO_1610:
666 reg += OMAP1610_GPIO_IRQSTATUS1;
669 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
670 case METHOD_GPIO_7XX:
671 reg += OMAP7XX_GPIO_INT_STATUS;
674 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
675 case METHOD_GPIO_24XX:
676 reg += OMAP24XX_GPIO_IRQSTATUS1;
679 #if defined(CONFIG_ARCH_OMAP4)
680 case METHOD_GPIO_44XX:
681 reg += OMAP4_GPIO_IRQSTATUS0;
688 __raw_writel(gpio_mask, reg);
690 /* Workaround for clearing DSP GPIO interrupts to allow retention */
691 if (cpu_is_omap24xx() || cpu_is_omap34xx())
692 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
693 else if (cpu_is_omap44xx())
694 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
696 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx())
697 __raw_writel(gpio_mask, reg);
699 /* Flush posted write for the irq status to avoid spurious interrupts */
703 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
705 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
708 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
710 void __iomem *reg = bank->base;
713 u32 mask = (1 << bank->width) - 1;
715 switch (bank->method) {
716 #ifdef CONFIG_ARCH_OMAP1
718 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
722 #ifdef CONFIG_ARCH_OMAP15XX
723 case METHOD_GPIO_1510:
724 reg += OMAP1510_GPIO_INT_MASK;
728 #ifdef CONFIG_ARCH_OMAP16XX
729 case METHOD_GPIO_1610:
730 reg += OMAP1610_GPIO_IRQENABLE1;
733 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
734 case METHOD_GPIO_7XX:
735 reg += OMAP7XX_GPIO_INT_MASK;
739 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
740 case METHOD_GPIO_24XX:
741 reg += OMAP24XX_GPIO_IRQENABLE1;
744 #if defined(CONFIG_ARCH_OMAP4)
745 case METHOD_GPIO_44XX:
746 reg += OMAP4_GPIO_IRQSTATUSSET0;
754 l = __raw_readl(reg);
761 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
763 void __iomem *reg = bank->base;
766 switch (bank->method) {
767 #ifdef CONFIG_ARCH_OMAP1
769 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
770 l = __raw_readl(reg);
777 #ifdef CONFIG_ARCH_OMAP15XX
778 case METHOD_GPIO_1510:
779 reg += OMAP1510_GPIO_INT_MASK;
780 l = __raw_readl(reg);
787 #ifdef CONFIG_ARCH_OMAP16XX
788 case METHOD_GPIO_1610:
790 reg += OMAP1610_GPIO_SET_IRQENABLE1;
792 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
796 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
797 case METHOD_GPIO_7XX:
798 reg += OMAP7XX_GPIO_INT_MASK;
799 l = __raw_readl(reg);
806 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
807 case METHOD_GPIO_24XX:
809 reg += OMAP24XX_GPIO_SETIRQENABLE1;
811 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
815 #ifdef CONFIG_ARCH_OMAP4
816 case METHOD_GPIO_44XX:
818 reg += OMAP4_GPIO_IRQSTATUSSET0;
820 reg += OMAP4_GPIO_IRQSTATUSCLR0;
828 __raw_writel(l, reg);
831 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
833 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
837 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
838 * 1510 does not seem to have a wake-up register. If JTAG is connected
839 * to the target, system will wake up always on GPIO events. While
840 * system is running all registered GPIO interrupts need to have wake-up
841 * enabled. When system is suspended, only selected GPIO interrupts need
842 * to have wake-up enabled.
844 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
846 unsigned long uninitialized_var(flags);
848 switch (bank->method) {
849 #ifdef CONFIG_ARCH_OMAP16XX
851 case METHOD_GPIO_1610:
852 spin_lock_irqsave(&bank->lock, flags);
854 bank->suspend_wakeup |= (1 << gpio);
856 bank->suspend_wakeup &= ~(1 << gpio);
857 spin_unlock_irqrestore(&bank->lock, flags);
860 #ifdef CONFIG_ARCH_OMAP2PLUS
861 case METHOD_GPIO_24XX:
862 case METHOD_GPIO_44XX:
863 if (bank->non_wakeup_gpios & (1 << gpio)) {
864 printk(KERN_ERR "Unable to modify wakeup on "
865 "non-wakeup GPIO%d\n",
866 (bank - gpio_bank) * bank->width + gpio);
869 spin_lock_irqsave(&bank->lock, flags);
871 bank->suspend_wakeup |= (1 << gpio);
873 bank->suspend_wakeup &= ~(1 << gpio);
874 spin_unlock_irqrestore(&bank->lock, flags);
878 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
884 static void _reset_gpio(struct gpio_bank *bank, int gpio)
886 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
887 _set_gpio_irqenable(bank, gpio, 0);
888 _clear_gpio_irqstatus(bank, gpio);
889 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
892 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
893 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
895 unsigned int gpio = d->irq - IH_GPIO_BASE;
896 struct gpio_bank *bank;
899 if (check_gpio(gpio) < 0)
901 bank = irq_data_get_irq_chip_data(d);
902 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
907 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
909 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
912 spin_lock_irqsave(&bank->lock, flags);
914 /* Set trigger to none. You need to enable the desired trigger with
915 * request_irq() or set_irq_type().
917 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
919 #ifdef CONFIG_ARCH_OMAP15XX
920 if (bank->method == METHOD_GPIO_1510) {
923 /* Claim the pin for MPU */
924 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
925 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
928 if (!cpu_class_is_omap1()) {
929 if (!bank->mod_usage) {
930 void __iomem *reg = bank->base;
933 if (cpu_is_omap24xx() || cpu_is_omap34xx())
934 reg += OMAP24XX_GPIO_CTRL;
935 else if (cpu_is_omap44xx())
936 reg += OMAP4_GPIO_CTRL;
937 ctrl = __raw_readl(reg);
938 /* Module is enabled, clocks are not gated */
940 __raw_writel(ctrl, reg);
942 bank->mod_usage |= 1 << offset;
944 spin_unlock_irqrestore(&bank->lock, flags);
949 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
951 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
954 spin_lock_irqsave(&bank->lock, flags);
955 #ifdef CONFIG_ARCH_OMAP16XX
956 if (bank->method == METHOD_GPIO_1610) {
957 /* Disable wake-up during idle for dynamic tick */
958 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
959 __raw_writel(1 << offset, reg);
962 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
963 if (bank->method == METHOD_GPIO_24XX) {
964 /* Disable wake-up during idle for dynamic tick */
965 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
966 __raw_writel(1 << offset, reg);
969 #ifdef CONFIG_ARCH_OMAP4
970 if (bank->method == METHOD_GPIO_44XX) {
971 /* Disable wake-up during idle for dynamic tick */
972 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
973 __raw_writel(1 << offset, reg);
976 if (!cpu_class_is_omap1()) {
977 bank->mod_usage &= ~(1 << offset);
978 if (!bank->mod_usage) {
979 void __iomem *reg = bank->base;
982 if (cpu_is_omap24xx() || cpu_is_omap34xx())
983 reg += OMAP24XX_GPIO_CTRL;
984 else if (cpu_is_omap44xx())
985 reg += OMAP4_GPIO_CTRL;
986 ctrl = __raw_readl(reg);
987 /* Module is disabled, clocks are gated */
989 __raw_writel(ctrl, reg);
992 _reset_gpio(bank, bank->chip.base + offset);
993 spin_unlock_irqrestore(&bank->lock, flags);
997 * We need to unmask the GPIO bank interrupt as soon as possible to
998 * avoid missing GPIO interrupts for other lines in the bank.
999 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1000 * in the bank to avoid missing nested interrupts for a GPIO line.
1001 * If we wait to unmask individual GPIO lines in the bank after the
1002 * line's interrupt handler has been run, we may miss some nested
1005 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1007 void __iomem *isr_reg = NULL;
1009 unsigned int gpio_irq, gpio_index;
1010 struct gpio_bank *bank;
1013 struct irq_chip *chip = irq_desc_get_chip(desc);
1015 chained_irq_enter(chip, desc);
1017 bank = irq_get_handler_data(irq);
1018 #ifdef CONFIG_ARCH_OMAP1
1019 if (bank->method == METHOD_MPUIO)
1020 isr_reg = bank->base +
1021 OMAP_MPUIO_GPIO_INT / bank->stride;
1023 #ifdef CONFIG_ARCH_OMAP15XX
1024 if (bank->method == METHOD_GPIO_1510)
1025 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1027 #if defined(CONFIG_ARCH_OMAP16XX)
1028 if (bank->method == METHOD_GPIO_1610)
1029 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1031 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1032 if (bank->method == METHOD_GPIO_7XX)
1033 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1035 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1036 if (bank->method == METHOD_GPIO_24XX)
1037 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1039 #if defined(CONFIG_ARCH_OMAP4)
1040 if (bank->method == METHOD_GPIO_44XX)
1041 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1044 if (WARN_ON(!isr_reg))
1048 u32 isr_saved, level_mask = 0;
1051 enabled = _get_gpio_irqbank_mask(bank);
1052 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1054 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1057 if (cpu_class_is_omap2()) {
1058 level_mask = bank->level_mask & enabled;
1061 /* clear edge sensitive interrupts before handler(s) are
1062 called so that we don't miss any interrupt occurred while
1064 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1065 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1066 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1068 /* if there is only edge sensitive GPIO pin interrupts
1069 configured, we could unmask GPIO bank interrupt immediately */
1070 if (!level_mask && !unmasked) {
1072 chained_irq_exit(chip, desc);
1080 gpio_irq = bank->virtual_irq_start;
1081 for (; isr != 0; isr >>= 1, gpio_irq++) {
1082 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1087 #ifdef CONFIG_ARCH_OMAP1
1089 * Some chips can't respond to both rising and falling
1090 * at the same time. If this irq was requested with
1091 * both flags, we need to flip the ICR data for the IRQ
1092 * to respond to the IRQ for the opposite direction.
1093 * This will be indicated in the bank toggle_mask.
1095 if (bank->toggle_mask & (1 << gpio_index))
1096 _toggle_gpio_edge_triggering(bank, gpio_index);
1099 generic_handle_irq(gpio_irq);
1102 /* if bank has any level sensitive GPIO pin interrupt
1103 configured, we must unmask the bank interrupt only after
1104 handler(s) are executed in order to avoid spurious bank
1108 chained_irq_exit(chip, desc);
1111 static void gpio_irq_shutdown(struct irq_data *d)
1113 unsigned int gpio = d->irq - IH_GPIO_BASE;
1114 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1115 unsigned long flags;
1117 spin_lock_irqsave(&bank->lock, flags);
1118 _reset_gpio(bank, gpio);
1119 spin_unlock_irqrestore(&bank->lock, flags);
1122 static void gpio_ack_irq(struct irq_data *d)
1124 unsigned int gpio = d->irq - IH_GPIO_BASE;
1125 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1127 _clear_gpio_irqstatus(bank, gpio);
1130 static void gpio_mask_irq(struct irq_data *d)
1132 unsigned int gpio = d->irq - IH_GPIO_BASE;
1133 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1134 unsigned long flags;
1136 spin_lock_irqsave(&bank->lock, flags);
1137 _set_gpio_irqenable(bank, gpio, 0);
1138 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1139 spin_unlock_irqrestore(&bank->lock, flags);
1142 static void gpio_unmask_irq(struct irq_data *d)
1144 unsigned int gpio = d->irq - IH_GPIO_BASE;
1145 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1146 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1147 u32 trigger = irqd_get_trigger_type(d);
1148 unsigned long flags;
1150 spin_lock_irqsave(&bank->lock, flags);
1152 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1154 /* For level-triggered GPIOs, the clearing must be done after
1155 * the HW source is cleared, thus after the handler has run */
1156 if (bank->level_mask & irq_mask) {
1157 _set_gpio_irqenable(bank, gpio, 0);
1158 _clear_gpio_irqstatus(bank, gpio);
1161 _set_gpio_irqenable(bank, gpio, 1);
1162 spin_unlock_irqrestore(&bank->lock, flags);
1165 static struct irq_chip gpio_irq_chip = {
1167 .irq_shutdown = gpio_irq_shutdown,
1168 .irq_ack = gpio_ack_irq,
1169 .irq_mask = gpio_mask_irq,
1170 .irq_unmask = gpio_unmask_irq,
1171 .irq_set_type = gpio_irq_type,
1172 .irq_set_wake = gpio_wake_enable,
1175 /*---------------------------------------------------------------------*/
1177 #ifdef CONFIG_ARCH_OMAP1
1179 /* MPUIO uses the always-on 32k clock */
1181 static void mpuio_ack_irq(struct irq_data *d)
1183 /* The ISR is reset automatically, so do nothing here. */
1186 static void mpuio_mask_irq(struct irq_data *d)
1188 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1189 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1191 _set_gpio_irqenable(bank, gpio, 0);
1194 static void mpuio_unmask_irq(struct irq_data *d)
1196 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1197 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1199 _set_gpio_irqenable(bank, gpio, 1);
1202 static struct irq_chip mpuio_irq_chip = {
1204 .irq_ack = mpuio_ack_irq,
1205 .irq_mask = mpuio_mask_irq,
1206 .irq_unmask = mpuio_unmask_irq,
1207 .irq_set_type = gpio_irq_type,
1208 #ifdef CONFIG_ARCH_OMAP16XX
1209 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1210 .irq_set_wake = gpio_wake_enable,
1215 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1218 #ifdef CONFIG_ARCH_OMAP16XX
1220 #include <linux/platform_device.h>
1222 static int omap_mpuio_suspend_noirq(struct device *dev)
1224 struct platform_device *pdev = to_platform_device(dev);
1225 struct gpio_bank *bank = platform_get_drvdata(pdev);
1226 void __iomem *mask_reg = bank->base +
1227 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1228 unsigned long flags;
1230 spin_lock_irqsave(&bank->lock, flags);
1231 bank->saved_wakeup = __raw_readl(mask_reg);
1232 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1233 spin_unlock_irqrestore(&bank->lock, flags);
1238 static int omap_mpuio_resume_noirq(struct device *dev)
1240 struct platform_device *pdev = to_platform_device(dev);
1241 struct gpio_bank *bank = platform_get_drvdata(pdev);
1242 void __iomem *mask_reg = bank->base +
1243 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1244 unsigned long flags;
1246 spin_lock_irqsave(&bank->lock, flags);
1247 __raw_writel(bank->saved_wakeup, mask_reg);
1248 spin_unlock_irqrestore(&bank->lock, flags);
1253 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1254 .suspend_noirq = omap_mpuio_suspend_noirq,
1255 .resume_noirq = omap_mpuio_resume_noirq,
1258 /* use platform_driver for this. */
1259 static struct platform_driver omap_mpuio_driver = {
1262 .pm = &omap_mpuio_dev_pm_ops,
1266 static struct platform_device omap_mpuio_device = {
1270 .driver = &omap_mpuio_driver.driver,
1272 /* could list the /proc/iomem resources */
1275 static inline void mpuio_init(void)
1277 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1278 platform_set_drvdata(&omap_mpuio_device, bank);
1280 if (platform_driver_register(&omap_mpuio_driver) == 0)
1281 (void) platform_device_register(&omap_mpuio_device);
1285 static inline void mpuio_init(void) {}
1290 extern struct irq_chip mpuio_irq_chip;
1292 #define bank_is_mpuio(bank) 0
1293 static inline void mpuio_init(void) {}
1297 /*---------------------------------------------------------------------*/
1299 /* REVISIT these are stupid implementations! replace by ones that
1300 * don't switch on METHOD_* and which mostly avoid spinlocks
1303 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1305 struct gpio_bank *bank;
1306 unsigned long flags;
1308 bank = container_of(chip, struct gpio_bank, chip);
1309 spin_lock_irqsave(&bank->lock, flags);
1310 _set_gpio_direction(bank, offset, 1);
1311 spin_unlock_irqrestore(&bank->lock, flags);
1315 static int gpio_is_input(struct gpio_bank *bank, int mask)
1317 void __iomem *reg = bank->base;
1319 switch (bank->method) {
1321 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1323 case METHOD_GPIO_1510:
1324 reg += OMAP1510_GPIO_DIR_CONTROL;
1326 case METHOD_GPIO_1610:
1327 reg += OMAP1610_GPIO_DIRECTION;
1329 case METHOD_GPIO_7XX:
1330 reg += OMAP7XX_GPIO_DIR_CONTROL;
1332 case METHOD_GPIO_24XX:
1333 reg += OMAP24XX_GPIO_OE;
1335 case METHOD_GPIO_44XX:
1336 reg += OMAP4_GPIO_OE;
1339 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1342 return __raw_readl(reg) & mask;
1345 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1347 struct gpio_bank *bank;
1352 gpio = chip->base + offset;
1353 bank = get_gpio_bank(gpio);
1355 mask = 1 << get_gpio_index(gpio);
1357 if (gpio_is_input(bank, mask))
1358 return _get_gpio_datain(bank, gpio);
1360 return _get_gpio_dataout(bank, gpio);
1363 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1365 struct gpio_bank *bank;
1366 unsigned long flags;
1368 bank = container_of(chip, struct gpio_bank, chip);
1369 spin_lock_irqsave(&bank->lock, flags);
1370 _set_gpio_dataout(bank, offset, value);
1371 _set_gpio_direction(bank, offset, 0);
1372 spin_unlock_irqrestore(&bank->lock, flags);
1376 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1379 struct gpio_bank *bank;
1380 unsigned long flags;
1382 bank = container_of(chip, struct gpio_bank, chip);
1385 bank->dbck = clk_get(bank->dev, "dbclk");
1386 if (IS_ERR(bank->dbck))
1387 dev_err(bank->dev, "Could not get gpio dbck\n");
1390 spin_lock_irqsave(&bank->lock, flags);
1391 _set_gpio_debounce(bank, offset, debounce);
1392 spin_unlock_irqrestore(&bank->lock, flags);
1397 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1399 struct gpio_bank *bank;
1400 unsigned long flags;
1402 bank = container_of(chip, struct gpio_bank, chip);
1403 spin_lock_irqsave(&bank->lock, flags);
1404 _set_gpio_dataout(bank, offset, value);
1405 spin_unlock_irqrestore(&bank->lock, flags);
1408 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1410 struct gpio_bank *bank;
1412 bank = container_of(chip, struct gpio_bank, chip);
1413 return bank->virtual_irq_start + offset;
1416 /*---------------------------------------------------------------------*/
1418 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1422 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1423 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1424 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1425 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1426 else if (cpu_is_omap44xx())
1427 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1431 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1432 (rev >> 4) & 0x0f, rev & 0x0f);
1435 /* This lock class tells lockdep that GPIO irqs are in a different
1436 * category than their parents, so it won't report false recursion.
1438 static struct lock_class_key gpio_lock_class;
1440 static inline int init_gpio_info(struct platform_device *pdev)
1442 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1443 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1446 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1452 /* TODO: Cleanup cpu_is_* checks */
1453 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1455 if (cpu_class_is_omap2()) {
1456 if (cpu_is_omap44xx()) {
1457 __raw_writel(0xffffffff, bank->base +
1458 OMAP4_GPIO_IRQSTATUSCLR0);
1459 __raw_writel(0x00000000, bank->base +
1460 OMAP4_GPIO_DEBOUNCENABLE);
1461 /* Initialize interface clk ungated, module enabled */
1462 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1463 } else if (cpu_is_omap34xx()) {
1464 __raw_writel(0x00000000, bank->base +
1465 OMAP24XX_GPIO_IRQENABLE1);
1466 __raw_writel(0xffffffff, bank->base +
1467 OMAP24XX_GPIO_IRQSTATUS1);
1468 __raw_writel(0x00000000, bank->base +
1469 OMAP24XX_GPIO_DEBOUNCE_EN);
1471 /* Initialize interface clk ungated, module enabled */
1472 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1473 } else if (cpu_is_omap24xx()) {
1474 static const u32 non_wakeup_gpios[] = {
1475 0xe203ffc0, 0x08700040
1477 if (id < ARRAY_SIZE(non_wakeup_gpios))
1478 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1480 } else if (cpu_class_is_omap1()) {
1481 if (bank_is_mpuio(bank))
1482 __raw_writew(0xffff, bank->base +
1483 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1484 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1485 __raw_writew(0xffff, bank->base
1486 + OMAP1510_GPIO_INT_MASK);
1487 __raw_writew(0x0000, bank->base
1488 + OMAP1510_GPIO_INT_STATUS);
1490 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1491 __raw_writew(0x0000, bank->base
1492 + OMAP1610_GPIO_IRQENABLE1);
1493 __raw_writew(0xffff, bank->base
1494 + OMAP1610_GPIO_IRQSTATUS1);
1495 __raw_writew(0x0014, bank->base
1496 + OMAP1610_GPIO_SYSCONFIG);
1499 * Enable system clock for GPIO module.
1500 * The CAM_CLK_CTRL *is* really the right place.
1502 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1505 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1506 __raw_writel(0xffffffff, bank->base
1507 + OMAP7XX_GPIO_INT_MASK);
1508 __raw_writel(0x00000000, bank->base
1509 + OMAP7XX_GPIO_INT_STATUS);
1514 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1519 bank->mod_usage = 0;
1521 * REVISIT eventually switch from OMAP-specific gpio structs
1522 * over to the generic ones
1524 bank->chip.request = omap_gpio_request;
1525 bank->chip.free = omap_gpio_free;
1526 bank->chip.direction_input = gpio_input;
1527 bank->chip.get = gpio_get;
1528 bank->chip.direction_output = gpio_output;
1529 bank->chip.set_debounce = gpio_debounce;
1530 bank->chip.set = gpio_set;
1531 bank->chip.to_irq = gpio_2irq;
1532 if (bank_is_mpuio(bank)) {
1533 bank->chip.label = "mpuio";
1534 #ifdef CONFIG_ARCH_OMAP16XX
1535 bank->chip.dev = &omap_mpuio_device.dev;
1537 bank->chip.base = OMAP_MPUIO(0);
1539 bank->chip.label = "gpio";
1540 bank->chip.base = gpio;
1541 gpio += bank->width;
1543 bank->chip.ngpio = bank->width;
1545 gpiochip_add(&bank->chip);
1547 for (j = bank->virtual_irq_start;
1548 j < bank->virtual_irq_start + bank->width; j++) {
1549 irq_set_lockdep_class(j, &gpio_lock_class);
1550 irq_set_chip_data(j, bank);
1551 if (bank_is_mpuio(bank))
1552 irq_set_chip(j, &mpuio_irq_chip);
1554 irq_set_chip(j, &gpio_irq_chip);
1555 irq_set_handler(j, handle_simple_irq);
1556 set_irq_flags(j, IRQF_VALID);
1558 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1559 irq_set_handler_data(bank->irq, bank);
1562 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1564 static int gpio_init_done;
1565 struct omap_gpio_platform_data *pdata;
1566 struct resource *res;
1568 struct gpio_bank *bank;
1570 if (!pdev->dev.platform_data)
1573 pdata = pdev->dev.platform_data;
1575 if (!gpio_init_done) {
1578 ret = init_gpio_info(pdev);
1584 bank = &gpio_bank[id];
1586 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1587 if (unlikely(!res)) {
1588 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1592 bank->irq = res->start;
1593 bank->virtual_irq_start = pdata->virtual_irq_start;
1594 bank->method = pdata->bank_type;
1595 bank->dev = &pdev->dev;
1596 bank->dbck_flag = pdata->dbck_flag;
1597 bank->stride = pdata->bank_stride;
1598 bank->width = pdata->bank_width;
1600 spin_lock_init(&bank->lock);
1602 /* Static mapping, never released */
1603 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1604 if (unlikely(!res)) {
1605 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1609 bank->base = ioremap(res->start, resource_size(res));
1611 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1615 pm_runtime_enable(bank->dev);
1616 pm_runtime_get_sync(bank->dev);
1618 omap_gpio_mod_init(bank, id);
1619 omap_gpio_chip_init(bank);
1620 omap_gpio_show_rev(bank);
1622 if (!gpio_init_done)
1628 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1629 static int omap_gpio_suspend(void)
1633 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1636 for (i = 0; i < gpio_bank_count; i++) {
1637 struct gpio_bank *bank = &gpio_bank[i];
1638 void __iomem *wake_status;
1639 void __iomem *wake_clear;
1640 void __iomem *wake_set;
1641 unsigned long flags;
1643 switch (bank->method) {
1644 #ifdef CONFIG_ARCH_OMAP16XX
1645 case METHOD_GPIO_1610:
1646 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1647 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1648 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1651 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1652 case METHOD_GPIO_24XX:
1653 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1654 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1655 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1658 #ifdef CONFIG_ARCH_OMAP4
1659 case METHOD_GPIO_44XX:
1660 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1661 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1662 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1669 spin_lock_irqsave(&bank->lock, flags);
1670 bank->saved_wakeup = __raw_readl(wake_status);
1671 __raw_writel(0xffffffff, wake_clear);
1672 __raw_writel(bank->suspend_wakeup, wake_set);
1673 spin_unlock_irqrestore(&bank->lock, flags);
1679 static void omap_gpio_resume(void)
1683 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1686 for (i = 0; i < gpio_bank_count; i++) {
1687 struct gpio_bank *bank = &gpio_bank[i];
1688 void __iomem *wake_clear;
1689 void __iomem *wake_set;
1690 unsigned long flags;
1692 switch (bank->method) {
1693 #ifdef CONFIG_ARCH_OMAP16XX
1694 case METHOD_GPIO_1610:
1695 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1696 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1699 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1700 case METHOD_GPIO_24XX:
1701 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1702 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1705 #ifdef CONFIG_ARCH_OMAP4
1706 case METHOD_GPIO_44XX:
1707 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1708 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1715 spin_lock_irqsave(&bank->lock, flags);
1716 __raw_writel(0xffffffff, wake_clear);
1717 __raw_writel(bank->saved_wakeup, wake_set);
1718 spin_unlock_irqrestore(&bank->lock, flags);
1722 static struct syscore_ops omap_gpio_syscore_ops = {
1723 .suspend = omap_gpio_suspend,
1724 .resume = omap_gpio_resume,
1729 #ifdef CONFIG_ARCH_OMAP2PLUS
1731 static int workaround_enabled;
1733 void omap2_gpio_prepare_for_idle(int off_mode)
1738 if (cpu_is_omap34xx())
1741 for (i = min; i < gpio_bank_count; i++) {
1742 struct gpio_bank *bank = &gpio_bank[i];
1746 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1747 clk_disable(bank->dbck);
1752 /* If going to OFF, remove triggering for all
1753 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1754 * generated. See OMAP2420 Errata item 1.101. */
1755 if (!(bank->enabled_non_wakeup_gpios))
1758 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1759 bank->saved_datain = __raw_readl(bank->base +
1760 OMAP24XX_GPIO_DATAIN);
1761 l1 = __raw_readl(bank->base +
1762 OMAP24XX_GPIO_FALLINGDETECT);
1763 l2 = __raw_readl(bank->base +
1764 OMAP24XX_GPIO_RISINGDETECT);
1767 if (cpu_is_omap44xx()) {
1768 bank->saved_datain = __raw_readl(bank->base +
1770 l1 = __raw_readl(bank->base +
1771 OMAP4_GPIO_FALLINGDETECT);
1772 l2 = __raw_readl(bank->base +
1773 OMAP4_GPIO_RISINGDETECT);
1776 bank->saved_fallingdetect = l1;
1777 bank->saved_risingdetect = l2;
1778 l1 &= ~bank->enabled_non_wakeup_gpios;
1779 l2 &= ~bank->enabled_non_wakeup_gpios;
1781 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1782 __raw_writel(l1, bank->base +
1783 OMAP24XX_GPIO_FALLINGDETECT);
1784 __raw_writel(l2, bank->base +
1785 OMAP24XX_GPIO_RISINGDETECT);
1788 if (cpu_is_omap44xx()) {
1789 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1790 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1796 workaround_enabled = 0;
1799 workaround_enabled = 1;
1802 void omap2_gpio_resume_after_idle(void)
1807 if (cpu_is_omap34xx())
1809 for (i = min; i < gpio_bank_count; i++) {
1810 struct gpio_bank *bank = &gpio_bank[i];
1811 u32 l = 0, gen, gen0, gen1;
1814 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1815 clk_enable(bank->dbck);
1817 if (!workaround_enabled)
1820 if (!(bank->enabled_non_wakeup_gpios))
1823 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1824 __raw_writel(bank->saved_fallingdetect,
1825 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1826 __raw_writel(bank->saved_risingdetect,
1827 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1828 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1831 if (cpu_is_omap44xx()) {
1832 __raw_writel(bank->saved_fallingdetect,
1833 bank->base + OMAP4_GPIO_FALLINGDETECT);
1834 __raw_writel(bank->saved_risingdetect,
1835 bank->base + OMAP4_GPIO_RISINGDETECT);
1836 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1839 /* Check if any of the non-wakeup interrupt GPIOs have changed
1840 * state. If so, generate an IRQ by software. This is
1841 * horribly racy, but it's the best we can do to work around
1842 * this silicon bug. */
1843 l ^= bank->saved_datain;
1844 l &= bank->enabled_non_wakeup_gpios;
1847 * No need to generate IRQs for the rising edge for gpio IRQs
1848 * configured with falling edge only; and vice versa.
1850 gen0 = l & bank->saved_fallingdetect;
1851 gen0 &= bank->saved_datain;
1853 gen1 = l & bank->saved_risingdetect;
1854 gen1 &= ~(bank->saved_datain);
1856 /* FIXME: Consider GPIO IRQs with level detections properly! */
1857 gen = l & (~(bank->saved_fallingdetect) &
1858 ~(bank->saved_risingdetect));
1859 /* Consider all GPIO IRQs needed to be updated */
1865 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1866 old0 = __raw_readl(bank->base +
1867 OMAP24XX_GPIO_LEVELDETECT0);
1868 old1 = __raw_readl(bank->base +
1869 OMAP24XX_GPIO_LEVELDETECT1);
1870 __raw_writel(old0 | gen, bank->base +
1871 OMAP24XX_GPIO_LEVELDETECT0);
1872 __raw_writel(old1 | gen, bank->base +
1873 OMAP24XX_GPIO_LEVELDETECT1);
1874 __raw_writel(old0, bank->base +
1875 OMAP24XX_GPIO_LEVELDETECT0);
1876 __raw_writel(old1, bank->base +
1877 OMAP24XX_GPIO_LEVELDETECT1);
1880 if (cpu_is_omap44xx()) {
1881 old0 = __raw_readl(bank->base +
1882 OMAP4_GPIO_LEVELDETECT0);
1883 old1 = __raw_readl(bank->base +
1884 OMAP4_GPIO_LEVELDETECT1);
1885 __raw_writel(old0 | l, bank->base +
1886 OMAP4_GPIO_LEVELDETECT0);
1887 __raw_writel(old1 | l, bank->base +
1888 OMAP4_GPIO_LEVELDETECT1);
1889 __raw_writel(old0, bank->base +
1890 OMAP4_GPIO_LEVELDETECT0);
1891 __raw_writel(old1, bank->base +
1892 OMAP4_GPIO_LEVELDETECT1);
1901 #ifdef CONFIG_ARCH_OMAP3
1902 /* save the registers of bank 2-6 */
1903 void omap_gpio_save_context(void)
1907 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1908 for (i = 1; i < gpio_bank_count; i++) {
1909 struct gpio_bank *bank = &gpio_bank[i];
1910 gpio_context[i].irqenable1 =
1911 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1912 gpio_context[i].irqenable2 =
1913 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1914 gpio_context[i].wake_en =
1915 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1916 gpio_context[i].ctrl =
1917 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1918 gpio_context[i].oe =
1919 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1920 gpio_context[i].leveldetect0 =
1921 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1922 gpio_context[i].leveldetect1 =
1923 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1924 gpio_context[i].risingdetect =
1925 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1926 gpio_context[i].fallingdetect =
1927 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1928 gpio_context[i].dataout =
1929 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1933 /* restore the required registers of bank 2-6 */
1934 void omap_gpio_restore_context(void)
1938 for (i = 1; i < gpio_bank_count; i++) {
1939 struct gpio_bank *bank = &gpio_bank[i];
1940 __raw_writel(gpio_context[i].irqenable1,
1941 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1942 __raw_writel(gpio_context[i].irqenable2,
1943 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1944 __raw_writel(gpio_context[i].wake_en,
1945 bank->base + OMAP24XX_GPIO_WAKE_EN);
1946 __raw_writel(gpio_context[i].ctrl,
1947 bank->base + OMAP24XX_GPIO_CTRL);
1948 __raw_writel(gpio_context[i].oe,
1949 bank->base + OMAP24XX_GPIO_OE);
1950 __raw_writel(gpio_context[i].leveldetect0,
1951 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1952 __raw_writel(gpio_context[i].leveldetect1,
1953 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1954 __raw_writel(gpio_context[i].risingdetect,
1955 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1956 __raw_writel(gpio_context[i].fallingdetect,
1957 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1958 __raw_writel(gpio_context[i].dataout,
1959 bank->base + OMAP24XX_GPIO_DATAOUT);
1964 static struct platform_driver omap_gpio_driver = {
1965 .probe = omap_gpio_probe,
1967 .name = "omap_gpio",
1972 * gpio driver register needs to be done before
1973 * machine_init functions access gpio APIs.
1974 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1976 static int __init omap_gpio_drv_reg(void)
1978 return platform_driver_register(&omap_gpio_driver);
1980 postcore_initcall(omap_gpio_drv_reg);
1982 static int __init omap_gpio_sysinit(void)
1986 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1987 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1988 register_syscore_ops(&omap_gpio_syscore_ops);
1994 arch_initcall(omap_gpio_sysinit);