2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/of_device.h>
27 #include <linux/irqdomain.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/gpio.h>
30 #include <linux/platform_data/gpio-omap.h>
34 static LIST_HEAD(omap_gpio_list);
52 struct list_head node;
55 struct irq_domain *domain;
57 u32 enabled_non_wakeup_gpios;
58 struct gpio_regs context;
63 struct gpio_chip chip;
76 int context_loss_count;
78 bool workaround_enabled;
80 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
81 int (*get_context_loss_count)(struct device *dev);
83 struct omap_gpio_reg_offs *regs;
86 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
87 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
88 #define GPIO_MOD_CTRL_BIT BIT(0)
90 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
91 #define LINE_USED(line, offset) (line & (1 << offset))
93 static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
95 return bank->chip.base + gpio_irq;
98 static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
100 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
102 return irq_find_mapping(bank->domain, offset);
105 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
107 void __iomem *reg = bank->base;
110 reg += bank->regs->direction;
111 l = readl_relaxed(reg);
116 writel_relaxed(l, reg);
117 bank->context.oe = l;
121 /* set data out value using dedicate set/clear register */
122 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
124 void __iomem *reg = bank->base;
125 u32 l = GPIO_BIT(bank, gpio);
128 reg += bank->regs->set_dataout;
129 bank->context.dataout |= l;
131 reg += bank->regs->clr_dataout;
132 bank->context.dataout &= ~l;
135 writel_relaxed(l, reg);
138 /* set data out value using mask register */
139 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
141 void __iomem *reg = bank->base + bank->regs->dataout;
142 u32 gpio_bit = GPIO_BIT(bank, gpio);
145 l = readl_relaxed(reg);
150 writel_relaxed(l, reg);
151 bank->context.dataout = l;
154 static int _get_gpio_datain(struct gpio_bank *bank, int offset)
156 void __iomem *reg = bank->base + bank->regs->datain;
158 return (readl_relaxed(reg) & (1 << offset)) != 0;
161 static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
163 void __iomem *reg = bank->base + bank->regs->dataout;
165 return (readl_relaxed(reg) & (1 << offset)) != 0;
168 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
170 int l = readl_relaxed(base + reg);
177 writel_relaxed(l, base + reg);
180 static inline void _gpio_dbck_enable(struct gpio_bank *bank)
182 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
183 clk_enable(bank->dbck);
184 bank->dbck_enabled = true;
186 writel_relaxed(bank->dbck_enable_mask,
187 bank->base + bank->regs->debounce_en);
191 static inline void _gpio_dbck_disable(struct gpio_bank *bank)
193 if (bank->dbck_enable_mask && bank->dbck_enabled) {
195 * Disable debounce before cutting it's clock. If debounce is
196 * enabled but the clock is not, GPIO module seems to be unable
197 * to detect events and generate interrupts at least on OMAP3.
199 writel_relaxed(0, bank->base + bank->regs->debounce_en);
201 clk_disable(bank->dbck);
202 bank->dbck_enabled = false;
207 * _set_gpio_debounce - low level gpio debounce time
208 * @bank: the gpio bank we're acting upon
209 * @gpio: the gpio number on this @gpio
210 * @debounce: debounce time to use
212 * OMAP's debounce time is in 31us steps so we need
213 * to convert and round up to the closest unit.
215 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
222 if (!bank->dbck_flag)
227 else if (debounce > 7936)
230 debounce = (debounce / 0x1f) - 1;
232 l = GPIO_BIT(bank, gpio);
234 clk_enable(bank->dbck);
235 reg = bank->base + bank->regs->debounce;
236 writel_relaxed(debounce, reg);
238 reg = bank->base + bank->regs->debounce_en;
239 val = readl_relaxed(reg);
245 bank->dbck_enable_mask = val;
247 writel_relaxed(val, reg);
248 clk_disable(bank->dbck);
250 * Enable debounce clock per module.
251 * This call is mandatory because in omap_gpio_request() when
252 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
253 * runtime callbck fails to turn on dbck because dbck_enable_mask
254 * used within _gpio_dbck_enable() is still not initialized at
255 * that point. Therefore we have to enable dbck here.
257 _gpio_dbck_enable(bank);
258 if (bank->dbck_enable_mask) {
259 bank->context.debounce = debounce;
260 bank->context.debounce_en = val;
265 * _clear_gpio_debounce - clear debounce settings for a gpio
266 * @bank: the gpio bank we're acting upon
267 * @gpio: the gpio number on this @gpio
269 * If a gpio is using debounce, then clear the debounce enable bit and if
270 * this is the only gpio in this bank using debounce, then clear the debounce
271 * time too. The debounce clock will also be disabled when calling this function
272 * if this is the only gpio in the bank using debounce.
274 static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
276 u32 gpio_bit = GPIO_BIT(bank, gpio);
278 if (!bank->dbck_flag)
281 if (!(bank->dbck_enable_mask & gpio_bit))
284 bank->dbck_enable_mask &= ~gpio_bit;
285 bank->context.debounce_en &= ~gpio_bit;
286 writel_relaxed(bank->context.debounce_en,
287 bank->base + bank->regs->debounce_en);
289 if (!bank->dbck_enable_mask) {
290 bank->context.debounce = 0;
291 writel_relaxed(bank->context.debounce, bank->base +
292 bank->regs->debounce);
293 clk_disable(bank->dbck);
294 bank->dbck_enabled = false;
298 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
301 void __iomem *base = bank->base;
302 u32 gpio_bit = 1 << gpio;
304 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
305 trigger & IRQ_TYPE_LEVEL_LOW);
306 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
307 trigger & IRQ_TYPE_LEVEL_HIGH);
308 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
309 trigger & IRQ_TYPE_EDGE_RISING);
310 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
311 trigger & IRQ_TYPE_EDGE_FALLING);
313 bank->context.leveldetect0 =
314 readl_relaxed(bank->base + bank->regs->leveldetect0);
315 bank->context.leveldetect1 =
316 readl_relaxed(bank->base + bank->regs->leveldetect1);
317 bank->context.risingdetect =
318 readl_relaxed(bank->base + bank->regs->risingdetect);
319 bank->context.fallingdetect =
320 readl_relaxed(bank->base + bank->regs->fallingdetect);
322 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
323 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
324 bank->context.wake_en =
325 readl_relaxed(bank->base + bank->regs->wkup_en);
328 /* This part needs to be executed always for OMAP{34xx, 44xx} */
329 if (!bank->regs->irqctrl) {
330 /* On omap24xx proceed only when valid GPIO bit is set */
331 if (bank->non_wakeup_gpios) {
332 if (!(bank->non_wakeup_gpios & gpio_bit))
337 * Log the edge gpio and manually trigger the IRQ
338 * after resume if the input level changes
339 * to avoid irq lost during PER RET/OFF mode
340 * Applies for omap2 non-wakeup gpio and all omap3 gpios
342 if (trigger & IRQ_TYPE_EDGE_BOTH)
343 bank->enabled_non_wakeup_gpios |= gpio_bit;
345 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
350 readl_relaxed(bank->base + bank->regs->leveldetect0) |
351 readl_relaxed(bank->base + bank->regs->leveldetect1);
354 #ifdef CONFIG_ARCH_OMAP1
356 * This only applies to chips that can't do both rising and falling edge
357 * detection at once. For all other chips, this function is a noop.
359 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
361 void __iomem *reg = bank->base;
364 if (!bank->regs->irqctrl)
367 reg += bank->regs->irqctrl;
369 l = readl_relaxed(reg);
375 writel_relaxed(l, reg);
378 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
381 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
384 void __iomem *reg = bank->base;
385 void __iomem *base = bank->base;
388 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
389 set_gpio_trigger(bank, gpio, trigger);
390 } else if (bank->regs->irqctrl) {
391 reg += bank->regs->irqctrl;
393 l = readl_relaxed(reg);
394 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
395 bank->toggle_mask |= 1 << gpio;
396 if (trigger & IRQ_TYPE_EDGE_RISING)
398 else if (trigger & IRQ_TYPE_EDGE_FALLING)
403 writel_relaxed(l, reg);
404 } else if (bank->regs->edgectrl1) {
406 reg += bank->regs->edgectrl2;
408 reg += bank->regs->edgectrl1;
411 l = readl_relaxed(reg);
412 l &= ~(3 << (gpio << 1));
413 if (trigger & IRQ_TYPE_EDGE_RISING)
414 l |= 2 << (gpio << 1);
415 if (trigger & IRQ_TYPE_EDGE_FALLING)
416 l |= 1 << (gpio << 1);
418 /* Enable wake-up during idle for dynamic tick */
419 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
420 bank->context.wake_en =
421 readl_relaxed(bank->base + bank->regs->wkup_en);
422 writel_relaxed(l, reg);
427 static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset)
429 if (bank->regs->pinctrl) {
430 void __iomem *reg = bank->base + bank->regs->pinctrl;
432 /* Claim the pin for MPU */
433 writel_relaxed(readl_relaxed(reg) | (1 << offset), reg);
436 if (bank->regs->ctrl && !BANK_USED(bank)) {
437 void __iomem *reg = bank->base + bank->regs->ctrl;
440 ctrl = readl_relaxed(reg);
441 /* Module is enabled, clocks are not gated */
442 ctrl &= ~GPIO_MOD_CTRL_BIT;
443 writel_relaxed(ctrl, reg);
444 bank->context.ctrl = ctrl;
448 static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset)
450 void __iomem *base = bank->base;
452 if (bank->regs->wkup_en &&
453 !LINE_USED(bank->mod_usage, offset) &&
454 !LINE_USED(bank->irq_usage, offset)) {
455 /* Disable wake-up during idle for dynamic tick */
456 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
457 bank->context.wake_en =
458 readl_relaxed(bank->base + bank->regs->wkup_en);
461 if (bank->regs->ctrl && !BANK_USED(bank)) {
462 void __iomem *reg = bank->base + bank->regs->ctrl;
465 ctrl = readl_relaxed(reg);
466 /* Module is disabled, clocks are gated */
467 ctrl |= GPIO_MOD_CTRL_BIT;
468 writel_relaxed(ctrl, reg);
469 bank->context.ctrl = ctrl;
473 static int gpio_is_input(struct gpio_bank *bank, int mask)
475 void __iomem *reg = bank->base + bank->regs->direction;
477 return readl_relaxed(reg) & mask;
480 static int gpio_irq_type(struct irq_data *d, unsigned type)
482 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
488 if (!BANK_USED(bank))
489 pm_runtime_get_sync(bank->dev);
491 #ifdef CONFIG_ARCH_OMAP1
492 if (d->irq > IH_MPUIO_BASE)
493 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
497 gpio = irq_to_gpio(bank, d->hwirq);
499 if (type & ~IRQ_TYPE_SENSE_MASK)
502 if (!bank->regs->leveldetect0 &&
503 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
506 spin_lock_irqsave(&bank->lock, flags);
507 offset = GPIO_INDEX(bank, gpio);
508 retval = _set_gpio_triggering(bank, offset, type);
509 if (!LINE_USED(bank->mod_usage, offset)) {
510 _enable_gpio_module(bank, offset);
511 _set_gpio_direction(bank, offset, 1);
512 } else if (!gpio_is_input(bank, 1 << offset)) {
513 spin_unlock_irqrestore(&bank->lock, flags);
517 retval = gpio_lock_as_irq(&bank->chip, offset);
519 dev_err(bank->dev, "unable to lock offset %d for IRQ\n",
521 spin_unlock_irqrestore(&bank->lock, flags);
525 bank->irq_usage |= 1 << GPIO_INDEX(bank, gpio);
526 spin_unlock_irqrestore(&bank->lock, flags);
528 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
529 __irq_set_handler_locked(d->irq, handle_level_irq);
530 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
531 __irq_set_handler_locked(d->irq, handle_edge_irq);
536 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
538 void __iomem *reg = bank->base;
540 reg += bank->regs->irqstatus;
541 writel_relaxed(gpio_mask, reg);
543 /* Workaround for clearing DSP GPIO interrupts to allow retention */
544 if (bank->regs->irqstatus2) {
545 reg = bank->base + bank->regs->irqstatus2;
546 writel_relaxed(gpio_mask, reg);
549 /* Flush posted write for the irq status to avoid spurious interrupts */
553 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
555 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
558 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
560 void __iomem *reg = bank->base;
562 u32 mask = (1 << bank->width) - 1;
564 reg += bank->regs->irqenable;
565 l = readl_relaxed(reg);
566 if (bank->regs->irqenable_inv)
572 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
574 void __iomem *reg = bank->base;
577 if (bank->regs->set_irqenable) {
578 reg += bank->regs->set_irqenable;
580 bank->context.irqenable1 |= gpio_mask;
582 reg += bank->regs->irqenable;
583 l = readl_relaxed(reg);
584 if (bank->regs->irqenable_inv)
588 bank->context.irqenable1 = l;
591 writel_relaxed(l, reg);
594 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
596 void __iomem *reg = bank->base;
599 if (bank->regs->clr_irqenable) {
600 reg += bank->regs->clr_irqenable;
602 bank->context.irqenable1 &= ~gpio_mask;
604 reg += bank->regs->irqenable;
605 l = readl_relaxed(reg);
606 if (bank->regs->irqenable_inv)
610 bank->context.irqenable1 = l;
613 writel_relaxed(l, reg);
616 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
619 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
621 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
625 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
626 * 1510 does not seem to have a wake-up register. If JTAG is connected
627 * to the target, system will wake up always on GPIO events. While
628 * system is running all registered GPIO interrupts need to have wake-up
629 * enabled. When system is suspended, only selected GPIO interrupts need
630 * to have wake-up enabled.
632 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
634 u32 gpio_bit = GPIO_BIT(bank, gpio);
637 if (bank->non_wakeup_gpios & gpio_bit) {
639 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
643 spin_lock_irqsave(&bank->lock, flags);
645 bank->context.wake_en |= gpio_bit;
647 bank->context.wake_en &= ~gpio_bit;
649 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
650 spin_unlock_irqrestore(&bank->lock, flags);
655 static void _reset_gpio(struct gpio_bank *bank, int gpio)
657 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
658 _set_gpio_irqenable(bank, gpio, 0);
659 _clear_gpio_irqstatus(bank, gpio);
660 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
661 _clear_gpio_debounce(bank, gpio);
664 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
665 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
667 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
668 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
670 return _set_gpio_wakeup(bank, gpio, enable);
673 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
675 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
679 * If this is the first gpio_request for the bank,
680 * enable the bank module.
682 if (!BANK_USED(bank))
683 pm_runtime_get_sync(bank->dev);
685 spin_lock_irqsave(&bank->lock, flags);
686 /* Set trigger to none. You need to enable the desired trigger with
687 * request_irq() or set_irq_type(). Only do this if the IRQ line has
688 * not already been requested.
690 if (!LINE_USED(bank->irq_usage, offset)) {
691 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
692 _enable_gpio_module(bank, offset);
694 bank->mod_usage |= 1 << offset;
695 spin_unlock_irqrestore(&bank->lock, flags);
700 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
702 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
705 spin_lock_irqsave(&bank->lock, flags);
706 bank->mod_usage &= ~(1 << offset);
707 _disable_gpio_module(bank, offset);
708 _reset_gpio(bank, bank->chip.base + offset);
709 spin_unlock_irqrestore(&bank->lock, flags);
712 * If this is the last gpio to be freed in the bank,
713 * disable the bank module.
715 if (!BANK_USED(bank))
716 pm_runtime_put(bank->dev);
720 * We need to unmask the GPIO bank interrupt as soon as possible to
721 * avoid missing GPIO interrupts for other lines in the bank.
722 * Then we need to mask-read-clear-unmask the triggered GPIO lines
723 * in the bank to avoid missing nested interrupts for a GPIO line.
724 * If we wait to unmask individual GPIO lines in the bank after the
725 * line's interrupt handler has been run, we may miss some nested
728 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
730 void __iomem *isr_reg = NULL;
733 struct gpio_bank *bank;
735 struct irq_chip *chip = irq_desc_get_chip(desc);
737 chained_irq_enter(chip, desc);
739 bank = irq_get_handler_data(irq);
740 isr_reg = bank->base + bank->regs->irqstatus;
741 pm_runtime_get_sync(bank->dev);
743 if (WARN_ON(!isr_reg))
747 u32 isr_saved, level_mask = 0;
750 enabled = _get_gpio_irqbank_mask(bank);
751 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
753 if (bank->level_mask)
754 level_mask = bank->level_mask & enabled;
756 /* clear edge sensitive interrupts before handler(s) are
757 called so that we don't miss any interrupt occurred while
759 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
760 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
761 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
763 /* if there is only edge sensitive GPIO pin interrupts
764 configured, we could unmask GPIO bank interrupt immediately */
765 if (!level_mask && !unmasked) {
767 chained_irq_exit(chip, desc);
778 * Some chips can't respond to both rising and falling
779 * at the same time. If this irq was requested with
780 * both flags, we need to flip the ICR data for the IRQ
781 * to respond to the IRQ for the opposite direction.
782 * This will be indicated in the bank toggle_mask.
784 if (bank->toggle_mask & (1 << bit))
785 _toggle_gpio_edge_triggering(bank, bit);
787 generic_handle_irq(irq_find_mapping(bank->domain, bit));
790 /* if bank has any level sensitive GPIO pin interrupt
791 configured, we must unmask the bank interrupt only after
792 handler(s) are executed in order to avoid spurious bank
796 chained_irq_exit(chip, desc);
797 pm_runtime_put(bank->dev);
800 static void gpio_irq_shutdown(struct irq_data *d)
802 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
803 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
805 unsigned offset = GPIO_INDEX(bank, gpio);
807 spin_lock_irqsave(&bank->lock, flags);
808 gpio_unlock_as_irq(&bank->chip, offset);
809 bank->irq_usage &= ~(1 << offset);
810 _disable_gpio_module(bank, offset);
811 _reset_gpio(bank, gpio);
812 spin_unlock_irqrestore(&bank->lock, flags);
815 * If this is the last IRQ to be freed in the bank,
816 * disable the bank module.
818 if (!BANK_USED(bank))
819 pm_runtime_put(bank->dev);
822 static void gpio_ack_irq(struct irq_data *d)
824 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
825 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
827 _clear_gpio_irqstatus(bank, gpio);
830 static void gpio_mask_irq(struct irq_data *d)
832 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
833 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
836 spin_lock_irqsave(&bank->lock, flags);
837 _set_gpio_irqenable(bank, gpio, 0);
838 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
839 spin_unlock_irqrestore(&bank->lock, flags);
842 static void gpio_unmask_irq(struct irq_data *d)
844 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
845 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
846 unsigned int irq_mask = GPIO_BIT(bank, gpio);
847 u32 trigger = irqd_get_trigger_type(d);
850 spin_lock_irqsave(&bank->lock, flags);
852 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
854 /* For level-triggered GPIOs, the clearing must be done after
855 * the HW source is cleared, thus after the handler has run */
856 if (bank->level_mask & irq_mask) {
857 _set_gpio_irqenable(bank, gpio, 0);
858 _clear_gpio_irqstatus(bank, gpio);
861 _set_gpio_irqenable(bank, gpio, 1);
862 spin_unlock_irqrestore(&bank->lock, flags);
865 static struct irq_chip gpio_irq_chip = {
867 .irq_shutdown = gpio_irq_shutdown,
868 .irq_ack = gpio_ack_irq,
869 .irq_mask = gpio_mask_irq,
870 .irq_unmask = gpio_unmask_irq,
871 .irq_set_type = gpio_irq_type,
872 .irq_set_wake = gpio_wake_enable,
875 /*---------------------------------------------------------------------*/
877 static int omap_mpuio_suspend_noirq(struct device *dev)
879 struct platform_device *pdev = to_platform_device(dev);
880 struct gpio_bank *bank = platform_get_drvdata(pdev);
881 void __iomem *mask_reg = bank->base +
882 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
885 spin_lock_irqsave(&bank->lock, flags);
886 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
887 spin_unlock_irqrestore(&bank->lock, flags);
892 static int omap_mpuio_resume_noirq(struct device *dev)
894 struct platform_device *pdev = to_platform_device(dev);
895 struct gpio_bank *bank = platform_get_drvdata(pdev);
896 void __iomem *mask_reg = bank->base +
897 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
900 spin_lock_irqsave(&bank->lock, flags);
901 writel_relaxed(bank->context.wake_en, mask_reg);
902 spin_unlock_irqrestore(&bank->lock, flags);
907 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
908 .suspend_noirq = omap_mpuio_suspend_noirq,
909 .resume_noirq = omap_mpuio_resume_noirq,
912 /* use platform_driver for this. */
913 static struct platform_driver omap_mpuio_driver = {
916 .pm = &omap_mpuio_dev_pm_ops,
920 static struct platform_device omap_mpuio_device = {
924 .driver = &omap_mpuio_driver.driver,
926 /* could list the /proc/iomem resources */
929 static inline void mpuio_init(struct gpio_bank *bank)
931 platform_set_drvdata(&omap_mpuio_device, bank);
933 if (platform_driver_register(&omap_mpuio_driver) == 0)
934 (void) platform_device_register(&omap_mpuio_device);
937 /*---------------------------------------------------------------------*/
939 static int gpio_input(struct gpio_chip *chip, unsigned offset)
941 struct gpio_bank *bank;
944 bank = container_of(chip, struct gpio_bank, chip);
945 spin_lock_irqsave(&bank->lock, flags);
946 _set_gpio_direction(bank, offset, 1);
947 spin_unlock_irqrestore(&bank->lock, flags);
951 static int gpio_get(struct gpio_chip *chip, unsigned offset)
953 struct gpio_bank *bank;
956 bank = container_of(chip, struct gpio_bank, chip);
957 mask = (1 << offset);
959 if (gpio_is_input(bank, mask))
960 return _get_gpio_datain(bank, offset);
962 return _get_gpio_dataout(bank, offset);
965 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
967 struct gpio_bank *bank;
970 bank = container_of(chip, struct gpio_bank, chip);
971 spin_lock_irqsave(&bank->lock, flags);
972 bank->set_dataout(bank, offset, value);
973 _set_gpio_direction(bank, offset, 0);
974 spin_unlock_irqrestore(&bank->lock, flags);
978 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
981 struct gpio_bank *bank;
984 bank = container_of(chip, struct gpio_bank, chip);
986 spin_lock_irqsave(&bank->lock, flags);
987 _set_gpio_debounce(bank, offset, debounce);
988 spin_unlock_irqrestore(&bank->lock, flags);
993 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
995 struct gpio_bank *bank;
998 bank = container_of(chip, struct gpio_bank, chip);
999 spin_lock_irqsave(&bank->lock, flags);
1000 bank->set_dataout(bank, offset, value);
1001 spin_unlock_irqrestore(&bank->lock, flags);
1004 /*---------------------------------------------------------------------*/
1006 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1011 if (called || bank->regs->revision == USHRT_MAX)
1014 rev = readw_relaxed(bank->base + bank->regs->revision);
1015 pr_info("OMAP GPIO hardware version %d.%d\n",
1016 (rev >> 4) & 0x0f, rev & 0x0f);
1021 /* This lock class tells lockdep that GPIO irqs are in a different
1022 * category than their parents, so it won't report false recursion.
1024 static struct lock_class_key gpio_lock_class;
1026 static void omap_gpio_mod_init(struct gpio_bank *bank)
1028 void __iomem *base = bank->base;
1031 if (bank->width == 16)
1034 if (bank->is_mpuio) {
1035 writel_relaxed(l, bank->base + bank->regs->irqenable);
1039 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
1040 _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
1041 if (bank->regs->debounce_en)
1042 writel_relaxed(0, base + bank->regs->debounce_en);
1044 /* Save OE default value (0xffffffff) in the context */
1045 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1046 /* Initialize interface clk ungated, module enabled */
1047 if (bank->regs->ctrl)
1048 writel_relaxed(0, base + bank->regs->ctrl);
1050 bank->dbck = clk_get(bank->dev, "dbclk");
1051 if (IS_ERR(bank->dbck))
1052 dev_err(bank->dev, "Could not get gpio dbck\n");
1056 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1059 struct irq_chip_generic *gc;
1060 struct irq_chip_type *ct;
1062 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1065 dev_err(bank->dev, "Memory alloc failed for gc\n");
1069 ct = gc->chip_types;
1071 /* NOTE: No ack required, reading IRQ status clears it. */
1072 ct->chip.irq_mask = irq_gc_mask_set_bit;
1073 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1074 ct->chip.irq_set_type = gpio_irq_type;
1076 if (bank->regs->wkup_en)
1077 ct->chip.irq_set_wake = gpio_wake_enable;
1079 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1080 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1081 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1084 static void omap_gpio_chip_init(struct gpio_bank *bank)
1090 * REVISIT eventually switch from OMAP-specific gpio structs
1091 * over to the generic ones
1093 bank->chip.request = omap_gpio_request;
1094 bank->chip.free = omap_gpio_free;
1095 bank->chip.direction_input = gpio_input;
1096 bank->chip.get = gpio_get;
1097 bank->chip.direction_output = gpio_output;
1098 bank->chip.set_debounce = gpio_debounce;
1099 bank->chip.set = gpio_set;
1100 bank->chip.to_irq = omap_gpio_to_irq;
1101 if (bank->is_mpuio) {
1102 bank->chip.label = "mpuio";
1103 if (bank->regs->wkup_en)
1104 bank->chip.dev = &omap_mpuio_device.dev;
1105 bank->chip.base = OMAP_MPUIO(0);
1107 bank->chip.label = "gpio";
1108 bank->chip.base = gpio;
1109 gpio += bank->width;
1111 bank->chip.ngpio = bank->width;
1113 gpiochip_add(&bank->chip);
1115 for (j = 0; j < bank->width; j++) {
1116 int irq = irq_create_mapping(bank->domain, j);
1117 irq_set_lockdep_class(irq, &gpio_lock_class);
1118 irq_set_chip_data(irq, bank);
1119 if (bank->is_mpuio) {
1120 omap_mpuio_alloc_gc(bank, irq, bank->width);
1122 irq_set_chip_and_handler(irq, &gpio_irq_chip,
1124 set_irq_flags(irq, IRQF_VALID);
1127 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1128 irq_set_handler_data(bank->irq, bank);
1131 static const struct of_device_id omap_gpio_match[];
1133 static int omap_gpio_probe(struct platform_device *pdev)
1135 struct device *dev = &pdev->dev;
1136 struct device_node *node = dev->of_node;
1137 const struct of_device_id *match;
1138 const struct omap_gpio_platform_data *pdata;
1139 struct resource *res;
1140 struct gpio_bank *bank;
1143 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1145 pdata = match ? match->data : dev_get_platdata(dev);
1149 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1151 dev_err(dev, "Memory alloc failed\n");
1155 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1156 if (unlikely(!res)) {
1157 dev_err(dev, "Invalid IRQ resource\n");
1161 bank->irq = res->start;
1163 bank->dbck_flag = pdata->dbck_flag;
1164 bank->stride = pdata->bank_stride;
1165 bank->width = pdata->bank_width;
1166 bank->is_mpuio = pdata->is_mpuio;
1167 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1168 bank->regs = pdata->regs;
1169 #ifdef CONFIG_OF_GPIO
1170 bank->chip.of_node = of_node_get(node);
1173 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1174 bank->loses_context = true;
1176 bank->loses_context = pdata->loses_context;
1178 if (bank->loses_context)
1179 bank->get_context_loss_count =
1180 pdata->get_context_loss_count;
1183 #ifdef CONFIG_ARCH_OMAP1
1185 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1186 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1188 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1190 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1194 bank->domain = irq_domain_add_simple(node, bank->width, irq_base,
1195 &irq_domain_simple_ops, NULL);
1196 if (!bank->domain) {
1197 dev_err(dev, "Couldn't register an IRQ domain\n");
1201 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1202 bank->set_dataout = _set_gpio_dataout_reg;
1204 bank->set_dataout = _set_gpio_dataout_mask;
1206 spin_lock_init(&bank->lock);
1208 /* Static mapping, never released */
1209 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1210 bank->base = devm_ioremap_resource(dev, res);
1211 if (IS_ERR(bank->base)) {
1212 irq_domain_remove(bank->domain);
1213 return PTR_ERR(bank->base);
1216 platform_set_drvdata(pdev, bank);
1218 pm_runtime_enable(bank->dev);
1219 pm_runtime_irq_safe(bank->dev);
1220 pm_runtime_get_sync(bank->dev);
1225 omap_gpio_mod_init(bank);
1226 omap_gpio_chip_init(bank);
1227 omap_gpio_show_rev(bank);
1229 pm_runtime_put(bank->dev);
1231 list_add_tail(&bank->node, &omap_gpio_list);
1236 #ifdef CONFIG_ARCH_OMAP2PLUS
1238 #if defined(CONFIG_PM_RUNTIME)
1239 static void omap_gpio_restore_context(struct gpio_bank *bank);
1241 static int omap_gpio_runtime_suspend(struct device *dev)
1243 struct platform_device *pdev = to_platform_device(dev);
1244 struct gpio_bank *bank = platform_get_drvdata(pdev);
1246 unsigned long flags;
1247 u32 wake_low, wake_hi;
1249 spin_lock_irqsave(&bank->lock, flags);
1252 * Only edges can generate a wakeup event to the PRCM.
1254 * Therefore, ensure any wake-up capable GPIOs have
1255 * edge-detection enabled before going idle to ensure a wakeup
1256 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1259 * The normal values will be restored upon ->runtime_resume()
1260 * by writing back the values saved in bank->context.
1262 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1264 writel_relaxed(wake_low | bank->context.fallingdetect,
1265 bank->base + bank->regs->fallingdetect);
1266 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1268 writel_relaxed(wake_hi | bank->context.risingdetect,
1269 bank->base + bank->regs->risingdetect);
1271 if (!bank->enabled_non_wakeup_gpios)
1272 goto update_gpio_context_count;
1274 if (bank->power_mode != OFF_MODE) {
1275 bank->power_mode = 0;
1276 goto update_gpio_context_count;
1279 * If going to OFF, remove triggering for all
1280 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1281 * generated. See OMAP2420 Errata item 1.101.
1283 bank->saved_datain = readl_relaxed(bank->base +
1284 bank->regs->datain);
1285 l1 = bank->context.fallingdetect;
1286 l2 = bank->context.risingdetect;
1288 l1 &= ~bank->enabled_non_wakeup_gpios;
1289 l2 &= ~bank->enabled_non_wakeup_gpios;
1291 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1292 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1294 bank->workaround_enabled = true;
1296 update_gpio_context_count:
1297 if (bank->get_context_loss_count)
1298 bank->context_loss_count =
1299 bank->get_context_loss_count(bank->dev);
1301 _gpio_dbck_disable(bank);
1302 spin_unlock_irqrestore(&bank->lock, flags);
1307 static void omap_gpio_init_context(struct gpio_bank *p);
1309 static int omap_gpio_runtime_resume(struct device *dev)
1311 struct platform_device *pdev = to_platform_device(dev);
1312 struct gpio_bank *bank = platform_get_drvdata(pdev);
1313 u32 l = 0, gen, gen0, gen1;
1314 unsigned long flags;
1317 spin_lock_irqsave(&bank->lock, flags);
1320 * On the first resume during the probe, the context has not
1321 * been initialised and so initialise it now. Also initialise
1322 * the context loss count.
1324 if (bank->loses_context && !bank->context_valid) {
1325 omap_gpio_init_context(bank);
1327 if (bank->get_context_loss_count)
1328 bank->context_loss_count =
1329 bank->get_context_loss_count(bank->dev);
1332 _gpio_dbck_enable(bank);
1335 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1336 * GPIOs were set to edge trigger also in order to be able to
1337 * generate a PRCM wakeup. Here we restore the
1338 * pre-runtime_suspend() values for edge triggering.
1340 writel_relaxed(bank->context.fallingdetect,
1341 bank->base + bank->regs->fallingdetect);
1342 writel_relaxed(bank->context.risingdetect,
1343 bank->base + bank->regs->risingdetect);
1345 if (bank->loses_context) {
1346 if (!bank->get_context_loss_count) {
1347 omap_gpio_restore_context(bank);
1349 c = bank->get_context_loss_count(bank->dev);
1350 if (c != bank->context_loss_count) {
1351 omap_gpio_restore_context(bank);
1353 spin_unlock_irqrestore(&bank->lock, flags);
1359 if (!bank->workaround_enabled) {
1360 spin_unlock_irqrestore(&bank->lock, flags);
1364 l = readl_relaxed(bank->base + bank->regs->datain);
1367 * Check if any of the non-wakeup interrupt GPIOs have changed
1368 * state. If so, generate an IRQ by software. This is
1369 * horribly racy, but it's the best we can do to work around
1372 l ^= bank->saved_datain;
1373 l &= bank->enabled_non_wakeup_gpios;
1376 * No need to generate IRQs for the rising edge for gpio IRQs
1377 * configured with falling edge only; and vice versa.
1379 gen0 = l & bank->context.fallingdetect;
1380 gen0 &= bank->saved_datain;
1382 gen1 = l & bank->context.risingdetect;
1383 gen1 &= ~(bank->saved_datain);
1385 /* FIXME: Consider GPIO IRQs with level detections properly! */
1386 gen = l & (~(bank->context.fallingdetect) &
1387 ~(bank->context.risingdetect));
1388 /* Consider all GPIO IRQs needed to be updated */
1394 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1395 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1397 if (!bank->regs->irqstatus_raw0) {
1398 writel_relaxed(old0 | gen, bank->base +
1399 bank->regs->leveldetect0);
1400 writel_relaxed(old1 | gen, bank->base +
1401 bank->regs->leveldetect1);
1404 if (bank->regs->irqstatus_raw0) {
1405 writel_relaxed(old0 | l, bank->base +
1406 bank->regs->leveldetect0);
1407 writel_relaxed(old1 | l, bank->base +
1408 bank->regs->leveldetect1);
1410 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1411 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1414 bank->workaround_enabled = false;
1415 spin_unlock_irqrestore(&bank->lock, flags);
1419 #endif /* CONFIG_PM_RUNTIME */
1421 void omap2_gpio_prepare_for_idle(int pwr_mode)
1423 struct gpio_bank *bank;
1425 list_for_each_entry(bank, &omap_gpio_list, node) {
1426 if (!BANK_USED(bank) || !bank->loses_context)
1429 bank->power_mode = pwr_mode;
1431 pm_runtime_put_sync_suspend(bank->dev);
1435 void omap2_gpio_resume_after_idle(void)
1437 struct gpio_bank *bank;
1439 list_for_each_entry(bank, &omap_gpio_list, node) {
1440 if (!BANK_USED(bank) || !bank->loses_context)
1443 pm_runtime_get_sync(bank->dev);
1447 #if defined(CONFIG_PM_RUNTIME)
1448 static void omap_gpio_init_context(struct gpio_bank *p)
1450 struct omap_gpio_reg_offs *regs = p->regs;
1451 void __iomem *base = p->base;
1453 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1454 p->context.oe = readl_relaxed(base + regs->direction);
1455 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1456 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1457 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1458 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1459 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1460 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1461 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1463 if (regs->set_dataout && p->regs->clr_dataout)
1464 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1466 p->context.dataout = readl_relaxed(base + regs->dataout);
1468 p->context_valid = true;
1471 static void omap_gpio_restore_context(struct gpio_bank *bank)
1473 writel_relaxed(bank->context.wake_en,
1474 bank->base + bank->regs->wkup_en);
1475 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1476 writel_relaxed(bank->context.leveldetect0,
1477 bank->base + bank->regs->leveldetect0);
1478 writel_relaxed(bank->context.leveldetect1,
1479 bank->base + bank->regs->leveldetect1);
1480 writel_relaxed(bank->context.risingdetect,
1481 bank->base + bank->regs->risingdetect);
1482 writel_relaxed(bank->context.fallingdetect,
1483 bank->base + bank->regs->fallingdetect);
1484 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1485 writel_relaxed(bank->context.dataout,
1486 bank->base + bank->regs->set_dataout);
1488 writel_relaxed(bank->context.dataout,
1489 bank->base + bank->regs->dataout);
1490 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1492 if (bank->dbck_enable_mask) {
1493 writel_relaxed(bank->context.debounce, bank->base +
1494 bank->regs->debounce);
1495 writel_relaxed(bank->context.debounce_en,
1496 bank->base + bank->regs->debounce_en);
1499 writel_relaxed(bank->context.irqenable1,
1500 bank->base + bank->regs->irqenable);
1501 writel_relaxed(bank->context.irqenable2,
1502 bank->base + bank->regs->irqenable2);
1504 #endif /* CONFIG_PM_RUNTIME */
1506 #define omap_gpio_runtime_suspend NULL
1507 #define omap_gpio_runtime_resume NULL
1508 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1511 static const struct dev_pm_ops gpio_pm_ops = {
1512 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1516 #if defined(CONFIG_OF)
1517 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1518 .revision = OMAP24XX_GPIO_REVISION,
1519 .direction = OMAP24XX_GPIO_OE,
1520 .datain = OMAP24XX_GPIO_DATAIN,
1521 .dataout = OMAP24XX_GPIO_DATAOUT,
1522 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1523 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1524 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1525 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1526 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1527 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1528 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1529 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1530 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1531 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1532 .ctrl = OMAP24XX_GPIO_CTRL,
1533 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1534 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1535 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1536 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1537 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1540 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1541 .revision = OMAP4_GPIO_REVISION,
1542 .direction = OMAP4_GPIO_OE,
1543 .datain = OMAP4_GPIO_DATAIN,
1544 .dataout = OMAP4_GPIO_DATAOUT,
1545 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1546 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1547 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1548 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1549 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1550 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1551 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1552 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1553 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1554 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1555 .ctrl = OMAP4_GPIO_CTRL,
1556 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1557 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1558 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1559 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1560 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1563 static const struct omap_gpio_platform_data omap2_pdata = {
1564 .regs = &omap2_gpio_regs,
1569 static const struct omap_gpio_platform_data omap3_pdata = {
1570 .regs = &omap2_gpio_regs,
1575 static const struct omap_gpio_platform_data omap4_pdata = {
1576 .regs = &omap4_gpio_regs,
1581 static const struct of_device_id omap_gpio_match[] = {
1583 .compatible = "ti,omap4-gpio",
1584 .data = &omap4_pdata,
1587 .compatible = "ti,omap3-gpio",
1588 .data = &omap3_pdata,
1591 .compatible = "ti,omap2-gpio",
1592 .data = &omap2_pdata,
1596 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1599 static struct platform_driver omap_gpio_driver = {
1600 .probe = omap_gpio_probe,
1602 .name = "omap_gpio",
1604 .of_match_table = of_match_ptr(omap_gpio_match),
1609 * gpio driver register needs to be done before
1610 * machine_init functions access gpio APIs.
1611 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1613 static int __init omap_gpio_drv_reg(void)
1615 return platform_driver_register(&omap_gpio_driver);
1617 postcore_initcall(omap_gpio_drv_reg);