drivers/gpio/gpio-omap.c

   1 /*
   2  * Support functions for OMAP GPIO
   3  *
   4  * Copyright (C) 2003-2005 Nokia Corporation
   5  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   6  *
   7  * Copyright (C) 2009 Texas Instruments
   8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/pm.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/gpio.h>
  28 #include <linux/bitops.h>
  29 #include <linux/platform_data/gpio-omap.h>
  30
  31 #define OFF_MODE        1
  32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
  33
  34 static LIST_HEAD(omap_gpio_list);
  35
  36 struct gpio_regs {
  37         u32 irqenable1;
  38         u32 irqenable2;
  39         u32 wake_en;
  40         u32 ctrl;
  41         u32 oe;
  42         u32 leveldetect0;
  43         u32 leveldetect1;
  44         u32 risingdetect;
  45         u32 fallingdetect;
  46         u32 dataout;
  47         u32 debounce;
  48         u32 debounce_en;
  49 };
  50
  51 struct gpio_bank {
  52         struct list_head node;
  53         void __iomem *base;
  54         int irq;
  55         u32 non_wakeup_gpios;
  56         u32 enabled_non_wakeup_gpios;
  57         struct gpio_regs context;
  58         u32 saved_datain;
  59         u32 level_mask;
  60         u32 toggle_mask;
  61         raw_spinlock_t lock;
  62         raw_spinlock_t wa_lock;
  63         struct gpio_chip chip;
  64         struct clk *dbck;
  65         u32 mod_usage;
  66         u32 irq_usage;
  67         u32 dbck_enable_mask;
  68         bool dbck_enabled;
  69         bool is_mpuio;
  70         bool dbck_flag;
  71         bool loses_context;
  72         bool context_valid;
  73         int stride;
  74         u32 width;
  75         int context_loss_count;
  76         int power_mode;
  77         bool workaround_enabled;
  78
  79         void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
  80         int (*get_context_loss_count)(struct device *dev);
  81
  82         struct omap_gpio_reg_offs *regs;
  83 };
  84
  85 #define GPIO_MOD_CTRL_BIT       BIT(0)
  86
  87 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
  88 #define LINE_USED(line, offset) (line & (BIT(offset)))
  89
  90 static void omap_gpio_unmask_irq(struct irq_data *d);
  91
  92 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
  93 {
  94         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  95         return gpiochip_get_data(chip);
  96 }
  97
  98 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
  99                                     int is_input)
 100 {
 101         void __iomem *reg = bank->base;
 102         u32 l;
 103
 104         reg += bank->regs->direction;
 105         l = readl_relaxed(reg);
 106         if (is_input)
 107                 l |= BIT(gpio);
 108         else
 109                 l &= ~(BIT(gpio));
 110         writel_relaxed(l, reg);
 111         bank->context.oe = l;
 112 }
 113
 114
 115 /* set data out value using dedicate set/clear register */
 116 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
 117                                       int enable)
 118 {
 119         void __iomem *reg = bank->base;
 120         u32 l = BIT(offset);
 121
 122         if (enable) {
 123                 reg += bank->regs->set_dataout;
 124                 bank->context.dataout |= l;
 125         } else {
 126                 reg += bank->regs->clr_dataout;
 127                 bank->context.dataout &= ~l;
 128         }
 129
 130         writel_relaxed(l, reg);
 131 }
 132
 133 /* set data out value using mask register */
 134 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
 135                                        int enable)
 136 {
 137         void __iomem *reg = bank->base + bank->regs->dataout;
 138         u32 gpio_bit = BIT(offset);
 139         u32 l;
 140
 141         l = readl_relaxed(reg);
 142         if (enable)
 143                 l |= gpio_bit;
 144         else
 145                 l &= ~gpio_bit;
 146         writel_relaxed(l, reg);
 147         bank->context.dataout = l;
 148 }
 149
 150 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
 151 {
 152         void __iomem *reg = bank->base + bank->regs->datain;
 153
 154         return (readl_relaxed(reg) & (BIT(offset))) != 0;
 155 }
 156
 157 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
 158 {
 159         void __iomem *reg = bank->base + bank->regs->dataout;
 160
 161         return (readl_relaxed(reg) & (BIT(offset))) != 0;
 162 }
 163
 164 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
 165 {
 166         int l = readl_relaxed(base + reg);
 167
 168         if (set)
 169                 l |= mask;
 170         else
 171                 l &= ~mask;
 172
 173         writel_relaxed(l, base + reg);
 174 }
 175
 176 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
 177 {
 178         if (bank->dbck_enable_mask && !bank->dbck_enabled) {
 179                 clk_enable(bank->dbck);
 180                 bank->dbck_enabled = true;
 181
 182                 writel_relaxed(bank->dbck_enable_mask,
 183                              bank->base + bank->regs->debounce_en);
 184         }
 185 }
 186
 187 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
 188 {
 189         if (bank->dbck_enable_mask && bank->dbck_enabled) {
 190                 /*
 191                  * Disable debounce before cutting it's clock. If debounce is
 192                  * enabled but the clock is not, GPIO module seems to be unable
 193                  * to detect events and generate interrupts at least on OMAP3.
 194                  */
 195                 writel_relaxed(0, bank->base + bank->regs->debounce_en);
 196
 197                 clk_disable(bank->dbck);
 198                 bank->dbck_enabled = false;
 199         }
 200 }
 201
 202 /**
 203  * omap2_set_gpio_debounce - low level gpio debounce time
 204  * @bank: the gpio bank we're acting upon
 205  * @offset: the gpio number on this @bank
 206  * @debounce: debounce time to use
 207  *
 208  * OMAP's debounce time is in 31us steps
 209  *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
 210  * so we need to convert and round up to the closest unit.
 211  */
 212 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
 213                                     unsigned debounce)
 214 {
 215         void __iomem            *reg;
 216         u32                     val;
 217         u32                     l;
 218         bool                    enable = !!debounce;
 219
 220         if (!bank->dbck_flag)
 221                 return;
 222
 223         if (enable) {
 224                 debounce = DIV_ROUND_UP(debounce, 31) - 1;
 225                 debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
 226         }
 227
 228         l = BIT(offset);
 229
 230         clk_enable(bank->dbck);
 231         reg = bank->base + bank->regs->debounce;
 232         writel_relaxed(debounce, reg);
 233
 234         reg = bank->base + bank->regs->debounce_en;
 235         val = readl_relaxed(reg);
 236
 237         if (enable)
 238                 val |= l;
 239         else
 240                 val &= ~l;
 241         bank->dbck_enable_mask = val;
 242
 243         writel_relaxed(val, reg);
 244         clk_disable(bank->dbck);
 245         /*
 246          * Enable debounce clock per module.
 247          * This call is mandatory because in omap_gpio_request() when
 248          * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
 249          * runtime callbck fails to turn on dbck because dbck_enable_mask
 250          * used within _gpio_dbck_enable() is still not initialized at
 251          * that point. Therefore we have to enable dbck here.
 252          */
 253         omap_gpio_dbck_enable(bank);
 254         if (bank->dbck_enable_mask) {
 255                 bank->context.debounce = debounce;
 256                 bank->context.debounce_en = val;
 257         }
 258 }
 259
 260 /**
 261  * omap_clear_gpio_debounce - clear debounce settings for a gpio
 262  * @bank: the gpio bank we're acting upon
 263  * @offset: the gpio number on this @bank
 264  *
 265  * If a gpio is using debounce, then clear the debounce enable bit and if
 266  * this is the only gpio in this bank using debounce, then clear the debounce
 267  * time too. The debounce clock will also be disabled when calling this function
 268  * if this is the only gpio in the bank using debounce.
 269  */
 270 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
 271 {
 272         u32 gpio_bit = BIT(offset);
 273
 274         if (!bank->dbck_flag)
 275                 return;
 276
 277         if (!(bank->dbck_enable_mask & gpio_bit))
 278                 return;
 279
 280         bank->dbck_enable_mask &= ~gpio_bit;
 281         bank->context.debounce_en &= ~gpio_bit;
 282         writel_relaxed(bank->context.debounce_en,
 283                      bank->base + bank->regs->debounce_en);
 284
 285         if (!bank->dbck_enable_mask) {
 286                 bank->context.debounce = 0;
 287                 writel_relaxed(bank->context.debounce, bank->base +
 288                              bank->regs->debounce);
 289                 clk_disable(bank->dbck);
 290                 bank->dbck_enabled = false;
 291         }
 292 }
 293
 294 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
 295                                                 unsigned trigger)
 296 {
 297         void __iomem *base = bank->base;
 298         u32 gpio_bit = BIT(gpio);
 299
 300         omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
 301                       trigger & IRQ_TYPE_LEVEL_LOW);
 302         omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
 303                       trigger & IRQ_TYPE_LEVEL_HIGH);
 304         omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
 305                       trigger & IRQ_TYPE_EDGE_RISING);
 306         omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
 307                       trigger & IRQ_TYPE_EDGE_FALLING);
 308
 309         bank->context.leveldetect0 =
 310                         readl_relaxed(bank->base + bank->regs->leveldetect0);
 311         bank->context.leveldetect1 =
 312                         readl_relaxed(bank->base + bank->regs->leveldetect1);
 313         bank->context.risingdetect =
 314                         readl_relaxed(bank->base + bank->regs->risingdetect);
 315         bank->context.fallingdetect =
 316                         readl_relaxed(bank->base + bank->regs->fallingdetect);
 317
 318         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 319                 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
 320                 bank->context.wake_en =
 321                         readl_relaxed(bank->base + bank->regs->wkup_en);
 322         }
 323
 324         /* This part needs to be executed always for OMAP{34xx, 44xx} */
 325         if (!bank->regs->irqctrl) {
 326                 /* On omap24xx proceed only when valid GPIO bit is set */
 327                 if (bank->non_wakeup_gpios) {
 328                         if (!(bank->non_wakeup_gpios & gpio_bit))
 329                                 goto exit;
 330                 }
 331
 332                 /*
 333                  * Log the edge gpio and manually trigger the IRQ
 334                  * after resume if the input level changes
 335                  * to avoid irq lost during PER RET/OFF mode
 336                  * Applies for omap2 non-wakeup gpio and all omap3 gpios
 337                  */
 338                 if (trigger & IRQ_TYPE_EDGE_BOTH)
 339                         bank->enabled_non_wakeup_gpios |= gpio_bit;
 340                 else
 341                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 342         }
 343
 344 exit:
 345         bank->level_mask =
 346                 readl_relaxed(bank->base + bank->regs->leveldetect0) |
 347                 readl_relaxed(bank->base + bank->regs->leveldetect1);
 348 }
 349
 350 #ifdef CONFIG_ARCH_OMAP1
 351 /*
 352  * This only applies to chips that can't do both rising and falling edge
 353  * detection at once.  For all other chips, this function is a noop.
 354  */
 355 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 356 {
 357         void __iomem *reg = bank->base;
 358         u32 l = 0;
 359
 360         if (!bank->regs->irqctrl)
 361                 return;
 362
 363         reg += bank->regs->irqctrl;
 364
 365         l = readl_relaxed(reg);
 366         if ((l >> gpio) & 1)
 367                 l &= ~(BIT(gpio));
 368         else
 369                 l |= BIT(gpio);
 370
 371         writel_relaxed(l, reg);
 372 }
 373 #else
 374 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 375 #endif
 376
 377 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
 378                                     unsigned trigger)
 379 {
 380         void __iomem *reg = bank->base;
 381         void __iomem *base = bank->base;
 382         u32 l = 0;
 383
 384         if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
 385                 omap_set_gpio_trigger(bank, gpio, trigger);
 386         } else if (bank->regs->irqctrl) {
 387                 reg += bank->regs->irqctrl;
 388
 389                 l = readl_relaxed(reg);
 390                 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
 391                         bank->toggle_mask |= BIT(gpio);
 392                 if (trigger & IRQ_TYPE_EDGE_RISING)
 393                         l |= BIT(gpio);
 394                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 395                         l &= ~(BIT(gpio));
 396                 else
 397                         return -EINVAL;
 398
 399                 writel_relaxed(l, reg);
 400         } else if (bank->regs->edgectrl1) {
 401                 if (gpio & 0x08)
 402                         reg += bank->regs->edgectrl2;
 403                 else
 404                         reg += bank->regs->edgectrl1;
 405
 406                 gpio &= 0x07;
 407                 l = readl_relaxed(reg);
 408                 l &= ~(3 << (gpio << 1));
 409                 if (trigger & IRQ_TYPE_EDGE_RISING)
 410                         l |= 2 << (gpio << 1);
 411                 if (trigger & IRQ_TYPE_EDGE_FALLING)
 412                         l |= BIT(gpio << 1);
 413
 414                 /* Enable wake-up during idle for dynamic tick */
 415                 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
 416                 bank->context.wake_en =
 417                         readl_relaxed(bank->base + bank->regs->wkup_en);
 418                 writel_relaxed(l, reg);
 419         }
 420         return 0;
 421 }
 422
 423 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
 424 {
 425         if (bank->regs->pinctrl) {
 426                 void __iomem *reg = bank->base + bank->regs->pinctrl;
 427
 428                 /* Claim the pin for MPU */
 429                 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
 430         }
 431
 432         if (bank->regs->ctrl && !BANK_USED(bank)) {
 433                 void __iomem *reg = bank->base + bank->regs->ctrl;
 434                 u32 ctrl;
 435
 436                 ctrl = readl_relaxed(reg);
 437                 /* Module is enabled, clocks are not gated */
 438                 ctrl &= ~GPIO_MOD_CTRL_BIT;
 439                 writel_relaxed(ctrl, reg);
 440                 bank->context.ctrl = ctrl;
 441         }
 442 }
 443
 444 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
 445 {
 446         void __iomem *base = bank->base;
 447
 448         if (bank->regs->wkup_en &&
 449             !LINE_USED(bank->mod_usage, offset) &&
 450             !LINE_USED(bank->irq_usage, offset)) {
 451                 /* Disable wake-up during idle for dynamic tick */
 452                 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
 453                 bank->context.wake_en =
 454                         readl_relaxed(bank->base + bank->regs->wkup_en);
 455         }
 456
 457         if (bank->regs->ctrl && !BANK_USED(bank)) {
 458                 void __iomem *reg = bank->base + bank->regs->ctrl;
 459                 u32 ctrl;
 460
 461                 ctrl = readl_relaxed(reg);
 462                 /* Module is disabled, clocks are gated */
 463                 ctrl |= GPIO_MOD_CTRL_BIT;
 464                 writel_relaxed(ctrl, reg);
 465                 bank->context.ctrl = ctrl;
 466         }
 467 }
 468
 469 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
 470 {
 471         void __iomem *reg = bank->base + bank->regs->direction;
 472
 473         return readl_relaxed(reg) & BIT(offset);
 474 }
 475
 476 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
 477 {
 478         if (!LINE_USED(bank->mod_usage, offset)) {
 479                 omap_enable_gpio_module(bank, offset);
 480                 omap_set_gpio_direction(bank, offset, 1);
 481         }
 482         bank->irq_usage |= BIT(offset);
 483 }
 484
 485 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
 486 {
 487         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 488         int retval;
 489         unsigned long flags;
 490         unsigned offset = d->hwirq;
 491
 492         if (type & ~IRQ_TYPE_SENSE_MASK)
 493                 return -EINVAL;
 494
 495         if (!bank->regs->leveldetect0 &&
 496                 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 497                 return -EINVAL;
 498
 499         raw_spin_lock_irqsave(&bank->lock, flags);
 500         retval = omap_set_gpio_triggering(bank, offset, type);
 501         if (retval) {
 502                 raw_spin_unlock_irqrestore(&bank->lock, flags);
 503                 goto error;
 504         }
 505         omap_gpio_init_irq(bank, offset);
 506         if (!omap_gpio_is_input(bank, offset)) {
 507                 raw_spin_unlock_irqrestore(&bank->lock, flags);
 508                 retval = -EINVAL;
 509                 goto error;
 510         }
 511         raw_spin_unlock_irqrestore(&bank->lock, flags);
 512
 513         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 514                 irq_set_handler_locked(d, handle_level_irq);
 515         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 516                 irq_set_handler_locked(d, handle_edge_irq);
 517
 518         return 0;
 519
 520 error:
 521         return retval;
 522 }
 523
 524 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 525 {
 526         void __iomem *reg = bank->base;
 527
 528         reg += bank->regs->irqstatus;
 529         writel_relaxed(gpio_mask, reg);
 530
 531         /* Workaround for clearing DSP GPIO interrupts to allow retention */
 532         if (bank->regs->irqstatus2) {
 533                 reg = bank->base + bank->regs->irqstatus2;
 534                 writel_relaxed(gpio_mask, reg);
 535         }
 536
 537         /* Flush posted write for the irq status to avoid spurious interrupts */
 538         readl_relaxed(reg);
 539 }
 540
 541 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
 542                                              unsigned offset)
 543 {
 544         omap_clear_gpio_irqbank(bank, BIT(offset));
 545 }
 546
 547 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
 548 {
 549         void __iomem *reg = bank->base;
 550         u32 l;
 551         u32 mask = (BIT(bank->width)) - 1;
 552
 553         reg += bank->regs->irqenable;
 554         l = readl_relaxed(reg);
 555         if (bank->regs->irqenable_inv)
 556                 l = ~l;
 557         l &= mask;
 558         return l;
 559 }
 560
 561 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 562 {
 563         void __iomem *reg = bank->base;
 564         u32 l;
 565
 566         if (bank->regs->set_irqenable) {
 567                 reg += bank->regs->set_irqenable;
 568                 l = gpio_mask;
 569                 bank->context.irqenable1 |= gpio_mask;
 570         } else {
 571                 reg += bank->regs->irqenable;
 572                 l = readl_relaxed(reg);
 573                 if (bank->regs->irqenable_inv)
 574                         l &= ~gpio_mask;
 575                 else
 576                         l |= gpio_mask;
 577                 bank->context.irqenable1 = l;
 578         }
 579
 580         writel_relaxed(l, reg);
 581 }
 582
 583 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 584 {
 585         void __iomem *reg = bank->base;
 586         u32 l;
 587
 588         if (bank->regs->clr_irqenable) {
 589                 reg += bank->regs->clr_irqenable;
 590                 l = gpio_mask;
 591                 bank->context.irqenable1 &= ~gpio_mask;
 592         } else {
 593                 reg += bank->regs->irqenable;
 594                 l = readl_relaxed(reg);
 595                 if (bank->regs->irqenable_inv)
 596                         l |= gpio_mask;
 597                 else
 598                         l &= ~gpio_mask;
 599                 bank->context.irqenable1 = l;
 600         }
 601
 602         writel_relaxed(l, reg);
 603 }
 604
 605 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
 606                                            unsigned offset, int enable)
 607 {
 608         if (enable)
 609                 omap_enable_gpio_irqbank(bank, BIT(offset));
 610         else
 611                 omap_disable_gpio_irqbank(bank, BIT(offset));
 612 }
 613
 614 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
 615 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 616 {
 617         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 618
 619         return irq_set_irq_wake(bank->irq, enable);
 620 }
 621
 622 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 623 {
 624         struct gpio_bank *bank = gpiochip_get_data(chip);
 625         unsigned long flags;
 626
 627         /*
 628          * If this is the first gpio_request for the bank,
 629          * enable the bank module.
 630          */
 631         if (!BANK_USED(bank))
 632                 pm_runtime_get_sync(chip->parent);
 633
 634         raw_spin_lock_irqsave(&bank->lock, flags);
 635         omap_enable_gpio_module(bank, offset);
 636         bank->mod_usage |= BIT(offset);
 637         raw_spin_unlock_irqrestore(&bank->lock, flags);
 638
 639         return 0;
 640 }
 641
 642 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 643 {
 644         struct gpio_bank *bank = gpiochip_get_data(chip);
 645         unsigned long flags;
 646
 647         raw_spin_lock_irqsave(&bank->lock, flags);
 648         bank->mod_usage &= ~(BIT(offset));
 649         if (!LINE_USED(bank->irq_usage, offset)) {
 650                 omap_set_gpio_direction(bank, offset, 1);
 651                 omap_clear_gpio_debounce(bank, offset);
 652         }
 653         omap_disable_gpio_module(bank, offset);
 654         raw_spin_unlock_irqrestore(&bank->lock, flags);
 655
 656         /*
 657          * If this is the last gpio to be freed in the bank,
 658          * disable the bank module.
 659          */
 660         if (!BANK_USED(bank))
 661                 pm_runtime_put(chip->parent);
 662 }
 663
 664 /*
 665  * We need to unmask the GPIO bank interrupt as soon as possible to
 666  * avoid missing GPIO interrupts for other lines in the bank.
 667  * Then we need to mask-read-clear-unmask the triggered GPIO lines
 668  * in the bank to avoid missing nested interrupts for a GPIO line.
 669  * If we wait to unmask individual GPIO lines in the bank after the
 670  * line's interrupt handler has been run, we may miss some nested
 671  * interrupts.
 672  */
 673 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
 674 {
 675         void __iomem *isr_reg = NULL;
 676         u32 isr;
 677         unsigned int bit;
 678         struct gpio_bank *bank = gpiobank;
 679         unsigned long wa_lock_flags;
 680         unsigned long lock_flags;
 681
 682         isr_reg = bank->base + bank->regs->irqstatus;
 683         if (WARN_ON(!isr_reg))
 684                 goto exit;
 685
 686         pm_runtime_get_sync(bank->chip.parent);
 687
 688         while (1) {
 689                 u32 isr_saved, level_mask = 0;
 690                 u32 enabled;
 691
 692                 raw_spin_lock_irqsave(&bank->lock, lock_flags);
 693
 694                 enabled = omap_get_gpio_irqbank_mask(bank);
 695                 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
 696
 697                 if (bank->level_mask)
 698                         level_mask = bank->level_mask & enabled;
 699
 700                 /* clear edge sensitive interrupts before handler(s) are
 701                 called so that we don't miss any interrupt occurred while
 702                 executing them */
 703                 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
 704                 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
 705                 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
 706
 707                 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 708
 709                 if (!isr)
 710                         break;
 711
 712                 while (isr) {
 713                         bit = __ffs(isr);
 714                         isr &= ~(BIT(bit));
 715
 716                         raw_spin_lock_irqsave(&bank->lock, lock_flags);
 717                         /*
 718                          * Some chips can't respond to both rising and falling
 719                          * at the same time.  If this irq was requested with
 720                          * both flags, we need to flip the ICR data for the IRQ
 721                          * to respond to the IRQ for the opposite direction.
 722                          * This will be indicated in the bank toggle_mask.
 723                          */
 724                         if (bank->toggle_mask & (BIT(bit)))
 725                                 omap_toggle_gpio_edge_triggering(bank, bit);
 726
 727                         raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 728
 729                         raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
 730
 731                         generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
 732                                                             bit));
 733
 734                         raw_spin_unlock_irqrestore(&bank->wa_lock,
 735                                                    wa_lock_flags);
 736                 }
 737         }
 738 exit:
 739         pm_runtime_put(bank->chip.parent);
 740         return IRQ_HANDLED;
 741 }
 742
 743 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
 744 {
 745         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 746         unsigned long flags;
 747         unsigned offset = d->hwirq;
 748
 749         raw_spin_lock_irqsave(&bank->lock, flags);
 750
 751         if (!LINE_USED(bank->mod_usage, offset))
 752                 omap_set_gpio_direction(bank, offset, 1);
 753         else if (!omap_gpio_is_input(bank, offset))
 754                 goto err;
 755         omap_enable_gpio_module(bank, offset);
 756         bank->irq_usage |= BIT(offset);
 757
 758         raw_spin_unlock_irqrestore(&bank->lock, flags);
 759         omap_gpio_unmask_irq(d);
 760
 761         return 0;
 762 err:
 763         raw_spin_unlock_irqrestore(&bank->lock, flags);
 764         return -EINVAL;
 765 }
 766
 767 static void omap_gpio_irq_shutdown(struct irq_data *d)
 768 {
 769         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 770         unsigned long flags;
 771         unsigned offset = d->hwirq;
 772
 773         raw_spin_lock_irqsave(&bank->lock, flags);
 774         bank->irq_usage &= ~(BIT(offset));
 775         omap_set_gpio_irqenable(bank, offset, 0);
 776         omap_clear_gpio_irqstatus(bank, offset);
 777         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 778         if (!LINE_USED(bank->mod_usage, offset))
 779                 omap_clear_gpio_debounce(bank, offset);
 780         omap_disable_gpio_module(bank, offset);
 781         raw_spin_unlock_irqrestore(&bank->lock, flags);
 782 }
 783
 784 static void omap_gpio_irq_bus_lock(struct irq_data *data)
 785 {
 786         struct gpio_bank *bank = omap_irq_data_get_bank(data);
 787
 788         if (!BANK_USED(bank))
 789                 pm_runtime_get_sync(bank->chip.parent);
 790 }
 791
 792 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
 793 {
 794         struct gpio_bank *bank = omap_irq_data_get_bank(data);
 795
 796         /*
 797          * If this is the last IRQ to be freed in the bank,
 798          * disable the bank module.
 799          */
 800         if (!BANK_USED(bank))
 801                 pm_runtime_put(bank->chip.parent);
 802 }
 803
 804 static void omap_gpio_ack_irq(struct irq_data *d)
 805 {
 806         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 807         unsigned offset = d->hwirq;
 808
 809         omap_clear_gpio_irqstatus(bank, offset);
 810 }
 811
 812 static void omap_gpio_mask_irq(struct irq_data *d)
 813 {
 814         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 815         unsigned offset = d->hwirq;
 816         unsigned long flags;
 817
 818         raw_spin_lock_irqsave(&bank->lock, flags);
 819         omap_set_gpio_irqenable(bank, offset, 0);
 820         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 821         raw_spin_unlock_irqrestore(&bank->lock, flags);
 822 }
 823
 824 static void omap_gpio_unmask_irq(struct irq_data *d)
 825 {
 826         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 827         unsigned offset = d->hwirq;
 828         u32 trigger = irqd_get_trigger_type(d);
 829         unsigned long flags;
 830
 831         raw_spin_lock_irqsave(&bank->lock, flags);
 832         if (trigger)
 833                 omap_set_gpio_triggering(bank, offset, trigger);
 834
 835         /* For level-triggered GPIOs, the clearing must be done after
 836          * the HW source is cleared, thus after the handler has run */
 837         if (bank->level_mask & BIT(offset)) {
 838                 omap_set_gpio_irqenable(bank, offset, 0);
 839                 omap_clear_gpio_irqstatus(bank, offset);
 840         }
 841
 842         omap_set_gpio_irqenable(bank, offset, 1);
 843         raw_spin_unlock_irqrestore(&bank->lock, flags);
 844 }
 845
 846 /*---------------------------------------------------------------------*/
 847
 848 static int omap_mpuio_suspend_noirq(struct device *dev)
 849 {
 850         struct platform_device *pdev = to_platform_device(dev);
 851         struct gpio_bank        *bank = platform_get_drvdata(pdev);
 852         void __iomem            *mask_reg = bank->base +
 853                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 854         unsigned long           flags;
 855
 856         raw_spin_lock_irqsave(&bank->lock, flags);
 857         writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
 858         raw_spin_unlock_irqrestore(&bank->lock, flags);
 859
 860         return 0;
 861 }
 862
 863 static int omap_mpuio_resume_noirq(struct device *dev)
 864 {
 865         struct platform_device *pdev = to_platform_device(dev);
 866         struct gpio_bank        *bank = platform_get_drvdata(pdev);
 867         void __iomem            *mask_reg = bank->base +
 868                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 869         unsigned long           flags;
 870
 871         raw_spin_lock_irqsave(&bank->lock, flags);
 872         writel_relaxed(bank->context.wake_en, mask_reg);
 873         raw_spin_unlock_irqrestore(&bank->lock, flags);
 874
 875         return 0;
 876 }
 877
 878 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
 879         .suspend_noirq = omap_mpuio_suspend_noirq,
 880         .resume_noirq = omap_mpuio_resume_noirq,
 881 };
 882
 883 /* use platform_driver for this. */
 884 static struct platform_driver omap_mpuio_driver = {
 885         .driver         = {
 886                 .name   = "mpuio",
 887                 .pm     = &omap_mpuio_dev_pm_ops,
 888         },
 889 };
 890
 891 static struct platform_device omap_mpuio_device = {
 892         .name           = "mpuio",
 893         .id             = -1,
 894         .dev = {
 895                 .driver = &omap_mpuio_driver.driver,
 896         }
 897         /* could list the /proc/iomem resources */
 898 };
 899
 900 static inline void omap_mpuio_init(struct gpio_bank *bank)
 901 {
 902         platform_set_drvdata(&omap_mpuio_device, bank);
 903
 904         if (platform_driver_register(&omap_mpuio_driver) == 0)
 905                 (void) platform_device_register(&omap_mpuio_device);
 906 }
 907
 908 /*---------------------------------------------------------------------*/
 909
 910 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 911 {
 912         struct gpio_bank *bank;
 913         unsigned long flags;
 914         void __iomem *reg;
 915         int dir;
 916
 917         bank = gpiochip_get_data(chip);
 918         reg = bank->base + bank->regs->direction;
 919         raw_spin_lock_irqsave(&bank->lock, flags);
 920         dir = !!(readl_relaxed(reg) & BIT(offset));
 921         raw_spin_unlock_irqrestore(&bank->lock, flags);
 922         return dir;
 923 }
 924
 925 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
 926 {
 927         struct gpio_bank *bank;
 928         unsigned long flags;
 929
 930         bank = gpiochip_get_data(chip);
 931         raw_spin_lock_irqsave(&bank->lock, flags);
 932         omap_set_gpio_direction(bank, offset, 1);
 933         raw_spin_unlock_irqrestore(&bank->lock, flags);
 934         return 0;
 935 }
 936
 937 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
 938 {
 939         struct gpio_bank *bank;
 940
 941         bank = gpiochip_get_data(chip);
 942
 943         if (omap_gpio_is_input(bank, offset))
 944                 return omap_get_gpio_datain(bank, offset);
 945         else
 946                 return omap_get_gpio_dataout(bank, offset);
 947 }
 948
 949 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
 950 {
 951         struct gpio_bank *bank;
 952         unsigned long flags;
 953
 954         bank = gpiochip_get_data(chip);
 955         raw_spin_lock_irqsave(&bank->lock, flags);
 956         bank->set_dataout(bank, offset, value);
 957         omap_set_gpio_direction(bank, offset, 0);
 958         raw_spin_unlock_irqrestore(&bank->lock, flags);
 959         return 0;
 960 }
 961
 962 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
 963                               unsigned debounce)
 964 {
 965         struct gpio_bank *bank;
 966         unsigned long flags;
 967
 968         bank = gpiochip_get_data(chip);
 969
 970         raw_spin_lock_irqsave(&bank->lock, flags);
 971         omap2_set_gpio_debounce(bank, offset, debounce);
 972         raw_spin_unlock_irqrestore(&bank->lock, flags);
 973
 974         return 0;
 975 }
 976
 977 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 978 {
 979         struct gpio_bank *bank;
 980         unsigned long flags;
 981
 982         bank = gpiochip_get_data(chip);
 983         raw_spin_lock_irqsave(&bank->lock, flags);
 984         bank->set_dataout(bank, offset, value);
 985         raw_spin_unlock_irqrestore(&bank->lock, flags);
 986 }
 987
 988 /*---------------------------------------------------------------------*/
 989
 990 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
 991 {
 992         static bool called;
 993         u32 rev;
 994
 995         if (called || bank->regs->revision == USHRT_MAX)
 996                 return;
 997
 998         rev = readw_relaxed(bank->base + bank->regs->revision);
 999         pr_info("OMAP GPIO hardware version %d.%d\n",
1000                 (rev >> 4) & 0x0f, rev & 0x0f);
1001
1002         called = true;
1003 }
1004
1005 static void omap_gpio_mod_init(struct gpio_bank *bank)
1006 {
1007         void __iomem *base = bank->base;
1008         u32 l = 0xffffffff;
1009
1010         if (bank->width == 16)
1011                 l = 0xffff;
1012
1013         if (bank->is_mpuio) {
1014                 writel_relaxed(l, bank->base + bank->regs->irqenable);
1015                 return;
1016         }
1017
1018         omap_gpio_rmw(base, bank->regs->irqenable, l,
1019                       bank->regs->irqenable_inv);
1020         omap_gpio_rmw(base, bank->regs->irqstatus, l,
1021                       !bank->regs->irqenable_inv);
1022         if (bank->regs->debounce_en)
1023                 writel_relaxed(0, base + bank->regs->debounce_en);
1024
1025         /* Save OE default value (0xffffffff) in the context */
1026         bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1027          /* Initialize interface clk ungated, module enabled */
1028         if (bank->regs->ctrl)
1029                 writel_relaxed(0, base + bank->regs->ctrl);
1030 }
1031
1032 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1033 {
1034         static int gpio;
1035         int irq_base = 0;
1036         int ret;
1037
1038         /*
1039          * REVISIT eventually switch from OMAP-specific gpio structs
1040          * over to the generic ones
1041          */
1042         bank->chip.request = omap_gpio_request;
1043         bank->chip.free = omap_gpio_free;
1044         bank->chip.get_direction = omap_gpio_get_direction;
1045         bank->chip.direction_input = omap_gpio_input;
1046         bank->chip.get = omap_gpio_get;
1047         bank->chip.direction_output = omap_gpio_output;
1048         bank->chip.set_debounce = omap_gpio_debounce;
1049         bank->chip.set = omap_gpio_set;
1050         if (bank->is_mpuio) {
1051                 bank->chip.label = "mpuio";
1052                 if (bank->regs->wkup_en)
1053                         bank->chip.parent = &omap_mpuio_device.dev;
1054                 bank->chip.base = OMAP_MPUIO(0);
1055         } else {
1056                 bank->chip.label = "gpio";
1057                 bank->chip.base = gpio;
1058         }
1059         bank->chip.ngpio = bank->width;
1060
1061         ret = gpiochip_add_data(&bank->chip, bank);
1062         if (ret) {
1063                 dev_err(bank->chip.parent,
1064                         "Could not register gpio chip %d\n", ret);
1065                 return ret;
1066         }
1067
1068         if (!bank->is_mpuio)
1069                 gpio += bank->width;
1070
1071 #ifdef CONFIG_ARCH_OMAP1
1072         /*
1073          * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1074          * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1075          */
1076         irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1077         if (irq_base < 0) {
1078                 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1079                 return -ENODEV;
1080         }
1081 #endif
1082
1083         /* MPUIO is a bit different, reading IRQ status clears it */
1084         if (bank->is_mpuio) {
1085                 irqc->irq_ack = dummy_irq_chip.irq_ack;
1086                 if (!bank->regs->wkup_en)
1087                         irqc->irq_set_wake = NULL;
1088         }
1089
1090         ret = gpiochip_irqchip_add(&bank->chip, irqc,
1091                                    irq_base, handle_bad_irq,
1092                                    IRQ_TYPE_NONE);
1093
1094         if (ret) {
1095                 dev_err(bank->chip.parent,
1096                         "Couldn't add irqchip to gpiochip %d\n", ret);
1097                 gpiochip_remove(&bank->chip);
1098                 return -ENODEV;
1099         }
1100
1101         gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1102
1103         ret = devm_request_irq(bank->chip.parent, bank->irq,
1104                                omap_gpio_irq_handler,
1105                                0, dev_name(bank->chip.parent), bank);
1106         if (ret)
1107                 gpiochip_remove(&bank->chip);
1108
1109         return ret;
1110 }
1111
1112 static const struct of_device_id omap_gpio_match[];
1113
1114 static int omap_gpio_probe(struct platform_device *pdev)
1115 {
1116         struct device *dev = &pdev->dev;
1117         struct device_node *node = dev->of_node;
1118         const struct of_device_id *match;
1119         const struct omap_gpio_platform_data *pdata;
1120         struct resource *res;
1121         struct gpio_bank *bank;
1122         struct irq_chip *irqc;
1123         int ret;
1124
1125         match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1126
1127         pdata = match ? match->data : dev_get_platdata(dev);
1128         if (!pdata)
1129                 return -EINVAL;
1130
1131         bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1132         if (!bank) {
1133                 dev_err(dev, "Memory alloc failed\n");
1134                 return -ENOMEM;
1135         }
1136
1137         irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1138         if (!irqc)
1139                 return -ENOMEM;
1140
1141         irqc->irq_startup = omap_gpio_irq_startup,
1142         irqc->irq_shutdown = omap_gpio_irq_shutdown,
1143         irqc->irq_ack = omap_gpio_ack_irq,
1144         irqc->irq_mask = omap_gpio_mask_irq,
1145         irqc->irq_unmask = omap_gpio_unmask_irq,
1146         irqc->irq_set_type = omap_gpio_irq_type,
1147         irqc->irq_set_wake = omap_gpio_wake_enable,
1148         irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1149         irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1150         irqc->name = dev_name(&pdev->dev);
1151         irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1152
1153         bank->irq = platform_get_irq(pdev, 0);
1154         if (bank->irq <= 0) {
1155                 if (!bank->irq)
1156                         bank->irq = -ENXIO;
1157                 if (bank->irq != -EPROBE_DEFER)
1158                         dev_err(dev,
1159                                 "can't get irq resource ret=%d\n", bank->irq);
1160                 return bank->irq;
1161         }
1162
1163         bank->chip.parent = dev;
1164         bank->chip.owner = THIS_MODULE;
1165         bank->dbck_flag = pdata->dbck_flag;
1166         bank->stride = pdata->bank_stride;
1167         bank->width = pdata->bank_width;
1168         bank->is_mpuio = pdata->is_mpuio;
1169         bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1170         bank->regs = pdata->regs;
1171 #ifdef CONFIG_OF_GPIO
1172         bank->chip.of_node = of_node_get(node);
1173 #endif
1174         if (node) {
1175                 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1176                         bank->loses_context = true;
1177         } else {
1178                 bank->loses_context = pdata->loses_context;
1179
1180                 if (bank->loses_context)
1181                         bank->get_context_loss_count =
1182                                 pdata->get_context_loss_count;
1183         }
1184
1185         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1186                 bank->set_dataout = omap_set_gpio_dataout_reg;
1187         else
1188                 bank->set_dataout = omap_set_gpio_dataout_mask;
1189
1190         raw_spin_lock_init(&bank->lock);
1191         raw_spin_lock_init(&bank->wa_lock);
1192
1193         /* Static mapping, never released */
1194         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1195         bank->base = devm_ioremap_resource(dev, res);
1196         if (IS_ERR(bank->base)) {
1197                 return PTR_ERR(bank->base);
1198         }
1199
1200         if (bank->dbck_flag) {
1201                 bank->dbck = devm_clk_get(dev, "dbclk");
1202                 if (IS_ERR(bank->dbck)) {
1203                         dev_err(dev,
1204                                 "Could not get gpio dbck. Disable debounce\n");
1205                         bank->dbck_flag = false;
1206                 } else {
1207                         clk_prepare(bank->dbck);
1208                 }
1209         }
1210
1211         platform_set_drvdata(pdev, bank);
1212
1213         pm_runtime_enable(dev);
1214         pm_runtime_irq_safe(dev);
1215         pm_runtime_get_sync(dev);
1216
1217         if (bank->is_mpuio)
1218                 omap_mpuio_init(bank);
1219
1220         omap_gpio_mod_init(bank);
1221
1222         ret = omap_gpio_chip_init(bank, irqc);
1223         if (ret) {
1224                 pm_runtime_put_sync(dev);
1225                 pm_runtime_disable(dev);
1226                 return ret;
1227         }
1228
1229         omap_gpio_show_rev(bank);
1230
1231         pm_runtime_put(dev);
1232
1233         list_add_tail(&bank->node, &omap_gpio_list);
1234
1235         return 0;
1236 }
1237
1238 static int omap_gpio_remove(struct platform_device *pdev)
1239 {
1240         struct gpio_bank *bank = platform_get_drvdata(pdev);
1241
1242         list_del(&bank->node);
1243         gpiochip_remove(&bank->chip);
1244         pm_runtime_disable(&pdev->dev);
1245         if (bank->dbck_flag)
1246                 clk_unprepare(bank->dbck);
1247
1248         return 0;
1249 }
1250
1251 #ifdef CONFIG_ARCH_OMAP2PLUS
1252
1253 #if defined(CONFIG_PM)
1254 static void omap_gpio_restore_context(struct gpio_bank *bank);
1255
1256 static int omap_gpio_runtime_suspend(struct device *dev)
1257 {
1258         struct platform_device *pdev = to_platform_device(dev);
1259         struct gpio_bank *bank = platform_get_drvdata(pdev);
1260         u32 l1 = 0, l2 = 0;
1261         unsigned long flags;
1262         u32 wake_low, wake_hi;
1263
1264         raw_spin_lock_irqsave(&bank->lock, flags);
1265
1266         /*
1267          * Only edges can generate a wakeup event to the PRCM.
1268          *
1269          * Therefore, ensure any wake-up capable GPIOs have
1270          * edge-detection enabled before going idle to ensure a wakeup
1271          * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1272          * NDA TRM 25.5.3.1)
1273          *
1274          * The normal values will be restored upon ->runtime_resume()
1275          * by writing back the values saved in bank->context.
1276          */
1277         wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1278         if (wake_low)
1279                 writel_relaxed(wake_low | bank->context.fallingdetect,
1280                              bank->base + bank->regs->fallingdetect);
1281         wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1282         if (wake_hi)
1283                 writel_relaxed(wake_hi | bank->context.risingdetect,
1284                              bank->base + bank->regs->risingdetect);
1285
1286         if (!bank->enabled_non_wakeup_gpios)
1287                 goto update_gpio_context_count;
1288
1289         if (bank->power_mode != OFF_MODE) {
1290                 bank->power_mode = 0;
1291                 goto update_gpio_context_count;
1292         }
1293         /*
1294          * If going to OFF, remove triggering for all
1295          * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1296          * generated.  See OMAP2420 Errata item 1.101.
1297          */
1298         bank->saved_datain = readl_relaxed(bank->base +
1299                                                 bank->regs->datain);
1300         l1 = bank->context.fallingdetect;
1301         l2 = bank->context.risingdetect;
1302
1303         l1 &= ~bank->enabled_non_wakeup_gpios;
1304         l2 &= ~bank->enabled_non_wakeup_gpios;
1305
1306         writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1307         writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1308
1309         bank->workaround_enabled = true;
1310
1311 update_gpio_context_count:
1312         if (bank->get_context_loss_count)
1313                 bank->context_loss_count =
1314                                 bank->get_context_loss_count(dev);
1315
1316         omap_gpio_dbck_disable(bank);
1317         raw_spin_unlock_irqrestore(&bank->lock, flags);
1318
1319         return 0;
1320 }
1321
1322 static void omap_gpio_init_context(struct gpio_bank *p);
1323
1324 static int omap_gpio_runtime_resume(struct device *dev)
1325 {
1326         struct platform_device *pdev = to_platform_device(dev);
1327         struct gpio_bank *bank = platform_get_drvdata(pdev);
1328         u32 l = 0, gen, gen0, gen1;
1329         unsigned long flags;
1330         int c;
1331
1332         raw_spin_lock_irqsave(&bank->lock, flags);
1333
1334         /*
1335          * On the first resume during the probe, the context has not
1336          * been initialised and so initialise it now. Also initialise
1337          * the context loss count.
1338          */
1339         if (bank->loses_context && !bank->context_valid) {
1340                 omap_gpio_init_context(bank);
1341
1342                 if (bank->get_context_loss_count)
1343                         bank->context_loss_count =
1344                                 bank->get_context_loss_count(dev);
1345         }
1346
1347         omap_gpio_dbck_enable(bank);
1348
1349         /*
1350          * In ->runtime_suspend(), level-triggered, wakeup-enabled
1351          * GPIOs were set to edge trigger also in order to be able to
1352          * generate a PRCM wakeup.  Here we restore the
1353          * pre-runtime_suspend() values for edge triggering.
1354          */
1355         writel_relaxed(bank->context.fallingdetect,
1356                      bank->base + bank->regs->fallingdetect);
1357         writel_relaxed(bank->context.risingdetect,
1358                      bank->base + bank->regs->risingdetect);
1359
1360         if (bank->loses_context) {
1361                 if (!bank->get_context_loss_count) {
1362                         omap_gpio_restore_context(bank);
1363                 } else {
1364                         c = bank->get_context_loss_count(dev);
1365                         if (c != bank->context_loss_count) {
1366                                 omap_gpio_restore_context(bank);
1367                         } else {
1368                                 raw_spin_unlock_irqrestore(&bank->lock, flags);
1369                                 return 0;
1370                         }
1371                 }
1372         }
1373
1374         if (!bank->workaround_enabled) {
1375                 raw_spin_unlock_irqrestore(&bank->lock, flags);
1376                 return 0;
1377         }
1378
1379         l = readl_relaxed(bank->base + bank->regs->datain);
1380
1381         /*
1382          * Check if any of the non-wakeup interrupt GPIOs have changed
1383          * state.  If so, generate an IRQ by software.  This is
1384          * horribly racy, but it's the best we can do to work around
1385          * this silicon bug.
1386          */
1387         l ^= bank->saved_datain;
1388         l &= bank->enabled_non_wakeup_gpios;
1389
1390         /*
1391          * No need to generate IRQs for the rising edge for gpio IRQs
1392          * configured with falling edge only; and vice versa.
1393          */
1394         gen0 = l & bank->context.fallingdetect;
1395         gen0 &= bank->saved_datain;
1396
1397         gen1 = l & bank->context.risingdetect;
1398         gen1 &= ~(bank->saved_datain);
1399
1400         /* FIXME: Consider GPIO IRQs with level detections properly! */
1401         gen = l & (~(bank->context.fallingdetect) &
1402                                          ~(bank->context.risingdetect));
1403         /* Consider all GPIO IRQs needed to be updated */
1404         gen |= gen0 | gen1;
1405
1406         if (gen) {
1407                 u32 old0, old1;
1408
1409                 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1410                 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1411
1412                 if (!bank->regs->irqstatus_raw0) {
1413                         writel_relaxed(old0 | gen, bank->base +
1414                                                 bank->regs->leveldetect0);
1415                         writel_relaxed(old1 | gen, bank->base +
1416                                                 bank->regs->leveldetect1);
1417                 }
1418
1419                 if (bank->regs->irqstatus_raw0) {
1420                         writel_relaxed(old0 | l, bank->base +
1421                                                 bank->regs->leveldetect0);
1422                         writel_relaxed(old1 | l, bank->base +
1423                                                 bank->regs->leveldetect1);
1424                 }
1425                 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1426                 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1427         }
1428
1429         bank->workaround_enabled = false;
1430         raw_spin_unlock_irqrestore(&bank->lock, flags);
1431
1432         return 0;
1433 }
1434 #endif /* CONFIG_PM */
1435
1436 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1437 void omap2_gpio_prepare_for_idle(int pwr_mode)
1438 {
1439         struct gpio_bank *bank;
1440
1441         list_for_each_entry(bank, &omap_gpio_list, node) {
1442                 if (!BANK_USED(bank) || !bank->loses_context)
1443                         continue;
1444
1445                 bank->power_mode = pwr_mode;
1446
1447                 pm_runtime_put_sync_suspend(bank->chip.parent);
1448         }
1449 }
1450
1451 void omap2_gpio_resume_after_idle(void)
1452 {
1453         struct gpio_bank *bank;
1454
1455         list_for_each_entry(bank, &omap_gpio_list, node) {
1456                 if (!BANK_USED(bank) || !bank->loses_context)
1457                         continue;
1458
1459                 pm_runtime_get_sync(bank->chip.parent);
1460         }
1461 }
1462 #endif
1463
1464 #if defined(CONFIG_PM)
1465 static void omap_gpio_init_context(struct gpio_bank *p)
1466 {
1467         struct omap_gpio_reg_offs *regs = p->regs;
1468         void __iomem *base = p->base;
1469
1470         p->context.ctrl         = readl_relaxed(base + regs->ctrl);
1471         p->context.oe           = readl_relaxed(base + regs->direction);
1472         p->context.wake_en      = readl_relaxed(base + regs->wkup_en);
1473         p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1474         p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1475         p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1476         p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1477         p->context.irqenable1   = readl_relaxed(base + regs->irqenable);
1478         p->context.irqenable2   = readl_relaxed(base + regs->irqenable2);
1479
1480         if (regs->set_dataout && p->regs->clr_dataout)
1481                 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1482         else
1483                 p->context.dataout = readl_relaxed(base + regs->dataout);
1484
1485         p->context_valid = true;
1486 }
1487
1488 static void omap_gpio_restore_context(struct gpio_bank *bank)
1489 {
1490         writel_relaxed(bank->context.wake_en,
1491                                 bank->base + bank->regs->wkup_en);
1492         writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1493         writel_relaxed(bank->context.leveldetect0,
1494                                 bank->base + bank->regs->leveldetect0);
1495         writel_relaxed(bank->context.leveldetect1,
1496                                 bank->base + bank->regs->leveldetect1);
1497         writel_relaxed(bank->context.risingdetect,
1498                                 bank->base + bank->regs->risingdetect);
1499         writel_relaxed(bank->context.fallingdetect,
1500                                 bank->base + bank->regs->fallingdetect);
1501         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1502                 writel_relaxed(bank->context.dataout,
1503                                 bank->base + bank->regs->set_dataout);
1504         else
1505                 writel_relaxed(bank->context.dataout,
1506                                 bank->base + bank->regs->dataout);
1507         writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1508
1509         if (bank->dbck_enable_mask) {
1510                 writel_relaxed(bank->context.debounce, bank->base +
1511                                         bank->regs->debounce);
1512                 writel_relaxed(bank->context.debounce_en,
1513                                         bank->base + bank->regs->debounce_en);
1514         }
1515
1516         writel_relaxed(bank->context.irqenable1,
1517                                 bank->base + bank->regs->irqenable);
1518         writel_relaxed(bank->context.irqenable2,
1519                                 bank->base + bank->regs->irqenable2);
1520 }
1521 #endif /* CONFIG_PM */
1522 #else
1523 #define omap_gpio_runtime_suspend NULL
1524 #define omap_gpio_runtime_resume NULL
1525 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1526 #endif
1527
1528 static const struct dev_pm_ops gpio_pm_ops = {
1529         SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1530                                                                         NULL)
1531 };
1532
1533 #if defined(CONFIG_OF)
1534 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1535         .revision =             OMAP24XX_GPIO_REVISION,
1536         .direction =            OMAP24XX_GPIO_OE,
1537         .datain =               OMAP24XX_GPIO_DATAIN,
1538         .dataout =              OMAP24XX_GPIO_DATAOUT,
1539         .set_dataout =          OMAP24XX_GPIO_SETDATAOUT,
1540         .clr_dataout =          OMAP24XX_GPIO_CLEARDATAOUT,
1541         .irqstatus =            OMAP24XX_GPIO_IRQSTATUS1,
1542         .irqstatus2 =           OMAP24XX_GPIO_IRQSTATUS2,
1543         .irqenable =            OMAP24XX_GPIO_IRQENABLE1,
1544         .irqenable2 =           OMAP24XX_GPIO_IRQENABLE2,
1545         .set_irqenable =        OMAP24XX_GPIO_SETIRQENABLE1,
1546         .clr_irqenable =        OMAP24XX_GPIO_CLEARIRQENABLE1,
1547         .debounce =             OMAP24XX_GPIO_DEBOUNCE_VAL,
1548         .debounce_en =          OMAP24XX_GPIO_DEBOUNCE_EN,
1549         .ctrl =                 OMAP24XX_GPIO_CTRL,
1550         .wkup_en =              OMAP24XX_GPIO_WAKE_EN,
1551         .leveldetect0 =         OMAP24XX_GPIO_LEVELDETECT0,
1552         .leveldetect1 =         OMAP24XX_GPIO_LEVELDETECT1,
1553         .risingdetect =         OMAP24XX_GPIO_RISINGDETECT,
1554         .fallingdetect =        OMAP24XX_GPIO_FALLINGDETECT,
1555 };
1556
1557 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1558         .revision =             OMAP4_GPIO_REVISION,
1559         .direction =            OMAP4_GPIO_OE,
1560         .datain =               OMAP4_GPIO_DATAIN,
1561         .dataout =              OMAP4_GPIO_DATAOUT,
1562         .set_dataout =          OMAP4_GPIO_SETDATAOUT,
1563         .clr_dataout =          OMAP4_GPIO_CLEARDATAOUT,
1564         .irqstatus =            OMAP4_GPIO_IRQSTATUS0,
1565         .irqstatus2 =           OMAP4_GPIO_IRQSTATUS1,
1566         .irqenable =            OMAP4_GPIO_IRQSTATUSSET0,
1567         .irqenable2 =           OMAP4_GPIO_IRQSTATUSSET1,
1568         .set_irqenable =        OMAP4_GPIO_IRQSTATUSSET0,
1569         .clr_irqenable =        OMAP4_GPIO_IRQSTATUSCLR0,
1570         .debounce =             OMAP4_GPIO_DEBOUNCINGTIME,
1571         .debounce_en =          OMAP4_GPIO_DEBOUNCENABLE,
1572         .ctrl =                 OMAP4_GPIO_CTRL,
1573         .wkup_en =              OMAP4_GPIO_IRQWAKEN0,
1574         .leveldetect0 =         OMAP4_GPIO_LEVELDETECT0,
1575         .leveldetect1 =         OMAP4_GPIO_LEVELDETECT1,
1576         .risingdetect =         OMAP4_GPIO_RISINGDETECT,
1577         .fallingdetect =        OMAP4_GPIO_FALLINGDETECT,
1578 };
1579
1580 static const struct omap_gpio_platform_data omap2_pdata = {
1581         .regs = &omap2_gpio_regs,
1582         .bank_width = 32,
1583         .dbck_flag = false,
1584 };
1585
1586 static const struct omap_gpio_platform_data omap3_pdata = {
1587         .regs = &omap2_gpio_regs,
1588         .bank_width = 32,
1589         .dbck_flag = true,
1590 };
1591
1592 static const struct omap_gpio_platform_data omap4_pdata = {
1593         .regs = &omap4_gpio_regs,
1594         .bank_width = 32,
1595         .dbck_flag = true,
1596 };
1597
1598 static const struct of_device_id omap_gpio_match[] = {
1599         {
1600                 .compatible = "ti,omap4-gpio",
1601                 .data = &omap4_pdata,
1602         },
1603         {
1604                 .compatible = "ti,omap3-gpio",
1605                 .data = &omap3_pdata,
1606         },
1607         {
1608                 .compatible = "ti,omap2-gpio",
1609                 .data = &omap2_pdata,
1610         },
1611         { },
1612 };
1613 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1614 #endif
1615
1616 static struct platform_driver omap_gpio_driver = {
1617         .probe          = omap_gpio_probe,
1618         .remove         = omap_gpio_remove,
1619         .driver         = {
1620                 .name   = "omap_gpio",
1621                 .pm     = &gpio_pm_ops,
1622                 .of_match_table = of_match_ptr(omap_gpio_match),
1623         },
1624 };
1625
1626 /*
1627  * gpio driver register needs to be done before
1628  * machine_init functions access gpio APIs.
1629  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1630  */
1631 static int __init omap_gpio_drv_reg(void)
1632 {
1633         return platform_driver_register(&omap_gpio_driver);
1634 }
1635 postcore_initcall(omap_gpio_drv_reg);
1636
1637 static void __exit omap_gpio_exit(void)
1638 {
1639         platform_driver_unregister(&omap_gpio_driver);
1640 }
1641 module_exit(omap_gpio_exit);
1642
1643 MODULE_DESCRIPTION("omap gpio driver");
1644 MODULE_ALIAS("platform:gpio-omap");
1645 MODULE_LICENSE("GPL v2");