2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
35 u16 virtual_irq_start;
37 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
42 u32 enabled_non_wakeup_gpios;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
50 struct gpio_chip chip;
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
61 struct omap_gpio_reg_offs *regs;
64 #ifdef CONFIG_ARCH_OMAP3
65 struct omap3_gpio_regs {
78 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
82 * TODO: Cleanup gpio_bank usage as it is having information
83 * related to all instances of the device
85 static struct gpio_bank *gpio_bank;
87 /* TODO: Analyze removing gpio_bank_count usage from driver code */
90 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
91 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
93 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
95 void __iomem *reg = bank->base;
98 reg += bank->regs->direction;
104 __raw_writel(l, reg);
108 /* set data out value using dedicate set/clear register */
109 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
111 void __iomem *reg = bank->base;
112 u32 l = GPIO_BIT(bank, gpio);
115 reg += bank->regs->set_dataout;
117 reg += bank->regs->clr_dataout;
119 __raw_writel(l, reg);
122 /* set data out value using mask register */
123 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
125 void __iomem *reg = bank->base + bank->regs->dataout;
126 u32 gpio_bit = GPIO_BIT(bank, gpio);
129 l = __raw_readl(reg);
134 __raw_writel(l, reg);
137 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
139 void __iomem *reg = bank->base + bank->regs->datain;
141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
144 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
146 void __iomem *reg = bank->base + bank->regs->dataout;
148 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
151 #define MOD_REG_BIT(reg, bit_mask, set) \
153 int l = __raw_readl(base + reg); \
154 if (set) l |= bit_mask; \
155 else l &= ~bit_mask; \
156 __raw_writel(l, base + reg); \
160 * _set_gpio_debounce - low level gpio debounce time
161 * @bank: the gpio bank we're acting upon
162 * @gpio: the gpio number on this @gpio
163 * @debounce: debounce time to use
165 * OMAP's debounce time is in 31us steps so we need
166 * to convert and round up to the closest unit.
168 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
175 if (!bank->dbck_flag)
180 else if (debounce > 7936)
183 debounce = (debounce / 0x1f) - 1;
185 l = GPIO_BIT(bank, gpio);
187 reg = bank->base + bank->regs->debounce;
188 __raw_writel(debounce, reg);
190 reg = bank->base + bank->regs->debounce_en;
191 val = __raw_readl(reg);
195 clk_enable(bank->dbck);
198 clk_disable(bank->dbck);
200 bank->dbck_enable_mask = val;
202 __raw_writel(val, reg);
205 #ifdef CONFIG_ARCH_OMAP2PLUS
206 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
209 void __iomem *base = bank->base;
210 u32 gpio_bit = 1 << gpio;
212 if (cpu_is_omap44xx()) {
213 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
214 trigger & IRQ_TYPE_LEVEL_LOW);
215 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
216 trigger & IRQ_TYPE_LEVEL_HIGH);
217 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
218 trigger & IRQ_TYPE_EDGE_RISING);
219 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
220 trigger & IRQ_TYPE_EDGE_FALLING);
222 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
223 trigger & IRQ_TYPE_LEVEL_LOW);
224 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
225 trigger & IRQ_TYPE_LEVEL_HIGH);
226 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
227 trigger & IRQ_TYPE_EDGE_RISING);
228 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
229 trigger & IRQ_TYPE_EDGE_FALLING);
231 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
232 if (cpu_is_omap44xx()) {
233 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
237 * GPIO wakeup request can only be generated on edge
240 if (trigger & IRQ_TYPE_EDGE_BOTH)
241 __raw_writel(1 << gpio, bank->base
242 + OMAP24XX_GPIO_SETWKUENA);
244 __raw_writel(1 << gpio, bank->base
245 + OMAP24XX_GPIO_CLEARWKUENA);
248 /* This part needs to be executed always for OMAP34xx */
249 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
251 * Log the edge gpio and manually trigger the IRQ
252 * after resume if the input level changes
253 * to avoid irq lost during PER RET/OFF mode
254 * Applies for omap2 non-wakeup gpio and all omap3 gpios
256 if (trigger & IRQ_TYPE_EDGE_BOTH)
257 bank->enabled_non_wakeup_gpios |= gpio_bit;
259 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
262 if (cpu_is_omap44xx()) {
264 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
265 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
268 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
269 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
274 #ifdef CONFIG_ARCH_OMAP1
276 * This only applies to chips that can't do both rising and falling edge
277 * detection at once. For all other chips, this function is a noop.
279 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
281 void __iomem *reg = bank->base;
284 switch (bank->method) {
286 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
288 #ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_INT_CONTROL;
293 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
294 case METHOD_GPIO_7XX:
295 reg += OMAP7XX_GPIO_INT_CONTROL;
302 l = __raw_readl(reg);
308 __raw_writel(l, reg);
312 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
314 void __iomem *reg = bank->base;
317 switch (bank->method) {
318 #ifdef CONFIG_ARCH_OMAP1
320 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
321 l = __raw_readl(reg);
322 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
323 bank->toggle_mask |= 1 << gpio;
324 if (trigger & IRQ_TYPE_EDGE_RISING)
326 else if (trigger & IRQ_TYPE_EDGE_FALLING)
332 #ifdef CONFIG_ARCH_OMAP15XX
333 case METHOD_GPIO_1510:
334 reg += OMAP1510_GPIO_INT_CONTROL;
335 l = __raw_readl(reg);
336 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
337 bank->toggle_mask |= 1 << gpio;
338 if (trigger & IRQ_TYPE_EDGE_RISING)
340 else if (trigger & IRQ_TYPE_EDGE_FALLING)
346 #ifdef CONFIG_ARCH_OMAP16XX
347 case METHOD_GPIO_1610:
349 reg += OMAP1610_GPIO_EDGE_CTRL2;
351 reg += OMAP1610_GPIO_EDGE_CTRL1;
353 l = __raw_readl(reg);
354 l &= ~(3 << (gpio << 1));
355 if (trigger & IRQ_TYPE_EDGE_RISING)
356 l |= 2 << (gpio << 1);
357 if (trigger & IRQ_TYPE_EDGE_FALLING)
358 l |= 1 << (gpio << 1);
360 /* Enable wake-up during idle for dynamic tick */
361 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
363 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
366 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
367 case METHOD_GPIO_7XX:
368 reg += OMAP7XX_GPIO_INT_CONTROL;
369 l = __raw_readl(reg);
370 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
371 bank->toggle_mask |= 1 << gpio;
372 if (trigger & IRQ_TYPE_EDGE_RISING)
374 else if (trigger & IRQ_TYPE_EDGE_FALLING)
380 #ifdef CONFIG_ARCH_OMAP2PLUS
381 case METHOD_GPIO_24XX:
382 case METHOD_GPIO_44XX:
383 set_24xx_gpio_triggering(bank, gpio, trigger);
389 __raw_writel(l, reg);
395 static int gpio_irq_type(struct irq_data *d, unsigned type)
397 struct gpio_bank *bank;
402 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
403 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
405 gpio = d->irq - IH_GPIO_BASE;
407 if (type & ~IRQ_TYPE_SENSE_MASK)
410 /* OMAP1 allows only only edge triggering */
411 if (!cpu_class_is_omap2()
412 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
415 bank = irq_data_get_irq_chip_data(d);
416 spin_lock_irqsave(&bank->lock, flags);
417 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
418 spin_unlock_irqrestore(&bank->lock, flags);
420 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
421 __irq_set_handler_locked(d->irq, handle_level_irq);
422 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
423 __irq_set_handler_locked(d->irq, handle_edge_irq);
428 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
430 void __iomem *reg = bank->base;
432 reg += bank->regs->irqstatus;
433 __raw_writel(gpio_mask, reg);
435 /* Workaround for clearing DSP GPIO interrupts to allow retention */
436 if (bank->regs->irqstatus2) {
437 reg = bank->base + bank->regs->irqstatus2;
438 __raw_writel(gpio_mask, reg);
441 /* Flush posted write for the irq status to avoid spurious interrupts */
445 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
447 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
450 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
452 void __iomem *reg = bank->base;
454 u32 mask = (1 << bank->width) - 1;
456 reg += bank->regs->irqenable;
457 l = __raw_readl(reg);
458 if (bank->regs->irqenable_inv)
464 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
466 void __iomem *reg = bank->base;
469 if (bank->regs->set_irqenable) {
470 reg += bank->regs->set_irqenable;
473 reg += bank->regs->irqenable;
474 l = __raw_readl(reg);
475 if (bank->regs->irqenable_inv)
481 __raw_writel(l, reg);
484 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
486 void __iomem *reg = bank->base;
489 if (bank->regs->clr_irqenable) {
490 reg += bank->regs->clr_irqenable;
493 reg += bank->regs->irqenable;
494 l = __raw_readl(reg);
495 if (bank->regs->irqenable_inv)
501 __raw_writel(l, reg);
504 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
506 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
510 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
511 * 1510 does not seem to have a wake-up register. If JTAG is connected
512 * to the target, system will wake up always on GPIO events. While
513 * system is running all registered GPIO interrupts need to have wake-up
514 * enabled. When system is suspended, only selected GPIO interrupts need
515 * to have wake-up enabled.
517 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
519 u32 gpio_bit = GPIO_BIT(bank, gpio);
522 if (bank->non_wakeup_gpios & gpio_bit) {
524 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
528 spin_lock_irqsave(&bank->lock, flags);
530 bank->suspend_wakeup |= gpio_bit;
532 bank->suspend_wakeup &= ~gpio_bit;
534 spin_unlock_irqrestore(&bank->lock, flags);
539 static void _reset_gpio(struct gpio_bank *bank, int gpio)
541 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
542 _set_gpio_irqenable(bank, gpio, 0);
543 _clear_gpio_irqstatus(bank, gpio);
544 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
547 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
548 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
550 unsigned int gpio = d->irq - IH_GPIO_BASE;
551 struct gpio_bank *bank;
554 bank = irq_data_get_irq_chip_data(d);
555 retval = _set_gpio_wakeup(bank, gpio, enable);
560 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
562 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
565 spin_lock_irqsave(&bank->lock, flags);
567 /* Set trigger to none. You need to enable the desired trigger with
568 * request_irq() or set_irq_type().
570 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
572 #ifdef CONFIG_ARCH_OMAP15XX
573 if (bank->method == METHOD_GPIO_1510) {
576 /* Claim the pin for MPU */
577 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
578 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
581 if (!cpu_class_is_omap1()) {
582 if (!bank->mod_usage) {
583 void __iomem *reg = bank->base;
586 if (cpu_is_omap24xx() || cpu_is_omap34xx())
587 reg += OMAP24XX_GPIO_CTRL;
588 else if (cpu_is_omap44xx())
589 reg += OMAP4_GPIO_CTRL;
590 ctrl = __raw_readl(reg);
591 /* Module is enabled, clocks are not gated */
593 __raw_writel(ctrl, reg);
595 bank->mod_usage |= 1 << offset;
597 spin_unlock_irqrestore(&bank->lock, flags);
602 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
604 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
607 spin_lock_irqsave(&bank->lock, flags);
608 #ifdef CONFIG_ARCH_OMAP16XX
609 if (bank->method == METHOD_GPIO_1610) {
610 /* Disable wake-up during idle for dynamic tick */
611 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
612 __raw_writel(1 << offset, reg);
615 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
616 if (bank->method == METHOD_GPIO_24XX) {
617 /* Disable wake-up during idle for dynamic tick */
618 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
619 __raw_writel(1 << offset, reg);
622 #ifdef CONFIG_ARCH_OMAP4
623 if (bank->method == METHOD_GPIO_44XX) {
624 /* Disable wake-up during idle for dynamic tick */
625 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
626 __raw_writel(1 << offset, reg);
629 if (!cpu_class_is_omap1()) {
630 bank->mod_usage &= ~(1 << offset);
631 if (!bank->mod_usage) {
632 void __iomem *reg = bank->base;
635 if (cpu_is_omap24xx() || cpu_is_omap34xx())
636 reg += OMAP24XX_GPIO_CTRL;
637 else if (cpu_is_omap44xx())
638 reg += OMAP4_GPIO_CTRL;
639 ctrl = __raw_readl(reg);
640 /* Module is disabled, clocks are gated */
642 __raw_writel(ctrl, reg);
645 _reset_gpio(bank, bank->chip.base + offset);
646 spin_unlock_irqrestore(&bank->lock, flags);
650 * We need to unmask the GPIO bank interrupt as soon as possible to
651 * avoid missing GPIO interrupts for other lines in the bank.
652 * Then we need to mask-read-clear-unmask the triggered GPIO lines
653 * in the bank to avoid missing nested interrupts for a GPIO line.
654 * If we wait to unmask individual GPIO lines in the bank after the
655 * line's interrupt handler has been run, we may miss some nested
658 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
660 void __iomem *isr_reg = NULL;
662 unsigned int gpio_irq, gpio_index;
663 struct gpio_bank *bank;
666 struct irq_chip *chip = irq_desc_get_chip(desc);
668 chained_irq_enter(chip, desc);
670 bank = irq_get_handler_data(irq);
671 isr_reg = bank->base + bank->regs->irqstatus;
673 if (WARN_ON(!isr_reg))
677 u32 isr_saved, level_mask = 0;
680 enabled = _get_gpio_irqbank_mask(bank);
681 isr_saved = isr = __raw_readl(isr_reg) & enabled;
683 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
686 if (cpu_class_is_omap2()) {
687 level_mask = bank->level_mask & enabled;
690 /* clear edge sensitive interrupts before handler(s) are
691 called so that we don't miss any interrupt occurred while
693 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
694 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
695 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
697 /* if there is only edge sensitive GPIO pin interrupts
698 configured, we could unmask GPIO bank interrupt immediately */
699 if (!level_mask && !unmasked) {
701 chained_irq_exit(chip, desc);
709 gpio_irq = bank->virtual_irq_start;
710 for (; isr != 0; isr >>= 1, gpio_irq++) {
711 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
716 #ifdef CONFIG_ARCH_OMAP1
718 * Some chips can't respond to both rising and falling
719 * at the same time. If this irq was requested with
720 * both flags, we need to flip the ICR data for the IRQ
721 * to respond to the IRQ for the opposite direction.
722 * This will be indicated in the bank toggle_mask.
724 if (bank->toggle_mask & (1 << gpio_index))
725 _toggle_gpio_edge_triggering(bank, gpio_index);
728 generic_handle_irq(gpio_irq);
731 /* if bank has any level sensitive GPIO pin interrupt
732 configured, we must unmask the bank interrupt only after
733 handler(s) are executed in order to avoid spurious bank
737 chained_irq_exit(chip, desc);
740 static void gpio_irq_shutdown(struct irq_data *d)
742 unsigned int gpio = d->irq - IH_GPIO_BASE;
743 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
746 spin_lock_irqsave(&bank->lock, flags);
747 _reset_gpio(bank, gpio);
748 spin_unlock_irqrestore(&bank->lock, flags);
751 static void gpio_ack_irq(struct irq_data *d)
753 unsigned int gpio = d->irq - IH_GPIO_BASE;
754 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
756 _clear_gpio_irqstatus(bank, gpio);
759 static void gpio_mask_irq(struct irq_data *d)
761 unsigned int gpio = d->irq - IH_GPIO_BASE;
762 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
765 spin_lock_irqsave(&bank->lock, flags);
766 _set_gpio_irqenable(bank, gpio, 0);
767 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
768 spin_unlock_irqrestore(&bank->lock, flags);
771 static void gpio_unmask_irq(struct irq_data *d)
773 unsigned int gpio = d->irq - IH_GPIO_BASE;
774 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
775 unsigned int irq_mask = GPIO_BIT(bank, gpio);
776 u32 trigger = irqd_get_trigger_type(d);
779 spin_lock_irqsave(&bank->lock, flags);
781 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
783 /* For level-triggered GPIOs, the clearing must be done after
784 * the HW source is cleared, thus after the handler has run */
785 if (bank->level_mask & irq_mask) {
786 _set_gpio_irqenable(bank, gpio, 0);
787 _clear_gpio_irqstatus(bank, gpio);
790 _set_gpio_irqenable(bank, gpio, 1);
791 spin_unlock_irqrestore(&bank->lock, flags);
794 static struct irq_chip gpio_irq_chip = {
796 .irq_shutdown = gpio_irq_shutdown,
797 .irq_ack = gpio_ack_irq,
798 .irq_mask = gpio_mask_irq,
799 .irq_unmask = gpio_unmask_irq,
800 .irq_set_type = gpio_irq_type,
801 .irq_set_wake = gpio_wake_enable,
804 /*---------------------------------------------------------------------*/
806 #ifdef CONFIG_ARCH_OMAP1
808 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
810 #ifdef CONFIG_ARCH_OMAP16XX
812 #include <linux/platform_device.h>
814 static int omap_mpuio_suspend_noirq(struct device *dev)
816 struct platform_device *pdev = to_platform_device(dev);
817 struct gpio_bank *bank = platform_get_drvdata(pdev);
818 void __iomem *mask_reg = bank->base +
819 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
822 spin_lock_irqsave(&bank->lock, flags);
823 bank->saved_wakeup = __raw_readl(mask_reg);
824 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
825 spin_unlock_irqrestore(&bank->lock, flags);
830 static int omap_mpuio_resume_noirq(struct device *dev)
832 struct platform_device *pdev = to_platform_device(dev);
833 struct gpio_bank *bank = platform_get_drvdata(pdev);
834 void __iomem *mask_reg = bank->base +
835 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
838 spin_lock_irqsave(&bank->lock, flags);
839 __raw_writel(bank->saved_wakeup, mask_reg);
840 spin_unlock_irqrestore(&bank->lock, flags);
845 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
846 .suspend_noirq = omap_mpuio_suspend_noirq,
847 .resume_noirq = omap_mpuio_resume_noirq,
850 /* use platform_driver for this. */
851 static struct platform_driver omap_mpuio_driver = {
854 .pm = &omap_mpuio_dev_pm_ops,
858 static struct platform_device omap_mpuio_device = {
862 .driver = &omap_mpuio_driver.driver,
864 /* could list the /proc/iomem resources */
867 static inline void mpuio_init(void)
869 struct gpio_bank *bank = &gpio_bank[0];
870 platform_set_drvdata(&omap_mpuio_device, bank);
872 if (platform_driver_register(&omap_mpuio_driver) == 0)
873 (void) platform_device_register(&omap_mpuio_device);
877 static inline void mpuio_init(void) {}
882 #define bank_is_mpuio(bank) 0
883 static inline void mpuio_init(void) {}
887 /*---------------------------------------------------------------------*/
889 /* REVISIT these are stupid implementations! replace by ones that
890 * don't switch on METHOD_* and which mostly avoid spinlocks
893 static int gpio_input(struct gpio_chip *chip, unsigned offset)
895 struct gpio_bank *bank;
898 bank = container_of(chip, struct gpio_bank, chip);
899 spin_lock_irqsave(&bank->lock, flags);
900 _set_gpio_direction(bank, offset, 1);
901 spin_unlock_irqrestore(&bank->lock, flags);
905 static int gpio_is_input(struct gpio_bank *bank, int mask)
907 void __iomem *reg = bank->base + bank->regs->direction;
909 return __raw_readl(reg) & mask;
912 static int gpio_get(struct gpio_chip *chip, unsigned offset)
914 struct gpio_bank *bank;
919 gpio = chip->base + offset;
920 bank = container_of(chip, struct gpio_bank, chip);
922 mask = GPIO_BIT(bank, gpio);
924 if (gpio_is_input(bank, mask))
925 return _get_gpio_datain(bank, gpio);
927 return _get_gpio_dataout(bank, gpio);
930 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
932 struct gpio_bank *bank;
935 bank = container_of(chip, struct gpio_bank, chip);
936 spin_lock_irqsave(&bank->lock, flags);
937 bank->set_dataout(bank, offset, value);
938 _set_gpio_direction(bank, offset, 0);
939 spin_unlock_irqrestore(&bank->lock, flags);
943 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
946 struct gpio_bank *bank;
949 bank = container_of(chip, struct gpio_bank, chip);
952 bank->dbck = clk_get(bank->dev, "dbclk");
953 if (IS_ERR(bank->dbck))
954 dev_err(bank->dev, "Could not get gpio dbck\n");
957 spin_lock_irqsave(&bank->lock, flags);
958 _set_gpio_debounce(bank, offset, debounce);
959 spin_unlock_irqrestore(&bank->lock, flags);
964 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
966 struct gpio_bank *bank;
969 bank = container_of(chip, struct gpio_bank, chip);
970 spin_lock_irqsave(&bank->lock, flags);
971 bank->set_dataout(bank, offset, value);
972 spin_unlock_irqrestore(&bank->lock, flags);
975 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
977 struct gpio_bank *bank;
979 bank = container_of(chip, struct gpio_bank, chip);
980 return bank->virtual_irq_start + offset;
983 /*---------------------------------------------------------------------*/
985 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
989 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
990 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
991 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
992 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
993 else if (cpu_is_omap44xx())
994 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
998 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
999 (rev >> 4) & 0x0f, rev & 0x0f);
1002 /* This lock class tells lockdep that GPIO irqs are in a different
1003 * category than their parents, so it won't report false recursion.
1005 static struct lock_class_key gpio_lock_class;
1007 static inline int init_gpio_info(struct platform_device *pdev)
1009 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1010 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1013 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1019 /* TODO: Cleanup cpu_is_* checks */
1020 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1022 if (cpu_class_is_omap2()) {
1023 if (cpu_is_omap44xx()) {
1024 __raw_writel(0xffffffff, bank->base +
1025 OMAP4_GPIO_IRQSTATUSCLR0);
1026 __raw_writel(0x00000000, bank->base +
1027 OMAP4_GPIO_DEBOUNCENABLE);
1028 /* Initialize interface clk ungated, module enabled */
1029 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1030 } else if (cpu_is_omap34xx()) {
1031 __raw_writel(0x00000000, bank->base +
1032 OMAP24XX_GPIO_IRQENABLE1);
1033 __raw_writel(0xffffffff, bank->base +
1034 OMAP24XX_GPIO_IRQSTATUS1);
1035 __raw_writel(0x00000000, bank->base +
1036 OMAP24XX_GPIO_DEBOUNCE_EN);
1038 /* Initialize interface clk ungated, module enabled */
1039 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1040 } else if (cpu_is_omap24xx()) {
1041 static const u32 non_wakeup_gpios[] = {
1042 0xe203ffc0, 0x08700040
1044 if (id < ARRAY_SIZE(non_wakeup_gpios))
1045 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1047 } else if (cpu_class_is_omap1()) {
1048 if (bank_is_mpuio(bank))
1049 __raw_writew(0xffff, bank->base +
1050 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1051 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1052 __raw_writew(0xffff, bank->base
1053 + OMAP1510_GPIO_INT_MASK);
1054 __raw_writew(0x0000, bank->base
1055 + OMAP1510_GPIO_INT_STATUS);
1057 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1058 __raw_writew(0x0000, bank->base
1059 + OMAP1610_GPIO_IRQENABLE1);
1060 __raw_writew(0xffff, bank->base
1061 + OMAP1610_GPIO_IRQSTATUS1);
1062 __raw_writew(0x0014, bank->base
1063 + OMAP1610_GPIO_SYSCONFIG);
1066 * Enable system clock for GPIO module.
1067 * The CAM_CLK_CTRL *is* really the right place.
1069 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1072 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1073 __raw_writel(0xffffffff, bank->base
1074 + OMAP7XX_GPIO_INT_MASK);
1075 __raw_writel(0x00000000, bank->base
1076 + OMAP7XX_GPIO_INT_STATUS);
1082 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1085 struct irq_chip_generic *gc;
1086 struct irq_chip_type *ct;
1088 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1090 ct = gc->chip_types;
1092 /* NOTE: No ack required, reading IRQ status clears it. */
1093 ct->chip.irq_mask = irq_gc_mask_set_bit;
1094 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1095 ct->chip.irq_set_type = gpio_irq_type;
1096 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1097 if (cpu_is_omap16xx())
1098 ct->chip.irq_set_wake = gpio_wake_enable,
1100 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1101 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1102 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1105 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1110 bank->mod_usage = 0;
1112 * REVISIT eventually switch from OMAP-specific gpio structs
1113 * over to the generic ones
1115 bank->chip.request = omap_gpio_request;
1116 bank->chip.free = omap_gpio_free;
1117 bank->chip.direction_input = gpio_input;
1118 bank->chip.get = gpio_get;
1119 bank->chip.direction_output = gpio_output;
1120 bank->chip.set_debounce = gpio_debounce;
1121 bank->chip.set = gpio_set;
1122 bank->chip.to_irq = gpio_2irq;
1123 if (bank_is_mpuio(bank)) {
1124 bank->chip.label = "mpuio";
1125 #ifdef CONFIG_ARCH_OMAP16XX
1126 bank->chip.dev = &omap_mpuio_device.dev;
1128 bank->chip.base = OMAP_MPUIO(0);
1130 bank->chip.label = "gpio";
1131 bank->chip.base = gpio;
1132 gpio += bank->width;
1134 bank->chip.ngpio = bank->width;
1136 gpiochip_add(&bank->chip);
1138 for (j = bank->virtual_irq_start;
1139 j < bank->virtual_irq_start + bank->width; j++) {
1140 irq_set_lockdep_class(j, &gpio_lock_class);
1141 irq_set_chip_data(j, bank);
1142 if (bank_is_mpuio(bank)) {
1143 omap_mpuio_alloc_gc(bank, j, bank->width);
1145 irq_set_chip(j, &gpio_irq_chip);
1146 irq_set_handler(j, handle_simple_irq);
1147 set_irq_flags(j, IRQF_VALID);
1150 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1151 irq_set_handler_data(bank->irq, bank);
1154 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1156 static int gpio_init_done;
1157 struct omap_gpio_platform_data *pdata;
1158 struct resource *res;
1160 struct gpio_bank *bank;
1162 if (!pdev->dev.platform_data)
1165 pdata = pdev->dev.platform_data;
1167 if (!gpio_init_done) {
1170 ret = init_gpio_info(pdev);
1176 bank = &gpio_bank[id];
1178 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1179 if (unlikely(!res)) {
1180 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1184 bank->irq = res->start;
1185 bank->virtual_irq_start = pdata->virtual_irq_start;
1186 bank->method = pdata->bank_type;
1187 bank->dev = &pdev->dev;
1188 bank->dbck_flag = pdata->dbck_flag;
1189 bank->stride = pdata->bank_stride;
1190 bank->width = pdata->bank_width;
1192 bank->regs = pdata->regs;
1194 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1195 bank->set_dataout = _set_gpio_dataout_reg;
1197 bank->set_dataout = _set_gpio_dataout_mask;
1199 spin_lock_init(&bank->lock);
1201 /* Static mapping, never released */
1202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1203 if (unlikely(!res)) {
1204 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1208 bank->base = ioremap(res->start, resource_size(res));
1210 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1214 pm_runtime_enable(bank->dev);
1215 pm_runtime_get_sync(bank->dev);
1217 omap_gpio_mod_init(bank, id);
1218 omap_gpio_chip_init(bank);
1219 omap_gpio_show_rev(bank);
1221 if (!gpio_init_done)
1227 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1228 static int omap_gpio_suspend(void)
1232 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1235 for (i = 0; i < gpio_bank_count; i++) {
1236 struct gpio_bank *bank = &gpio_bank[i];
1237 void __iomem *wake_status;
1238 void __iomem *wake_clear;
1239 void __iomem *wake_set;
1240 unsigned long flags;
1242 switch (bank->method) {
1243 #ifdef CONFIG_ARCH_OMAP16XX
1244 case METHOD_GPIO_1610:
1245 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1246 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1247 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1250 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1251 case METHOD_GPIO_24XX:
1252 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1253 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1254 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1257 #ifdef CONFIG_ARCH_OMAP4
1258 case METHOD_GPIO_44XX:
1259 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1260 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1261 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1268 spin_lock_irqsave(&bank->lock, flags);
1269 bank->saved_wakeup = __raw_readl(wake_status);
1270 __raw_writel(0xffffffff, wake_clear);
1271 __raw_writel(bank->suspend_wakeup, wake_set);
1272 spin_unlock_irqrestore(&bank->lock, flags);
1278 static void omap_gpio_resume(void)
1282 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1285 for (i = 0; i < gpio_bank_count; i++) {
1286 struct gpio_bank *bank = &gpio_bank[i];
1287 void __iomem *wake_clear;
1288 void __iomem *wake_set;
1289 unsigned long flags;
1291 switch (bank->method) {
1292 #ifdef CONFIG_ARCH_OMAP16XX
1293 case METHOD_GPIO_1610:
1294 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1295 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1298 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1299 case METHOD_GPIO_24XX:
1300 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1301 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1304 #ifdef CONFIG_ARCH_OMAP4
1305 case METHOD_GPIO_44XX:
1306 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1307 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1314 spin_lock_irqsave(&bank->lock, flags);
1315 __raw_writel(0xffffffff, wake_clear);
1316 __raw_writel(bank->saved_wakeup, wake_set);
1317 spin_unlock_irqrestore(&bank->lock, flags);
1321 static struct syscore_ops omap_gpio_syscore_ops = {
1322 .suspend = omap_gpio_suspend,
1323 .resume = omap_gpio_resume,
1328 #ifdef CONFIG_ARCH_OMAP2PLUS
1330 static int workaround_enabled;
1332 void omap2_gpio_prepare_for_idle(int off_mode)
1337 if (cpu_is_omap34xx())
1340 for (i = min; i < gpio_bank_count; i++) {
1341 struct gpio_bank *bank = &gpio_bank[i];
1345 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1346 clk_disable(bank->dbck);
1351 /* If going to OFF, remove triggering for all
1352 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1353 * generated. See OMAP2420 Errata item 1.101. */
1354 if (!(bank->enabled_non_wakeup_gpios))
1357 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1358 bank->saved_datain = __raw_readl(bank->base +
1359 OMAP24XX_GPIO_DATAIN);
1360 l1 = __raw_readl(bank->base +
1361 OMAP24XX_GPIO_FALLINGDETECT);
1362 l2 = __raw_readl(bank->base +
1363 OMAP24XX_GPIO_RISINGDETECT);
1366 if (cpu_is_omap44xx()) {
1367 bank->saved_datain = __raw_readl(bank->base +
1369 l1 = __raw_readl(bank->base +
1370 OMAP4_GPIO_FALLINGDETECT);
1371 l2 = __raw_readl(bank->base +
1372 OMAP4_GPIO_RISINGDETECT);
1375 bank->saved_fallingdetect = l1;
1376 bank->saved_risingdetect = l2;
1377 l1 &= ~bank->enabled_non_wakeup_gpios;
1378 l2 &= ~bank->enabled_non_wakeup_gpios;
1380 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1381 __raw_writel(l1, bank->base +
1382 OMAP24XX_GPIO_FALLINGDETECT);
1383 __raw_writel(l2, bank->base +
1384 OMAP24XX_GPIO_RISINGDETECT);
1387 if (cpu_is_omap44xx()) {
1388 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1389 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1395 workaround_enabled = 0;
1398 workaround_enabled = 1;
1401 void omap2_gpio_resume_after_idle(void)
1406 if (cpu_is_omap34xx())
1408 for (i = min; i < gpio_bank_count; i++) {
1409 struct gpio_bank *bank = &gpio_bank[i];
1410 u32 l = 0, gen, gen0, gen1;
1413 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1414 clk_enable(bank->dbck);
1416 if (!workaround_enabled)
1419 if (!(bank->enabled_non_wakeup_gpios))
1422 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1423 __raw_writel(bank->saved_fallingdetect,
1424 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1425 __raw_writel(bank->saved_risingdetect,
1426 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1427 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1430 if (cpu_is_omap44xx()) {
1431 __raw_writel(bank->saved_fallingdetect,
1432 bank->base + OMAP4_GPIO_FALLINGDETECT);
1433 __raw_writel(bank->saved_risingdetect,
1434 bank->base + OMAP4_GPIO_RISINGDETECT);
1435 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1438 /* Check if any of the non-wakeup interrupt GPIOs have changed
1439 * state. If so, generate an IRQ by software. This is
1440 * horribly racy, but it's the best we can do to work around
1441 * this silicon bug. */
1442 l ^= bank->saved_datain;
1443 l &= bank->enabled_non_wakeup_gpios;
1446 * No need to generate IRQs for the rising edge for gpio IRQs
1447 * configured with falling edge only; and vice versa.
1449 gen0 = l & bank->saved_fallingdetect;
1450 gen0 &= bank->saved_datain;
1452 gen1 = l & bank->saved_risingdetect;
1453 gen1 &= ~(bank->saved_datain);
1455 /* FIXME: Consider GPIO IRQs with level detections properly! */
1456 gen = l & (~(bank->saved_fallingdetect) &
1457 ~(bank->saved_risingdetect));
1458 /* Consider all GPIO IRQs needed to be updated */
1464 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1465 old0 = __raw_readl(bank->base +
1466 OMAP24XX_GPIO_LEVELDETECT0);
1467 old1 = __raw_readl(bank->base +
1468 OMAP24XX_GPIO_LEVELDETECT1);
1469 __raw_writel(old0 | gen, bank->base +
1470 OMAP24XX_GPIO_LEVELDETECT0);
1471 __raw_writel(old1 | gen, bank->base +
1472 OMAP24XX_GPIO_LEVELDETECT1);
1473 __raw_writel(old0, bank->base +
1474 OMAP24XX_GPIO_LEVELDETECT0);
1475 __raw_writel(old1, bank->base +
1476 OMAP24XX_GPIO_LEVELDETECT1);
1479 if (cpu_is_omap44xx()) {
1480 old0 = __raw_readl(bank->base +
1481 OMAP4_GPIO_LEVELDETECT0);
1482 old1 = __raw_readl(bank->base +
1483 OMAP4_GPIO_LEVELDETECT1);
1484 __raw_writel(old0 | l, bank->base +
1485 OMAP4_GPIO_LEVELDETECT0);
1486 __raw_writel(old1 | l, bank->base +
1487 OMAP4_GPIO_LEVELDETECT1);
1488 __raw_writel(old0, bank->base +
1489 OMAP4_GPIO_LEVELDETECT0);
1490 __raw_writel(old1, bank->base +
1491 OMAP4_GPIO_LEVELDETECT1);
1500 #ifdef CONFIG_ARCH_OMAP3
1501 /* save the registers of bank 2-6 */
1502 void omap_gpio_save_context(void)
1506 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1507 for (i = 1; i < gpio_bank_count; i++) {
1508 struct gpio_bank *bank = &gpio_bank[i];
1509 gpio_context[i].irqenable1 =
1510 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1511 gpio_context[i].irqenable2 =
1512 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1513 gpio_context[i].wake_en =
1514 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1515 gpio_context[i].ctrl =
1516 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1517 gpio_context[i].oe =
1518 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1519 gpio_context[i].leveldetect0 =
1520 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1521 gpio_context[i].leveldetect1 =
1522 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1523 gpio_context[i].risingdetect =
1524 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1525 gpio_context[i].fallingdetect =
1526 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1527 gpio_context[i].dataout =
1528 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1532 /* restore the required registers of bank 2-6 */
1533 void omap_gpio_restore_context(void)
1537 for (i = 1; i < gpio_bank_count; i++) {
1538 struct gpio_bank *bank = &gpio_bank[i];
1539 __raw_writel(gpio_context[i].irqenable1,
1540 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1541 __raw_writel(gpio_context[i].irqenable2,
1542 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1543 __raw_writel(gpio_context[i].wake_en,
1544 bank->base + OMAP24XX_GPIO_WAKE_EN);
1545 __raw_writel(gpio_context[i].ctrl,
1546 bank->base + OMAP24XX_GPIO_CTRL);
1547 __raw_writel(gpio_context[i].oe,
1548 bank->base + OMAP24XX_GPIO_OE);
1549 __raw_writel(gpio_context[i].leveldetect0,
1550 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1551 __raw_writel(gpio_context[i].leveldetect1,
1552 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1553 __raw_writel(gpio_context[i].risingdetect,
1554 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1555 __raw_writel(gpio_context[i].fallingdetect,
1556 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1557 __raw_writel(gpio_context[i].dataout,
1558 bank->base + OMAP24XX_GPIO_DATAOUT);
1563 static struct platform_driver omap_gpio_driver = {
1564 .probe = omap_gpio_probe,
1566 .name = "omap_gpio",
1571 * gpio driver register needs to be done before
1572 * machine_init functions access gpio APIs.
1573 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1575 static int __init omap_gpio_drv_reg(void)
1577 return platform_driver_register(&omap_gpio_driver);
1579 postcore_initcall(omap_gpio_drv_reg);
1581 static int __init omap_gpio_sysinit(void)
1585 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1586 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1587 register_syscore_ops(&omap_gpio_syscore_ops);
1593 arch_initcall(omap_gpio_sysinit);