2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/of_device.h>
27 #include <linux/irqdomain.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/gpio.h>
30 #include <linux/platform_data/gpio-omap.h>
34 static LIST_HEAD(omap_gpio_list);
52 struct list_head node;
55 struct irq_domain *domain;
57 u32 enabled_non_wakeup_gpios;
58 struct gpio_regs context;
63 struct gpio_chip chip;
75 int context_loss_count;
77 bool workaround_enabled;
79 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
80 int (*get_context_loss_count)(struct device *dev);
82 struct omap_gpio_reg_offs *regs;
85 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
86 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
87 #define GPIO_MOD_CTRL_BIT BIT(0)
89 static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
91 return bank->chip.base + gpio_irq;
94 static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
96 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
98 return irq_find_mapping(bank->domain, offset);
101 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
103 void __iomem *reg = bank->base;
106 reg += bank->regs->direction;
107 l = __raw_readl(reg);
112 __raw_writel(l, reg);
113 bank->context.oe = l;
117 /* set data out value using dedicate set/clear register */
118 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
120 void __iomem *reg = bank->base;
121 u32 l = GPIO_BIT(bank, gpio);
124 reg += bank->regs->set_dataout;
125 bank->context.dataout |= l;
127 reg += bank->regs->clr_dataout;
128 bank->context.dataout &= ~l;
131 __raw_writel(l, reg);
134 /* set data out value using mask register */
135 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = GPIO_BIT(bank, gpio);
141 l = __raw_readl(reg);
146 __raw_writel(l, reg);
147 bank->context.dataout = l;
150 static int _get_gpio_datain(struct gpio_bank *bank, int offset)
152 void __iomem *reg = bank->base + bank->regs->datain;
154 return (__raw_readl(reg) & (1 << offset)) != 0;
157 static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
159 void __iomem *reg = bank->base + bank->regs->dataout;
161 return (__raw_readl(reg) & (1 << offset)) != 0;
164 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
166 int l = __raw_readl(base + reg);
173 __raw_writel(l, base + reg);
176 static inline void _gpio_dbck_enable(struct gpio_bank *bank)
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
182 __raw_writel(bank->dbck_enable_mask,
183 bank->base + bank->regs->debounce_en);
187 static inline void _gpio_dbck_disable(struct gpio_bank *bank)
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
195 __raw_writel(0, bank->base + bank->regs->debounce_en);
197 clk_disable(bank->dbck);
198 bank->dbck_enabled = false;
203 * _set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @gpio: the gpio number on this @gpio
206 * @debounce: debounce time to use
208 * OMAP's debounce time is in 31us steps so we need
209 * to convert and round up to the closest unit.
211 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
218 if (!bank->dbck_flag)
223 else if (debounce > 7936)
226 debounce = (debounce / 0x1f) - 1;
228 l = GPIO_BIT(bank, gpio);
230 clk_enable(bank->dbck);
231 reg = bank->base + bank->regs->debounce;
232 __raw_writel(debounce, reg);
234 reg = bank->base + bank->regs->debounce_en;
235 val = __raw_readl(reg);
241 bank->dbck_enable_mask = val;
243 __raw_writel(val, reg);
244 clk_disable(bank->dbck);
246 * Enable debounce clock per module.
247 * This call is mandatory because in omap_gpio_request() when
248 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
249 * runtime callbck fails to turn on dbck because dbck_enable_mask
250 * used within _gpio_dbck_enable() is still not initialized at
251 * that point. Therefore we have to enable dbck here.
253 _gpio_dbck_enable(bank);
254 if (bank->dbck_enable_mask) {
255 bank->context.debounce = debounce;
256 bank->context.debounce_en = val;
261 * _clear_gpio_debounce - clear debounce settings for a gpio
262 * @bank: the gpio bank we're acting upon
263 * @gpio: the gpio number on this @gpio
265 * If a gpio is using debounce, then clear the debounce enable bit and if
266 * this is the only gpio in this bank using debounce, then clear the debounce
267 * time too. The debounce clock will also be disabled when calling this function
268 * if this is the only gpio in the bank using debounce.
270 static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
272 u32 gpio_bit = GPIO_BIT(bank, gpio);
274 if (!bank->dbck_flag)
277 if (!(bank->dbck_enable_mask & gpio_bit))
280 bank->dbck_enable_mask &= ~gpio_bit;
281 bank->context.debounce_en &= ~gpio_bit;
282 __raw_writel(bank->context.debounce_en,
283 bank->base + bank->regs->debounce_en);
285 if (!bank->dbck_enable_mask) {
286 bank->context.debounce = 0;
287 __raw_writel(bank->context.debounce, bank->base +
288 bank->regs->debounce);
289 clk_disable(bank->dbck);
290 bank->dbck_enabled = false;
294 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
297 void __iomem *base = bank->base;
298 u32 gpio_bit = 1 << gpio;
300 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
301 trigger & IRQ_TYPE_LEVEL_LOW);
302 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
303 trigger & IRQ_TYPE_LEVEL_HIGH);
304 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
305 trigger & IRQ_TYPE_EDGE_RISING);
306 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
307 trigger & IRQ_TYPE_EDGE_FALLING);
309 bank->context.leveldetect0 =
310 __raw_readl(bank->base + bank->regs->leveldetect0);
311 bank->context.leveldetect1 =
312 __raw_readl(bank->base + bank->regs->leveldetect1);
313 bank->context.risingdetect =
314 __raw_readl(bank->base + bank->regs->risingdetect);
315 bank->context.fallingdetect =
316 __raw_readl(bank->base + bank->regs->fallingdetect);
318 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
319 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
320 bank->context.wake_en =
321 __raw_readl(bank->base + bank->regs->wkup_en);
324 /* This part needs to be executed always for OMAP{34xx, 44xx} */
325 if (!bank->regs->irqctrl) {
326 /* On omap24xx proceed only when valid GPIO bit is set */
327 if (bank->non_wakeup_gpios) {
328 if (!(bank->non_wakeup_gpios & gpio_bit))
333 * Log the edge gpio and manually trigger the IRQ
334 * after resume if the input level changes
335 * to avoid irq lost during PER RET/OFF mode
336 * Applies for omap2 non-wakeup gpio and all omap3 gpios
338 if (trigger & IRQ_TYPE_EDGE_BOTH)
339 bank->enabled_non_wakeup_gpios |= gpio_bit;
341 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
346 __raw_readl(bank->base + bank->regs->leveldetect0) |
347 __raw_readl(bank->base + bank->regs->leveldetect1);
350 #ifdef CONFIG_ARCH_OMAP1
352 * This only applies to chips that can't do both rising and falling edge
353 * detection at once. For all other chips, this function is a noop.
355 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
357 void __iomem *reg = bank->base;
360 if (!bank->regs->irqctrl)
363 reg += bank->regs->irqctrl;
365 l = __raw_readl(reg);
371 __raw_writel(l, reg);
374 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
377 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
380 void __iomem *reg = bank->base;
381 void __iomem *base = bank->base;
384 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
385 set_gpio_trigger(bank, gpio, trigger);
386 } else if (bank->regs->irqctrl) {
387 reg += bank->regs->irqctrl;
389 l = __raw_readl(reg);
390 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
391 bank->toggle_mask |= 1 << gpio;
392 if (trigger & IRQ_TYPE_EDGE_RISING)
394 else if (trigger & IRQ_TYPE_EDGE_FALLING)
399 __raw_writel(l, reg);
400 } else if (bank->regs->edgectrl1) {
402 reg += bank->regs->edgectrl2;
404 reg += bank->regs->edgectrl1;
407 l = __raw_readl(reg);
408 l &= ~(3 << (gpio << 1));
409 if (trigger & IRQ_TYPE_EDGE_RISING)
410 l |= 2 << (gpio << 1);
411 if (trigger & IRQ_TYPE_EDGE_FALLING)
412 l |= 1 << (gpio << 1);
414 /* Enable wake-up during idle for dynamic tick */
415 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
416 bank->context.wake_en =
417 __raw_readl(bank->base + bank->regs->wkup_en);
418 __raw_writel(l, reg);
423 static int gpio_irq_type(struct irq_data *d, unsigned type)
425 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
430 if (WARN_ON(!bank->mod_usage))
433 #ifdef CONFIG_ARCH_OMAP1
434 if (d->irq > IH_MPUIO_BASE)
435 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
439 gpio = irq_to_gpio(bank, d->hwirq);
441 if (type & ~IRQ_TYPE_SENSE_MASK)
444 if (!bank->regs->leveldetect0 &&
445 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
448 spin_lock_irqsave(&bank->lock, flags);
449 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
450 spin_unlock_irqrestore(&bank->lock, flags);
452 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
453 __irq_set_handler_locked(d->irq, handle_level_irq);
454 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
455 __irq_set_handler_locked(d->irq, handle_edge_irq);
460 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
462 void __iomem *reg = bank->base;
464 reg += bank->regs->irqstatus;
465 __raw_writel(gpio_mask, reg);
467 /* Workaround for clearing DSP GPIO interrupts to allow retention */
468 if (bank->regs->irqstatus2) {
469 reg = bank->base + bank->regs->irqstatus2;
470 __raw_writel(gpio_mask, reg);
473 /* Flush posted write for the irq status to avoid spurious interrupts */
477 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
479 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
482 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
484 void __iomem *reg = bank->base;
486 u32 mask = (1 << bank->width) - 1;
488 reg += bank->regs->irqenable;
489 l = __raw_readl(reg);
490 if (bank->regs->irqenable_inv)
496 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
498 void __iomem *reg = bank->base;
501 if (bank->regs->set_irqenable) {
502 reg += bank->regs->set_irqenable;
504 bank->context.irqenable1 |= gpio_mask;
506 reg += bank->regs->irqenable;
507 l = __raw_readl(reg);
508 if (bank->regs->irqenable_inv)
512 bank->context.irqenable1 = l;
515 __raw_writel(l, reg);
518 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
520 void __iomem *reg = bank->base;
523 if (bank->regs->clr_irqenable) {
524 reg += bank->regs->clr_irqenable;
526 bank->context.irqenable1 &= ~gpio_mask;
528 reg += bank->regs->irqenable;
529 l = __raw_readl(reg);
530 if (bank->regs->irqenable_inv)
534 bank->context.irqenable1 = l;
537 __raw_writel(l, reg);
540 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
543 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
545 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
549 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
550 * 1510 does not seem to have a wake-up register. If JTAG is connected
551 * to the target, system will wake up always on GPIO events. While
552 * system is running all registered GPIO interrupts need to have wake-up
553 * enabled. When system is suspended, only selected GPIO interrupts need
554 * to have wake-up enabled.
556 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
558 u32 gpio_bit = GPIO_BIT(bank, gpio);
561 if (bank->non_wakeup_gpios & gpio_bit) {
563 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
567 spin_lock_irqsave(&bank->lock, flags);
569 bank->context.wake_en |= gpio_bit;
571 bank->context.wake_en &= ~gpio_bit;
573 __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
574 spin_unlock_irqrestore(&bank->lock, flags);
579 static void _reset_gpio(struct gpio_bank *bank, int gpio)
581 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
582 _set_gpio_irqenable(bank, gpio, 0);
583 _clear_gpio_irqstatus(bank, gpio);
584 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
585 _clear_gpio_debounce(bank, gpio);
588 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
589 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
591 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
592 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
594 return _set_gpio_wakeup(bank, gpio, enable);
597 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
599 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
603 * If this is the first gpio_request for the bank,
604 * enable the bank module.
606 if (!bank->mod_usage)
607 pm_runtime_get_sync(bank->dev);
609 spin_lock_irqsave(&bank->lock, flags);
610 /* Set trigger to none. You need to enable the desired trigger with
611 * request_irq() or set_irq_type().
613 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
615 if (bank->regs->pinctrl) {
616 void __iomem *reg = bank->base + bank->regs->pinctrl;
618 /* Claim the pin for MPU */
619 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
622 if (bank->regs->ctrl && !bank->mod_usage) {
623 void __iomem *reg = bank->base + bank->regs->ctrl;
626 ctrl = __raw_readl(reg);
627 /* Module is enabled, clocks are not gated */
628 ctrl &= ~GPIO_MOD_CTRL_BIT;
629 __raw_writel(ctrl, reg);
630 bank->context.ctrl = ctrl;
633 bank->mod_usage |= 1 << offset;
635 spin_unlock_irqrestore(&bank->lock, flags);
640 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
642 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
643 void __iomem *base = bank->base;
646 spin_lock_irqsave(&bank->lock, flags);
648 if (bank->regs->wkup_en) {
649 /* Disable wake-up during idle for dynamic tick */
650 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
651 bank->context.wake_en =
652 __raw_readl(bank->base + bank->regs->wkup_en);
655 bank->mod_usage &= ~(1 << offset);
657 if (bank->regs->ctrl && !bank->mod_usage) {
658 void __iomem *reg = bank->base + bank->regs->ctrl;
661 ctrl = __raw_readl(reg);
662 /* Module is disabled, clocks are gated */
663 ctrl |= GPIO_MOD_CTRL_BIT;
664 __raw_writel(ctrl, reg);
665 bank->context.ctrl = ctrl;
668 _reset_gpio(bank, bank->chip.base + offset);
669 spin_unlock_irqrestore(&bank->lock, flags);
672 * If this is the last gpio to be freed in the bank,
673 * disable the bank module.
675 if (!bank->mod_usage)
676 pm_runtime_put(bank->dev);
680 * We need to unmask the GPIO bank interrupt as soon as possible to
681 * avoid missing GPIO interrupts for other lines in the bank.
682 * Then we need to mask-read-clear-unmask the triggered GPIO lines
683 * in the bank to avoid missing nested interrupts for a GPIO line.
684 * If we wait to unmask individual GPIO lines in the bank after the
685 * line's interrupt handler has been run, we may miss some nested
688 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
690 void __iomem *isr_reg = NULL;
693 struct gpio_bank *bank;
695 struct irq_chip *chip = irq_desc_get_chip(desc);
697 chained_irq_enter(chip, desc);
699 bank = irq_get_handler_data(irq);
700 isr_reg = bank->base + bank->regs->irqstatus;
701 pm_runtime_get_sync(bank->dev);
703 if (WARN_ON(!isr_reg))
707 u32 isr_saved, level_mask = 0;
710 enabled = _get_gpio_irqbank_mask(bank);
711 isr_saved = isr = __raw_readl(isr_reg) & enabled;
713 if (bank->level_mask)
714 level_mask = bank->level_mask & enabled;
716 /* clear edge sensitive interrupts before handler(s) are
717 called so that we don't miss any interrupt occurred while
719 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
720 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
721 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
723 /* if there is only edge sensitive GPIO pin interrupts
724 configured, we could unmask GPIO bank interrupt immediately */
725 if (!level_mask && !unmasked) {
727 chained_irq_exit(chip, desc);
738 * Some chips can't respond to both rising and falling
739 * at the same time. If this irq was requested with
740 * both flags, we need to flip the ICR data for the IRQ
741 * to respond to the IRQ for the opposite direction.
742 * This will be indicated in the bank toggle_mask.
744 if (bank->toggle_mask & (1 << bit))
745 _toggle_gpio_edge_triggering(bank, bit);
747 generic_handle_irq(irq_find_mapping(bank->domain, bit));
750 /* if bank has any level sensitive GPIO pin interrupt
751 configured, we must unmask the bank interrupt only after
752 handler(s) are executed in order to avoid spurious bank
756 chained_irq_exit(chip, desc);
757 pm_runtime_put(bank->dev);
760 static void gpio_irq_shutdown(struct irq_data *d)
762 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
763 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
766 spin_lock_irqsave(&bank->lock, flags);
767 _reset_gpio(bank, gpio);
768 spin_unlock_irqrestore(&bank->lock, flags);
771 static void gpio_ack_irq(struct irq_data *d)
773 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
774 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
776 _clear_gpio_irqstatus(bank, gpio);
779 static void gpio_mask_irq(struct irq_data *d)
781 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
782 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
785 spin_lock_irqsave(&bank->lock, flags);
786 _set_gpio_irqenable(bank, gpio, 0);
787 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
788 spin_unlock_irqrestore(&bank->lock, flags);
791 static void gpio_unmask_irq(struct irq_data *d)
793 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
794 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
795 unsigned int irq_mask = GPIO_BIT(bank, gpio);
796 u32 trigger = irqd_get_trigger_type(d);
799 spin_lock_irqsave(&bank->lock, flags);
801 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
803 /* For level-triggered GPIOs, the clearing must be done after
804 * the HW source is cleared, thus after the handler has run */
805 if (bank->level_mask & irq_mask) {
806 _set_gpio_irqenable(bank, gpio, 0);
807 _clear_gpio_irqstatus(bank, gpio);
810 _set_gpio_irqenable(bank, gpio, 1);
811 spin_unlock_irqrestore(&bank->lock, flags);
814 static struct irq_chip gpio_irq_chip = {
816 .irq_shutdown = gpio_irq_shutdown,
817 .irq_ack = gpio_ack_irq,
818 .irq_mask = gpio_mask_irq,
819 .irq_unmask = gpio_unmask_irq,
820 .irq_set_type = gpio_irq_type,
821 .irq_set_wake = gpio_wake_enable,
824 /*---------------------------------------------------------------------*/
826 static int omap_mpuio_suspend_noirq(struct device *dev)
828 struct platform_device *pdev = to_platform_device(dev);
829 struct gpio_bank *bank = platform_get_drvdata(pdev);
830 void __iomem *mask_reg = bank->base +
831 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
834 spin_lock_irqsave(&bank->lock, flags);
835 __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
836 spin_unlock_irqrestore(&bank->lock, flags);
841 static int omap_mpuio_resume_noirq(struct device *dev)
843 struct platform_device *pdev = to_platform_device(dev);
844 struct gpio_bank *bank = platform_get_drvdata(pdev);
845 void __iomem *mask_reg = bank->base +
846 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
849 spin_lock_irqsave(&bank->lock, flags);
850 __raw_writel(bank->context.wake_en, mask_reg);
851 spin_unlock_irqrestore(&bank->lock, flags);
856 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
857 .suspend_noirq = omap_mpuio_suspend_noirq,
858 .resume_noirq = omap_mpuio_resume_noirq,
861 /* use platform_driver for this. */
862 static struct platform_driver omap_mpuio_driver = {
865 .pm = &omap_mpuio_dev_pm_ops,
869 static struct platform_device omap_mpuio_device = {
873 .driver = &omap_mpuio_driver.driver,
875 /* could list the /proc/iomem resources */
878 static inline void mpuio_init(struct gpio_bank *bank)
880 platform_set_drvdata(&omap_mpuio_device, bank);
882 if (platform_driver_register(&omap_mpuio_driver) == 0)
883 (void) platform_device_register(&omap_mpuio_device);
886 /*---------------------------------------------------------------------*/
888 static int gpio_input(struct gpio_chip *chip, unsigned offset)
890 struct gpio_bank *bank;
893 bank = container_of(chip, struct gpio_bank, chip);
894 spin_lock_irqsave(&bank->lock, flags);
895 _set_gpio_direction(bank, offset, 1);
896 spin_unlock_irqrestore(&bank->lock, flags);
900 static int gpio_is_input(struct gpio_bank *bank, int mask)
902 void __iomem *reg = bank->base + bank->regs->direction;
904 return __raw_readl(reg) & mask;
907 static int gpio_get(struct gpio_chip *chip, unsigned offset)
909 struct gpio_bank *bank;
912 bank = container_of(chip, struct gpio_bank, chip);
913 mask = (1 << offset);
915 if (gpio_is_input(bank, mask))
916 return _get_gpio_datain(bank, offset);
918 return _get_gpio_dataout(bank, offset);
921 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
923 struct gpio_bank *bank;
926 bank = container_of(chip, struct gpio_bank, chip);
927 spin_lock_irqsave(&bank->lock, flags);
928 bank->set_dataout(bank, offset, value);
929 _set_gpio_direction(bank, offset, 0);
930 spin_unlock_irqrestore(&bank->lock, flags);
934 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
937 struct gpio_bank *bank;
940 bank = container_of(chip, struct gpio_bank, chip);
942 spin_lock_irqsave(&bank->lock, flags);
943 _set_gpio_debounce(bank, offset, debounce);
944 spin_unlock_irqrestore(&bank->lock, flags);
949 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
951 struct gpio_bank *bank;
954 bank = container_of(chip, struct gpio_bank, chip);
955 spin_lock_irqsave(&bank->lock, flags);
956 bank->set_dataout(bank, offset, value);
957 spin_unlock_irqrestore(&bank->lock, flags);
960 /*---------------------------------------------------------------------*/
962 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
967 if (called || bank->regs->revision == USHRT_MAX)
970 rev = __raw_readw(bank->base + bank->regs->revision);
971 pr_info("OMAP GPIO hardware version %d.%d\n",
972 (rev >> 4) & 0x0f, rev & 0x0f);
977 /* This lock class tells lockdep that GPIO irqs are in a different
978 * category than their parents, so it won't report false recursion.
980 static struct lock_class_key gpio_lock_class;
982 static void omap_gpio_mod_init(struct gpio_bank *bank)
984 void __iomem *base = bank->base;
987 if (bank->width == 16)
990 if (bank->is_mpuio) {
991 __raw_writel(l, bank->base + bank->regs->irqenable);
995 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
996 _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
997 if (bank->regs->debounce_en)
998 __raw_writel(0, base + bank->regs->debounce_en);
1000 /* Save OE default value (0xffffffff) in the context */
1001 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
1002 /* Initialize interface clk ungated, module enabled */
1003 if (bank->regs->ctrl)
1004 __raw_writel(0, base + bank->regs->ctrl);
1006 bank->dbck = clk_get(bank->dev, "dbclk");
1007 if (IS_ERR(bank->dbck))
1008 dev_err(bank->dev, "Could not get gpio dbck\n");
1012 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1015 struct irq_chip_generic *gc;
1016 struct irq_chip_type *ct;
1018 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1021 dev_err(bank->dev, "Memory alloc failed for gc\n");
1025 ct = gc->chip_types;
1027 /* NOTE: No ack required, reading IRQ status clears it. */
1028 ct->chip.irq_mask = irq_gc_mask_set_bit;
1029 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1030 ct->chip.irq_set_type = gpio_irq_type;
1032 if (bank->regs->wkup_en)
1033 ct->chip.irq_set_wake = gpio_wake_enable,
1035 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1036 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1037 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1040 static void omap_gpio_chip_init(struct gpio_bank *bank)
1046 * REVISIT eventually switch from OMAP-specific gpio structs
1047 * over to the generic ones
1049 bank->chip.request = omap_gpio_request;
1050 bank->chip.free = omap_gpio_free;
1051 bank->chip.direction_input = gpio_input;
1052 bank->chip.get = gpio_get;
1053 bank->chip.direction_output = gpio_output;
1054 bank->chip.set_debounce = gpio_debounce;
1055 bank->chip.set = gpio_set;
1056 bank->chip.to_irq = omap_gpio_to_irq;
1057 if (bank->is_mpuio) {
1058 bank->chip.label = "mpuio";
1059 if (bank->regs->wkup_en)
1060 bank->chip.dev = &omap_mpuio_device.dev;
1061 bank->chip.base = OMAP_MPUIO(0);
1063 bank->chip.label = "gpio";
1064 bank->chip.base = gpio;
1065 gpio += bank->width;
1067 bank->chip.ngpio = bank->width;
1069 gpiochip_add(&bank->chip);
1072 * REVISIT these explicit calls to irq_create_mapping()
1073 * to do the GPIO to IRQ domain mapping for each GPIO in
1074 * the bank can be removed once all OMAP platforms have
1075 * been migrated to Device Tree boot only.
1076 * Since in DT boot irq_create_mapping() is called from
1077 * irq_create_of_mapping() only for the GPIO lines that
1078 * are used as interrupts.
1080 if (!bank->chip.of_node)
1081 for (j = 0; j < bank->width; j++)
1082 irq_create_mapping(bank->domain, j);
1083 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1084 irq_set_handler_data(bank->irq, bank);
1087 static const struct of_device_id omap_gpio_match[];
1089 static int omap_gpio_irq_map(struct irq_domain *d, unsigned int virq,
1090 irq_hw_number_t hwirq)
1092 struct gpio_bank *bank = d->host_data;
1097 irq_set_lockdep_class(virq, &gpio_lock_class);
1098 irq_set_chip_data(virq, bank);
1099 if (bank->is_mpuio) {
1100 omap_mpuio_alloc_gc(bank, virq, bank->width);
1102 irq_set_chip_and_handler(virq, &gpio_irq_chip,
1104 set_irq_flags(virq, IRQF_VALID);
1110 static struct irq_domain_ops omap_gpio_irq_ops = {
1111 .xlate = irq_domain_xlate_onetwocell,
1112 .map = omap_gpio_irq_map,
1115 static int omap_gpio_probe(struct platform_device *pdev)
1117 struct device *dev = &pdev->dev;
1118 struct device_node *node = dev->of_node;
1119 const struct of_device_id *match;
1120 const struct omap_gpio_platform_data *pdata;
1121 struct resource *res;
1122 struct gpio_bank *bank;
1123 #ifdef CONFIG_ARCH_OMAP1
1127 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1129 pdata = match ? match->data : dev->platform_data;
1133 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1135 dev_err(dev, "Memory alloc failed\n");
1139 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1140 if (unlikely(!res)) {
1141 dev_err(dev, "Invalid IRQ resource\n");
1145 bank->irq = res->start;
1147 bank->dbck_flag = pdata->dbck_flag;
1148 bank->stride = pdata->bank_stride;
1149 bank->width = pdata->bank_width;
1150 bank->is_mpuio = pdata->is_mpuio;
1151 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1152 bank->regs = pdata->regs;
1153 #ifdef CONFIG_OF_GPIO
1154 bank->chip.of_node = of_node_get(node);
1157 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1158 bank->loses_context = true;
1160 bank->loses_context = pdata->loses_context;
1162 if (bank->loses_context)
1163 bank->get_context_loss_count =
1164 pdata->get_context_loss_count;
1167 #ifdef CONFIG_ARCH_OMAP1
1169 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1170 * irq_alloc_descs() and irq_domain_add_legacy() and just use a
1171 * linear IRQ domain mapping for all OMAP platforms.
1173 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1175 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1179 bank->domain = irq_domain_add_legacy(node, bank->width, irq_base,
1180 0, &omap_gpio_irq_ops, bank);
1182 bank->domain = irq_domain_add_linear(node, bank->width,
1183 &omap_gpio_irq_ops, bank);
1185 if (!bank->domain) {
1186 dev_err(dev, "Couldn't register an IRQ domain\n");
1190 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1191 bank->set_dataout = _set_gpio_dataout_reg;
1193 bank->set_dataout = _set_gpio_dataout_mask;
1195 spin_lock_init(&bank->lock);
1197 /* Static mapping, never released */
1198 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1199 if (unlikely(!res)) {
1200 dev_err(dev, "Invalid mem resource\n");
1201 irq_domain_remove(bank->domain);
1205 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1207 dev_err(dev, "Region already claimed\n");
1208 irq_domain_remove(bank->domain);
1212 bank->base = devm_ioremap(dev, res->start, resource_size(res));
1214 dev_err(dev, "Could not ioremap\n");
1215 irq_domain_remove(bank->domain);
1219 platform_set_drvdata(pdev, bank);
1221 pm_runtime_enable(bank->dev);
1222 pm_runtime_irq_safe(bank->dev);
1223 pm_runtime_get_sync(bank->dev);
1228 omap_gpio_mod_init(bank);
1229 omap_gpio_chip_init(bank);
1230 omap_gpio_show_rev(bank);
1232 pm_runtime_put(bank->dev);
1234 list_add_tail(&bank->node, &omap_gpio_list);
1239 #ifdef CONFIG_ARCH_OMAP2PLUS
1241 #if defined(CONFIG_PM_RUNTIME)
1242 static void omap_gpio_restore_context(struct gpio_bank *bank);
1244 static int omap_gpio_runtime_suspend(struct device *dev)
1246 struct platform_device *pdev = to_platform_device(dev);
1247 struct gpio_bank *bank = platform_get_drvdata(pdev);
1249 unsigned long flags;
1250 u32 wake_low, wake_hi;
1252 spin_lock_irqsave(&bank->lock, flags);
1255 * Only edges can generate a wakeup event to the PRCM.
1257 * Therefore, ensure any wake-up capable GPIOs have
1258 * edge-detection enabled before going idle to ensure a wakeup
1259 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1262 * The normal values will be restored upon ->runtime_resume()
1263 * by writing back the values saved in bank->context.
1265 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1267 __raw_writel(wake_low | bank->context.fallingdetect,
1268 bank->base + bank->regs->fallingdetect);
1269 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1271 __raw_writel(wake_hi | bank->context.risingdetect,
1272 bank->base + bank->regs->risingdetect);
1274 if (!bank->enabled_non_wakeup_gpios)
1275 goto update_gpio_context_count;
1277 if (bank->power_mode != OFF_MODE) {
1278 bank->power_mode = 0;
1279 goto update_gpio_context_count;
1282 * If going to OFF, remove triggering for all
1283 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1284 * generated. See OMAP2420 Errata item 1.101.
1286 bank->saved_datain = __raw_readl(bank->base +
1287 bank->regs->datain);
1288 l1 = bank->context.fallingdetect;
1289 l2 = bank->context.risingdetect;
1291 l1 &= ~bank->enabled_non_wakeup_gpios;
1292 l2 &= ~bank->enabled_non_wakeup_gpios;
1294 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1295 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1297 bank->workaround_enabled = true;
1299 update_gpio_context_count:
1300 if (bank->get_context_loss_count)
1301 bank->context_loss_count =
1302 bank->get_context_loss_count(bank->dev);
1304 _gpio_dbck_disable(bank);
1305 spin_unlock_irqrestore(&bank->lock, flags);
1310 static void omap_gpio_init_context(struct gpio_bank *p);
1312 static int omap_gpio_runtime_resume(struct device *dev)
1314 struct platform_device *pdev = to_platform_device(dev);
1315 struct gpio_bank *bank = platform_get_drvdata(pdev);
1316 u32 l = 0, gen, gen0, gen1;
1317 unsigned long flags;
1320 spin_lock_irqsave(&bank->lock, flags);
1323 * On the first resume during the probe, the context has not
1324 * been initialised and so initialise it now. Also initialise
1325 * the context loss count.
1327 if (bank->loses_context && !bank->context_valid) {
1328 omap_gpio_init_context(bank);
1330 if (bank->get_context_loss_count)
1331 bank->context_loss_count =
1332 bank->get_context_loss_count(bank->dev);
1335 _gpio_dbck_enable(bank);
1338 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1339 * GPIOs were set to edge trigger also in order to be able to
1340 * generate a PRCM wakeup. Here we restore the
1341 * pre-runtime_suspend() values for edge triggering.
1343 __raw_writel(bank->context.fallingdetect,
1344 bank->base + bank->regs->fallingdetect);
1345 __raw_writel(bank->context.risingdetect,
1346 bank->base + bank->regs->risingdetect);
1348 if (bank->loses_context) {
1349 if (!bank->get_context_loss_count) {
1350 omap_gpio_restore_context(bank);
1352 c = bank->get_context_loss_count(bank->dev);
1353 if (c != bank->context_loss_count) {
1354 omap_gpio_restore_context(bank);
1356 spin_unlock_irqrestore(&bank->lock, flags);
1362 if (!bank->workaround_enabled) {
1363 spin_unlock_irqrestore(&bank->lock, flags);
1367 l = __raw_readl(bank->base + bank->regs->datain);
1370 * Check if any of the non-wakeup interrupt GPIOs have changed
1371 * state. If so, generate an IRQ by software. This is
1372 * horribly racy, but it's the best we can do to work around
1375 l ^= bank->saved_datain;
1376 l &= bank->enabled_non_wakeup_gpios;
1379 * No need to generate IRQs for the rising edge for gpio IRQs
1380 * configured with falling edge only; and vice versa.
1382 gen0 = l & bank->context.fallingdetect;
1383 gen0 &= bank->saved_datain;
1385 gen1 = l & bank->context.risingdetect;
1386 gen1 &= ~(bank->saved_datain);
1388 /* FIXME: Consider GPIO IRQs with level detections properly! */
1389 gen = l & (~(bank->context.fallingdetect) &
1390 ~(bank->context.risingdetect));
1391 /* Consider all GPIO IRQs needed to be updated */
1397 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1398 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1400 if (!bank->regs->irqstatus_raw0) {
1401 __raw_writel(old0 | gen, bank->base +
1402 bank->regs->leveldetect0);
1403 __raw_writel(old1 | gen, bank->base +
1404 bank->regs->leveldetect1);
1407 if (bank->regs->irqstatus_raw0) {
1408 __raw_writel(old0 | l, bank->base +
1409 bank->regs->leveldetect0);
1410 __raw_writel(old1 | l, bank->base +
1411 bank->regs->leveldetect1);
1413 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1414 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1417 bank->workaround_enabled = false;
1418 spin_unlock_irqrestore(&bank->lock, flags);
1422 #endif /* CONFIG_PM_RUNTIME */
1424 void omap2_gpio_prepare_for_idle(int pwr_mode)
1426 struct gpio_bank *bank;
1428 list_for_each_entry(bank, &omap_gpio_list, node) {
1429 if (!bank->mod_usage || !bank->loses_context)
1432 bank->power_mode = pwr_mode;
1434 pm_runtime_put_sync_suspend(bank->dev);
1438 void omap2_gpio_resume_after_idle(void)
1440 struct gpio_bank *bank;
1442 list_for_each_entry(bank, &omap_gpio_list, node) {
1443 if (!bank->mod_usage || !bank->loses_context)
1446 pm_runtime_get_sync(bank->dev);
1450 #if defined(CONFIG_PM_RUNTIME)
1451 static void omap_gpio_init_context(struct gpio_bank *p)
1453 struct omap_gpio_reg_offs *regs = p->regs;
1454 void __iomem *base = p->base;
1456 p->context.ctrl = __raw_readl(base + regs->ctrl);
1457 p->context.oe = __raw_readl(base + regs->direction);
1458 p->context.wake_en = __raw_readl(base + regs->wkup_en);
1459 p->context.leveldetect0 = __raw_readl(base + regs->leveldetect0);
1460 p->context.leveldetect1 = __raw_readl(base + regs->leveldetect1);
1461 p->context.risingdetect = __raw_readl(base + regs->risingdetect);
1462 p->context.fallingdetect = __raw_readl(base + regs->fallingdetect);
1463 p->context.irqenable1 = __raw_readl(base + regs->irqenable);
1464 p->context.irqenable2 = __raw_readl(base + regs->irqenable2);
1466 if (regs->set_dataout && p->regs->clr_dataout)
1467 p->context.dataout = __raw_readl(base + regs->set_dataout);
1469 p->context.dataout = __raw_readl(base + regs->dataout);
1471 p->context_valid = true;
1474 static void omap_gpio_restore_context(struct gpio_bank *bank)
1476 __raw_writel(bank->context.wake_en,
1477 bank->base + bank->regs->wkup_en);
1478 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1479 __raw_writel(bank->context.leveldetect0,
1480 bank->base + bank->regs->leveldetect0);
1481 __raw_writel(bank->context.leveldetect1,
1482 bank->base + bank->regs->leveldetect1);
1483 __raw_writel(bank->context.risingdetect,
1484 bank->base + bank->regs->risingdetect);
1485 __raw_writel(bank->context.fallingdetect,
1486 bank->base + bank->regs->fallingdetect);
1487 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1488 __raw_writel(bank->context.dataout,
1489 bank->base + bank->regs->set_dataout);
1491 __raw_writel(bank->context.dataout,
1492 bank->base + bank->regs->dataout);
1493 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1495 if (bank->dbck_enable_mask) {
1496 __raw_writel(bank->context.debounce, bank->base +
1497 bank->regs->debounce);
1498 __raw_writel(bank->context.debounce_en,
1499 bank->base + bank->regs->debounce_en);
1502 __raw_writel(bank->context.irqenable1,
1503 bank->base + bank->regs->irqenable);
1504 __raw_writel(bank->context.irqenable2,
1505 bank->base + bank->regs->irqenable2);
1507 #endif /* CONFIG_PM_RUNTIME */
1509 #define omap_gpio_runtime_suspend NULL
1510 #define omap_gpio_runtime_resume NULL
1511 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1514 static const struct dev_pm_ops gpio_pm_ops = {
1515 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1519 #if defined(CONFIG_OF)
1520 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1521 .revision = OMAP24XX_GPIO_REVISION,
1522 .direction = OMAP24XX_GPIO_OE,
1523 .datain = OMAP24XX_GPIO_DATAIN,
1524 .dataout = OMAP24XX_GPIO_DATAOUT,
1525 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1526 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1527 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1528 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1529 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1530 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1531 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1532 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1533 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1534 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1535 .ctrl = OMAP24XX_GPIO_CTRL,
1536 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1537 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1538 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1539 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1540 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1543 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1544 .revision = OMAP4_GPIO_REVISION,
1545 .direction = OMAP4_GPIO_OE,
1546 .datain = OMAP4_GPIO_DATAIN,
1547 .dataout = OMAP4_GPIO_DATAOUT,
1548 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1549 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1550 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1551 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1552 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1553 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1554 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1555 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1556 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1557 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1558 .ctrl = OMAP4_GPIO_CTRL,
1559 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1560 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1561 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1562 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1563 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1566 static const struct omap_gpio_platform_data omap2_pdata = {
1567 .regs = &omap2_gpio_regs,
1572 static const struct omap_gpio_platform_data omap3_pdata = {
1573 .regs = &omap2_gpio_regs,
1578 static const struct omap_gpio_platform_data omap4_pdata = {
1579 .regs = &omap4_gpio_regs,
1584 static const struct of_device_id omap_gpio_match[] = {
1586 .compatible = "ti,omap4-gpio",
1587 .data = &omap4_pdata,
1590 .compatible = "ti,omap3-gpio",
1591 .data = &omap3_pdata,
1594 .compatible = "ti,omap2-gpio",
1595 .data = &omap2_pdata,
1599 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1602 static struct platform_driver omap_gpio_driver = {
1603 .probe = omap_gpio_probe,
1605 .name = "omap_gpio",
1607 .of_match_table = of_match_ptr(omap_gpio_match),
1612 * gpio driver register needs to be done before
1613 * machine_init functions access gpio APIs.
1614 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1616 static int __init omap_gpio_drv_reg(void)
1618 return platform_driver_register(&omap_gpio_driver);
1620 postcore_initcall(omap_gpio_drv_reg);