2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/pci.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
24 #define PCH_EDGE_FALLING 0
25 #define PCH_EDGE_RISING BIT(0)
26 #define PCH_LEVEL_L BIT(1)
27 #define PCH_LEVEL_H (BIT(0) | BIT(1))
28 #define PCH_EDGE_BOTH BIT(2)
29 #define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31 #define PCH_IRQ_BASE 24
52 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
53 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
56 /* Specifies number of GPIO PINS */
57 static int gpio_pins[] = {
58 [INTEL_EG20T_PCH] = 12,
59 [OKISEMI_ML7223m_IOH] = 8,
60 [OKISEMI_ML7223n_IOH] = 8,
64 * struct pch_gpio_reg_data - The register store data.
65 * @ien_reg: To store contents of IEN register.
66 * @imask_reg: To store contents of IMASK register.
67 * @po_reg: To store contents of PO register.
68 * @pm_reg: To store contents of PM register.
69 * @im0_reg: To store contents of IM0 register.
70 * @im1_reg: To store contents of IM1 register.
71 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
74 struct pch_gpio_reg_data {
85 * struct pch_gpio - GPIO private data structure.
86 * @base: PCI base address of Memory mapped I/O register.
87 * @reg: Memory mapped PCH GPIO register list.
88 * @dev: Pointer to device structure.
89 * @gpio: Data for GPIO infrastructure.
90 * @pch_gpio_reg: Memory mapped Register data is saved here
92 * @lock: Used for register access protection
93 * @irq_base: Save base of IRQ number for interrupt
95 * @spinlock: Used for register access protection
99 struct pch_regs __iomem *reg;
101 struct gpio_chip gpio;
102 struct pch_gpio_reg_data pch_gpio_reg;
108 static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
111 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
114 spin_lock_irqsave(&chip->spinlock, flags);
115 reg_val = ioread32(&chip->reg->po);
117 reg_val |= (1 << nr);
119 reg_val &= ~(1 << nr);
121 iowrite32(reg_val, &chip->reg->po);
122 spin_unlock_irqrestore(&chip->spinlock, flags);
125 static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
127 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
129 return ioread32(&chip->reg->pi) & (1 << nr);
132 static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
135 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
140 spin_lock_irqsave(&chip->spinlock, flags);
142 reg_val = ioread32(&chip->reg->po);
144 reg_val |= (1 << nr);
146 reg_val &= ~(1 << nr);
147 iowrite32(reg_val, &chip->reg->po);
149 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
151 iowrite32(pm, &chip->reg->pm);
153 spin_unlock_irqrestore(&chip->spinlock, flags);
158 static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
160 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
164 spin_lock_irqsave(&chip->spinlock, flags);
165 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
167 iowrite32(pm, &chip->reg->pm);
168 spin_unlock_irqrestore(&chip->spinlock, flags);
174 * Save register configuration and disable interrupts.
176 static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
178 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
179 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
180 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
181 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
182 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
183 if (chip->ioh == INTEL_EG20T_PCH)
184 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
185 if (chip->ioh == OKISEMI_ML7223n_IOH)
186 chip->pch_gpio_reg.gpio_use_sel_reg =\
187 ioread32(&chip->reg->gpio_use_sel);
191 * This function restores the register configuration of the GPIO device.
193 static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
195 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
196 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
197 /* to store contents of PO register */
198 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
199 /* to store contents of PM register */
200 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
201 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
202 if (chip->ioh == INTEL_EG20T_PCH)
203 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
204 if (chip->ioh == OKISEMI_ML7223n_IOH)
205 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
206 &chip->reg->gpio_use_sel);
209 static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
211 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
212 return chip->irq_base + offset;
215 static void pch_gpio_setup(struct pch_gpio *chip)
217 struct gpio_chip *gpio = &chip->gpio;
219 gpio->label = dev_name(chip->dev);
220 gpio->dev = chip->dev;
221 gpio->owner = THIS_MODULE;
222 gpio->direction_input = pch_gpio_direction_input;
223 gpio->get = pch_gpio_get;
224 gpio->direction_output = pch_gpio_direction_output;
225 gpio->set = pch_gpio_set;
226 gpio->dbg_show = NULL;
228 gpio->ngpio = gpio_pins[chip->ioh];
229 gpio->can_sleep = false;
230 gpio->to_irq = pch_gpio_to_irq;
233 static int pch_irq_type(struct irq_data *d, unsigned int type)
235 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
236 struct pch_gpio *chip = gc->private;
240 int ch, irq = d->irq;
242 ch = irq - chip->irq_base;
243 if (irq <= chip->irq_base + 7) {
244 im_reg = &chip->reg->im0;
247 im_reg = &chip->reg->im1;
250 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
251 __func__, irq, type, ch, im_pos);
253 spin_lock_irqsave(&chip->spinlock, flags);
256 case IRQ_TYPE_EDGE_RISING:
257 val = PCH_EDGE_RISING;
259 case IRQ_TYPE_EDGE_FALLING:
260 val = PCH_EDGE_FALLING;
262 case IRQ_TYPE_EDGE_BOTH:
265 case IRQ_TYPE_LEVEL_HIGH:
268 case IRQ_TYPE_LEVEL_LOW:
275 /* Set interrupt mode */
276 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
277 iowrite32(im | (val << (im_pos * 4)), im_reg);
279 /* And the handler */
280 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
281 __irq_set_handler_locked(d->irq, handle_level_irq);
282 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
283 __irq_set_handler_locked(d->irq, handle_edge_irq);
286 spin_unlock_irqrestore(&chip->spinlock, flags);
290 static void pch_irq_unmask(struct irq_data *d)
292 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
293 struct pch_gpio *chip = gc->private;
295 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
298 static void pch_irq_mask(struct irq_data *d)
300 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
301 struct pch_gpio *chip = gc->private;
303 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
306 static void pch_irq_ack(struct irq_data *d)
308 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
309 struct pch_gpio *chip = gc->private;
311 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
314 static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
316 struct pch_gpio *chip = dev_id;
317 u32 reg_val = ioread32(&chip->reg->istatus);
318 int i, ret = IRQ_NONE;
320 for (i = 0; i < gpio_pins[chip->ioh]; i++) {
321 if (reg_val & BIT(i)) {
322 dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
323 __func__, i, irq, reg_val);
324 generic_handle_irq(chip->irq_base + i);
331 static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
332 unsigned int irq_start, unsigned int num)
334 struct irq_chip_generic *gc;
335 struct irq_chip_type *ct;
337 gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
342 ct->chip.irq_ack = pch_irq_ack;
343 ct->chip.irq_mask = pch_irq_mask;
344 ct->chip.irq_unmask = pch_irq_unmask;
345 ct->chip.irq_set_type = pch_irq_type;
347 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
348 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
351 static int pch_gpio_probe(struct pci_dev *pdev,
352 const struct pci_device_id *id)
355 struct pch_gpio *chip;
359 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
363 chip->dev = &pdev->dev;
364 ret = pci_enable_device(pdev);
366 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
370 ret = pci_request_regions(pdev, KBUILD_MODNAME);
372 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
373 goto err_request_regions;
376 chip->base = pci_iomap(pdev, 1, 0);
378 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
383 if (pdev->device == 0x8803)
384 chip->ioh = INTEL_EG20T_PCH;
385 else if (pdev->device == 0x8014)
386 chip->ioh = OKISEMI_ML7223m_IOH;
387 else if (pdev->device == 0x8043)
388 chip->ioh = OKISEMI_ML7223n_IOH;
390 chip->reg = chip->base;
391 pci_set_drvdata(pdev, chip);
392 spin_lock_init(&chip->spinlock);
393 pch_gpio_setup(chip);
394 ret = gpiochip_add(&chip->gpio);
396 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
397 goto err_gpiochip_add;
400 irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
402 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
406 chip->irq_base = irq_base;
408 /* Mask all interrupts, but enable them */
409 msk = (1 << gpio_pins[chip->ioh]) - 1;
410 iowrite32(msk, &chip->reg->imask);
411 iowrite32(msk, &chip->reg->ien);
413 ret = request_irq(pdev->irq, pch_gpio_handler,
414 IRQF_SHARED, KBUILD_MODNAME, chip);
417 "%s request_irq failed\n", __func__);
418 goto err_request_irq;
421 pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
427 irq_free_descs(irq_base, gpio_pins[chip->ioh]);
429 if (gpiochip_remove(&chip->gpio))
430 dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);
433 pci_iounmap(pdev, chip->base);
436 pci_release_regions(pdev);
439 pci_disable_device(pdev);
443 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
447 static void pch_gpio_remove(struct pci_dev *pdev)
450 struct pch_gpio *chip = pci_get_drvdata(pdev);
452 if (chip->irq_base != -1) {
453 free_irq(pdev->irq, chip);
455 irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
458 err = gpiochip_remove(&chip->gpio);
460 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
462 pci_iounmap(pdev, chip->base);
463 pci_release_regions(pdev);
464 pci_disable_device(pdev);
469 static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
472 struct pch_gpio *chip = pci_get_drvdata(pdev);
475 spin_lock_irqsave(&chip->spinlock, flags);
476 pch_gpio_save_reg_conf(chip);
477 spin_unlock_irqrestore(&chip->spinlock, flags);
479 ret = pci_save_state(pdev);
481 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
484 pci_disable_device(pdev);
485 pci_set_power_state(pdev, PCI_D0);
486 ret = pci_enable_wake(pdev, PCI_D0, 1);
488 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
493 static int pch_gpio_resume(struct pci_dev *pdev)
496 struct pch_gpio *chip = pci_get_drvdata(pdev);
499 ret = pci_enable_wake(pdev, PCI_D0, 0);
501 pci_set_power_state(pdev, PCI_D0);
502 ret = pci_enable_device(pdev);
504 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
507 pci_restore_state(pdev);
509 spin_lock_irqsave(&chip->spinlock, flags);
510 iowrite32(0x01, &chip->reg->reset);
511 iowrite32(0x00, &chip->reg->reset);
512 pch_gpio_restore_reg_conf(chip);
513 spin_unlock_irqrestore(&chip->spinlock, flags);
518 #define pch_gpio_suspend NULL
519 #define pch_gpio_resume NULL
522 #define PCI_VENDOR_ID_ROHM 0x10DB
523 static const struct pci_device_id pch_gpio_pcidev_id[] = {
524 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
525 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
526 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
527 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
530 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
532 static struct pci_driver pch_gpio_driver = {
534 .id_table = pch_gpio_pcidev_id,
535 .probe = pch_gpio_probe,
536 .remove = pch_gpio_remove,
537 .suspend = pch_gpio_suspend,
538 .resume = pch_gpio_resume
541 module_pci_driver(pch_gpio_driver);
543 MODULE_DESCRIPTION("PCH GPIO PCI Driver");
544 MODULE_LICENSE("GPL");