2 * Copyright (C) 2008, 2009 Provigent Ltd.
4 * Author: Baruch Siach <baruch@tkos.co.il>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
12 * Data sheet: ARM DDI 0190B, September 2000
14 #include <linux/spinlock.h>
15 #include <linux/errno.h>
16 #include <linux/init.h>
18 #include <linux/ioport.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/bitops.h>
23 #include <linux/gpio.h>
24 #include <linux/device.h>
25 #include <linux/amba/bus.h>
26 #include <linux/amba/pl061.h>
27 #include <linux/slab.h>
28 #include <linux/pinctrl/consumer.h>
40 #define PL061_GPIO_NR 8
43 struct pl061_context_save_regs {
61 struct pl061_context_save_regs csave_regs;
65 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
67 struct pl061 *chip = gpiochip_get_data(gc);
69 return !(readb(chip->base + GPIODIR) & BIT(offset));
72 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
74 struct pl061 *chip = gpiochip_get_data(gc);
76 unsigned char gpiodir;
78 spin_lock_irqsave(&chip->lock, flags);
79 gpiodir = readb(chip->base + GPIODIR);
80 gpiodir &= ~(BIT(offset));
81 writeb(gpiodir, chip->base + GPIODIR);
82 spin_unlock_irqrestore(&chip->lock, flags);
87 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
90 struct pl061 *chip = gpiochip_get_data(gc);
92 unsigned char gpiodir;
94 spin_lock_irqsave(&chip->lock, flags);
95 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
96 gpiodir = readb(chip->base + GPIODIR);
97 gpiodir |= BIT(offset);
98 writeb(gpiodir, chip->base + GPIODIR);
101 * gpio value is set again, because pl061 doesn't allow to set value of
102 * a gpio pin before configuring it in OUT mode.
104 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
105 spin_unlock_irqrestore(&chip->lock, flags);
110 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
112 struct pl061 *chip = gpiochip_get_data(gc);
114 return !!readb(chip->base + (BIT(offset + 2)));
117 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
119 struct pl061 *chip = gpiochip_get_data(gc);
121 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
124 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
126 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
127 struct pl061 *chip = gpiochip_get_data(gc);
128 int offset = irqd_to_hwirq(d);
130 u8 gpiois, gpioibe, gpioiev;
131 u8 bit = BIT(offset);
133 if (offset < 0 || offset >= PL061_GPIO_NR)
136 if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
137 (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
140 "trying to configure line %d for both level and edge "
141 "detection, choose one!\n",
147 spin_lock_irqsave(&chip->lock, flags);
149 gpioiev = readb(chip->base + GPIOIEV);
150 gpiois = readb(chip->base + GPIOIS);
151 gpioibe = readb(chip->base + GPIOIBE);
153 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
154 bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
156 /* Disable edge detection */
158 /* Enable level detection */
160 /* Select polarity */
165 irq_set_handler_locked(d, handle_level_irq);
166 dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
168 polarity ? "HIGH" : "LOW");
169 } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
170 /* Disable level detection */
172 /* Select both edges, setting this makes GPIOEV be ignored */
174 irq_set_handler_locked(d, handle_edge_irq);
175 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
176 } else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
177 (trigger & IRQ_TYPE_EDGE_FALLING)) {
178 bool rising = trigger & IRQ_TYPE_EDGE_RISING;
180 /* Disable level detection */
182 /* Clear detection on both edges */
189 irq_set_handler_locked(d, handle_edge_irq);
190 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
192 rising ? "RISING" : "FALLING");
194 /* No trigger: disable everything */
198 irq_set_handler_locked(d, handle_bad_irq);
199 dev_warn(gc->parent, "no trigger selected for line %d\n",
203 writeb(gpiois, chip->base + GPIOIS);
204 writeb(gpioibe, chip->base + GPIOIBE);
205 writeb(gpioiev, chip->base + GPIOIEV);
207 spin_unlock_irqrestore(&chip->lock, flags);
212 static void pl061_irq_handler(struct irq_desc *desc)
214 unsigned long pending;
216 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
217 struct pl061 *chip = gpiochip_get_data(gc);
218 struct irq_chip *irqchip = irq_desc_get_chip(desc);
220 chained_irq_enter(irqchip, desc);
222 pending = readb(chip->base + GPIOMIS);
224 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
225 generic_handle_irq(irq_find_mapping(gc->irqdomain,
229 chained_irq_exit(irqchip, desc);
232 static void pl061_irq_mask(struct irq_data *d)
234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
235 struct pl061 *chip = gpiochip_get_data(gc);
236 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
239 spin_lock(&chip->lock);
240 gpioie = readb(chip->base + GPIOIE) & ~mask;
241 writeb(gpioie, chip->base + GPIOIE);
242 spin_unlock(&chip->lock);
245 static void pl061_irq_unmask(struct irq_data *d)
247 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
248 struct pl061 *chip = gpiochip_get_data(gc);
249 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
252 spin_lock(&chip->lock);
253 gpioie = readb(chip->base + GPIOIE) | mask;
254 writeb(gpioie, chip->base + GPIOIE);
255 spin_unlock(&chip->lock);
259 * pl061_irq_ack() - ACK an edge IRQ
260 * @d: IRQ data for this IRQ
262 * This gets called from the edge IRQ handler to ACK the edge IRQ
263 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
264 * not needed: these go away when the level signal goes away.
266 static void pl061_irq_ack(struct irq_data *d)
268 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
269 struct pl061 *chip = gpiochip_get_data(gc);
270 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
272 spin_lock(&chip->lock);
273 writeb(mask, chip->base + GPIOIC);
274 spin_unlock(&chip->lock);
277 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
280 struct pl061 *chip = gpiochip_get_data(gc);
282 return irq_set_irq_wake(chip->parent_irq, state);
285 static struct irq_chip pl061_irqchip = {
287 .irq_ack = pl061_irq_ack,
288 .irq_mask = pl061_irq_mask,
289 .irq_unmask = pl061_irq_unmask,
290 .irq_set_type = pl061_irq_type,
291 .irq_set_wake = pl061_irq_set_wake,
294 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
296 struct device *dev = &adev->dev;
297 struct pl061_platform_data *pdata = dev_get_platdata(dev);
299 int ret, irq, i, irq_base;
301 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
306 chip->gc.base = pdata->gpio_base;
307 irq_base = pdata->irq_base;
309 dev_err(&adev->dev, "invalid IRQ base in pdata\n");
317 chip->base = devm_ioremap_resource(dev, &adev->res);
318 if (IS_ERR(chip->base))
319 return PTR_ERR(chip->base);
321 spin_lock_init(&chip->lock);
322 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
323 chip->gc.request = gpiochip_generic_request;
324 chip->gc.free = gpiochip_generic_free;
327 chip->gc.get_direction = pl061_get_direction;
328 chip->gc.direction_input = pl061_direction_input;
329 chip->gc.direction_output = pl061_direction_output;
330 chip->gc.get = pl061_get_value;
331 chip->gc.set = pl061_set_value;
332 chip->gc.ngpio = PL061_GPIO_NR;
333 chip->gc.label = dev_name(dev);
334 chip->gc.parent = dev;
335 chip->gc.owner = THIS_MODULE;
337 ret = gpiochip_add_data(&chip->gc, chip);
344 writeb(0, chip->base + GPIOIE); /* disable irqs */
347 dev_err(&adev->dev, "invalid IRQ\n");
350 chip->parent_irq = irq;
352 ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
353 irq_base, handle_bad_irq,
356 dev_info(&adev->dev, "could not add irqchip\n");
359 gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
360 irq, pl061_irq_handler);
362 for (i = 0; i < PL061_GPIO_NR; i++) {
364 if (pdata->directions & (BIT(i)))
365 pl061_direction_output(&chip->gc, i,
366 pdata->values & (BIT(i)));
368 pl061_direction_input(&chip->gc, i);
372 amba_set_drvdata(adev, chip);
373 dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
380 static int pl061_suspend(struct device *dev)
382 struct pl061 *chip = dev_get_drvdata(dev);
385 chip->csave_regs.gpio_data = 0;
386 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
387 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
388 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
389 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
390 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
392 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
393 if (chip->csave_regs.gpio_dir & (BIT(offset)))
394 chip->csave_regs.gpio_data |=
395 pl061_get_value(&chip->gc, offset) << offset;
401 static int pl061_resume(struct device *dev)
403 struct pl061 *chip = dev_get_drvdata(dev);
406 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
407 if (chip->csave_regs.gpio_dir & (BIT(offset)))
408 pl061_direction_output(&chip->gc, offset,
409 chip->csave_regs.gpio_data &
412 pl061_direction_input(&chip->gc, offset);
415 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
416 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
417 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
418 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
423 static const struct dev_pm_ops pl061_dev_pm_ops = {
424 .suspend = pl061_suspend,
425 .resume = pl061_resume,
426 .freeze = pl061_suspend,
427 .restore = pl061_resume,
431 static struct amba_id pl061_ids[] = {
439 static struct amba_driver pl061_gpio_driver = {
441 .name = "pl061_gpio",
443 .pm = &pl061_dev_pm_ops,
446 .id_table = pl061_ids,
447 .probe = pl061_probe,
450 static int __init pl061_gpio_init(void)
452 return amba_driver_register(&pl061_gpio_driver);
454 device_initcall(pl061_gpio_init);