2 * Copyright (C) 2008, 2009 Provigent Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
10 * Data sheet: ARM DDI 0190B, September 2000
12 #include <linux/spinlock.h>
13 #include <linux/errno.h>
14 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/bitops.h>
20 #include <linux/gpio.h>
21 #include <linux/device.h>
22 #include <linux/amba/bus.h>
23 #include <linux/amba/pl061.h>
24 #include <linux/slab.h>
25 #include <linux/pinctrl/consumer.h>
37 #define PL061_GPIO_NR 8
40 struct pl061_context_save_regs {
57 struct pl061_context_save_regs csave_regs;
61 static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
64 * Map back to global GPIO space and request muxing, the direction
65 * parameter does not matter for this controller.
67 int gpio = chip->base + offset;
69 return pinctrl_request_gpio(gpio);
72 static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset)
74 int gpio = chip->base + offset;
76 pinctrl_free_gpio(gpio);
79 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
81 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
83 unsigned char gpiodir;
85 if (offset >= gc->ngpio)
88 spin_lock_irqsave(&chip->lock, flags);
89 gpiodir = readb(chip->base + GPIODIR);
90 gpiodir &= ~(BIT(offset));
91 writeb(gpiodir, chip->base + GPIODIR);
92 spin_unlock_irqrestore(&chip->lock, flags);
97 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
100 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
102 unsigned char gpiodir;
104 if (offset >= gc->ngpio)
107 spin_lock_irqsave(&chip->lock, flags);
108 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
109 gpiodir = readb(chip->base + GPIODIR);
110 gpiodir |= BIT(offset);
111 writeb(gpiodir, chip->base + GPIODIR);
114 * gpio value is set again, because pl061 doesn't allow to set value of
115 * a gpio pin before configuring it in OUT mode.
117 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
118 spin_unlock_irqrestore(&chip->lock, flags);
123 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
125 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
127 return !!readb(chip->base + (BIT(offset + 2)));
130 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
132 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
134 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
137 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
140 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
141 int offset = irqd_to_hwirq(d);
143 u8 gpiois, gpioibe, gpioiev;
144 u8 bit = BIT(offset);
146 if (offset < 0 || offset >= PL061_GPIO_NR)
149 spin_lock_irqsave(&chip->lock, flags);
151 gpioiev = readb(chip->base + GPIOIEV);
152 gpiois = readb(chip->base + GPIOIS);
153 gpioibe = readb(chip->base + GPIOIBE);
155 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
157 if (trigger & IRQ_TYPE_LEVEL_HIGH)
164 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
165 /* Setting this makes GPIOEV be ignored */
169 if (trigger & IRQ_TYPE_EDGE_RISING)
171 else if (trigger & IRQ_TYPE_EDGE_FALLING)
175 writeb(gpiois, chip->base + GPIOIS);
176 writeb(gpioibe, chip->base + GPIOIBE);
177 writeb(gpioiev, chip->base + GPIOIEV);
179 spin_unlock_irqrestore(&chip->lock, flags);
184 static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
186 unsigned long pending;
188 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
189 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
190 struct irq_chip *irqchip = irq_desc_get_chip(desc);
192 chained_irq_enter(irqchip, desc);
194 pending = readb(chip->base + GPIOMIS);
195 writeb(pending, chip->base + GPIOIC);
197 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
198 generic_handle_irq(irq_find_mapping(gc->irqdomain,
202 chained_irq_exit(irqchip, desc);
205 static void pl061_irq_mask(struct irq_data *d)
207 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
208 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
209 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
212 spin_lock(&chip->lock);
213 gpioie = readb(chip->base + GPIOIE) & ~mask;
214 writeb(gpioie, chip->base + GPIOIE);
215 spin_unlock(&chip->lock);
218 static void pl061_irq_unmask(struct irq_data *d)
220 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
221 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
222 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
225 spin_lock(&chip->lock);
226 gpioie = readb(chip->base + GPIOIE) | mask;
227 writeb(gpioie, chip->base + GPIOIE);
228 spin_unlock(&chip->lock);
231 static struct irq_chip pl061_irqchip = {
233 .irq_mask = pl061_irq_mask,
234 .irq_unmask = pl061_irq_unmask,
235 .irq_set_type = pl061_irq_type,
238 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
240 struct device *dev = &adev->dev;
241 struct pl061_platform_data *pdata = dev_get_platdata(dev);
242 struct pl061_gpio *chip;
243 int ret, irq, i, irq_base;
245 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
250 chip->gc.base = pdata->gpio_base;
251 irq_base = pdata->irq_base;
253 dev_err(&adev->dev, "invalid IRQ base in pdata\n");
261 chip->base = devm_ioremap_resource(dev, &adev->res);
262 if (IS_ERR(chip->base))
263 return PTR_ERR(chip->base);
265 spin_lock_init(&chip->lock);
267 chip->gc.request = pl061_gpio_request;
268 chip->gc.free = pl061_gpio_free;
269 chip->gc.direction_input = pl061_direction_input;
270 chip->gc.direction_output = pl061_direction_output;
271 chip->gc.get = pl061_get_value;
272 chip->gc.set = pl061_set_value;
273 chip->gc.ngpio = PL061_GPIO_NR;
274 chip->gc.label = dev_name(dev);
276 chip->gc.owner = THIS_MODULE;
278 ret = gpiochip_add(&chip->gc);
285 writeb(0, chip->base + GPIOIE); /* disable irqs */
288 dev_err(&adev->dev, "invalid IRQ\n");
292 ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
293 irq_base, handle_simple_irq,
296 dev_info(&adev->dev, "could not add irqchip\n");
299 gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
300 irq, pl061_irq_handler);
302 for (i = 0; i < PL061_GPIO_NR; i++) {
304 if (pdata->directions & (BIT(i)))
305 pl061_direction_output(&chip->gc, i,
306 pdata->values & (BIT(i)));
308 pl061_direction_input(&chip->gc, i);
312 amba_set_drvdata(adev, chip);
313 dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
320 static int pl061_suspend(struct device *dev)
322 struct pl061_gpio *chip = dev_get_drvdata(dev);
325 chip->csave_regs.gpio_data = 0;
326 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
327 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
328 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
329 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
330 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
332 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
333 if (chip->csave_regs.gpio_dir & (BIT(offset)))
334 chip->csave_regs.gpio_data |=
335 pl061_get_value(&chip->gc, offset) << offset;
341 static int pl061_resume(struct device *dev)
343 struct pl061_gpio *chip = dev_get_drvdata(dev);
346 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
347 if (chip->csave_regs.gpio_dir & (BIT(offset)))
348 pl061_direction_output(&chip->gc, offset,
349 chip->csave_regs.gpio_data &
352 pl061_direction_input(&chip->gc, offset);
355 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
356 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
357 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
358 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
363 static const struct dev_pm_ops pl061_dev_pm_ops = {
364 .suspend = pl061_suspend,
365 .resume = pl061_resume,
366 .freeze = pl061_suspend,
367 .restore = pl061_resume,
371 static struct amba_id pl061_ids[] = {
379 MODULE_DEVICE_TABLE(amba, pl061_ids);
381 static struct amba_driver pl061_gpio_driver = {
383 .name = "pl061_gpio",
385 .pm = &pl061_dev_pm_ops,
388 .id_table = pl061_ids,
389 .probe = pl061_probe,
392 static int __init pl061_gpio_init(void)
394 return amba_driver_register(&pl061_gpio_driver);
396 module_init(pl061_gpio_init);
398 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
399 MODULE_DESCRIPTION("PL061 GPIO driver");
400 MODULE_LICENSE("GPL");