2 * Renesas R-Car GPIO Support
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/gpio.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <linux/irq.h>
25 #include <linux/module.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/spinlock.h>
31 #include <linux/slab.h>
33 struct gpio_rcar_priv {
36 struct platform_device *pdev;
37 struct gpio_chip gpio_chip;
38 struct irq_chip irq_chip;
40 unsigned int irq_parent;
41 bool has_both_edge_trigger;
45 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
46 #define INOUTSEL 0x04 /* General Input/Output Switching Register */
47 #define OUTDT 0x08 /* General Output Register */
48 #define INDT 0x0c /* General Input Register */
49 #define INTDT 0x10 /* Interrupt Display Register */
50 #define INTCLR 0x14 /* Interrupt Clear Register */
51 #define INTMSK 0x18 /* Interrupt Mask Register */
52 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */
53 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
54 #define EDGLEVEL 0x24 /* Edge/level Select Register */
55 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
56 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
58 #define RCAR_MAX_GPIO_PER_BANK 32
60 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
62 return ioread32(p->base + offs);
65 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
68 iowrite32(value, p->base + offs);
71 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
74 u32 tmp = gpio_rcar_read(p, offs);
81 gpio_rcar_write(p, offs, tmp);
84 static void gpio_rcar_irq_disable(struct irq_data *d)
86 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
87 struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
90 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
93 static void gpio_rcar_irq_enable(struct irq_data *d)
95 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
96 struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
99 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
102 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
104 bool active_high_rising_edge,
110 /* follow steps in the GPIO documentation for
111 * "Setting Edge-Sensitive Interrupt Input Mode" and
112 * "Setting Level-Sensitive Interrupt Input Mode"
115 spin_lock_irqsave(&p->lock, flags);
117 /* Configure postive or negative logic in POSNEG */
118 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
120 /* Configure edge or level trigger in EDGLEVEL */
121 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
123 /* Select one edge or both edges in BOTHEDGE */
124 if (p->has_both_edge_trigger)
125 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
127 /* Select "Interrupt Input Mode" in IOINTSEL */
128 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
130 /* Write INTCLR in case of edge trigger */
132 gpio_rcar_write(p, INTCLR, BIT(hwirq));
134 spin_unlock_irqrestore(&p->lock, flags);
137 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
140 struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
142 unsigned int hwirq = irqd_to_hwirq(d);
144 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
146 switch (type & IRQ_TYPE_SENSE_MASK) {
147 case IRQ_TYPE_LEVEL_HIGH:
148 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
151 case IRQ_TYPE_LEVEL_LOW:
152 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
155 case IRQ_TYPE_EDGE_RISING:
156 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
159 case IRQ_TYPE_EDGE_FALLING:
160 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
163 case IRQ_TYPE_EDGE_BOTH:
164 if (!p->has_both_edge_trigger)
166 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
175 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
177 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
178 struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
183 error = irq_set_irq_wake(p->irq_parent, on);
185 dev_dbg(&p->pdev->dev,
186 "irq %u doesn't support irq_set_wake\n",
203 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
205 struct gpio_rcar_priv *p = dev_id;
207 unsigned int offset, irqs_handled = 0;
209 while ((pending = gpio_rcar_read(p, INTDT) &
210 gpio_rcar_read(p, INTMSK))) {
211 offset = __ffs(pending);
212 gpio_rcar_write(p, INTCLR, BIT(offset));
213 generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
218 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
221 static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
223 return container_of(chip, struct gpio_rcar_priv, gpio_chip);
226 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
230 struct gpio_rcar_priv *p = gpio_to_priv(chip);
233 /* follow steps in the GPIO documentation for
234 * "Setting General Output Mode" and
235 * "Setting General Input Mode"
238 spin_lock_irqsave(&p->lock, flags);
240 /* Configure postive logic in POSNEG */
241 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
243 /* Select "General Input/Output Mode" in IOINTSEL */
244 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
246 /* Select Input Mode or Output Mode in INOUTSEL */
247 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
249 spin_unlock_irqrestore(&p->lock, flags);
252 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
254 struct gpio_rcar_priv *p = gpio_to_priv(chip);
257 error = pm_runtime_get_sync(&p->pdev->dev);
261 error = pinctrl_request_gpio(chip->base + offset);
263 pm_runtime_put(&p->pdev->dev);
268 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
270 struct gpio_rcar_priv *p = gpio_to_priv(chip);
272 pinctrl_free_gpio(chip->base + offset);
274 /* Set the GPIO as an input to ensure that the next GPIO request won't
275 * drive the GPIO pin as an output.
277 gpio_rcar_config_general_input_output_mode(chip, offset, false);
279 pm_runtime_put(&p->pdev->dev);
282 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
284 gpio_rcar_config_general_input_output_mode(chip, offset, false);
288 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
290 u32 bit = BIT(offset);
292 /* testing on r8a7790 shows that INDT does not show correct pin state
293 * when configured as output, so use OUTDT in case of output pins */
294 if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
295 return !!(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
297 return !!(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
300 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
302 struct gpio_rcar_priv *p = gpio_to_priv(chip);
305 spin_lock_irqsave(&p->lock, flags);
306 gpio_rcar_modify_bit(p, OUTDT, offset, value);
307 spin_unlock_irqrestore(&p->lock, flags);
310 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
313 /* write GPIO value to output before selecting output mode of pin */
314 gpio_rcar_set(chip, offset, value);
315 gpio_rcar_config_general_input_output_mode(chip, offset, true);
319 struct gpio_rcar_info {
320 bool has_both_edge_trigger;
324 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
325 .has_both_edge_trigger = false,
329 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
330 .has_both_edge_trigger = true,
334 static const struct of_device_id gpio_rcar_of_table[] = {
336 .compatible = "renesas,gpio-r8a7790",
337 .data = &gpio_rcar_info_gen2,
339 .compatible = "renesas,gpio-r8a7791",
340 .data = &gpio_rcar_info_gen2,
342 .compatible = "renesas,gpio-r8a7793",
343 .data = &gpio_rcar_info_gen2,
345 .compatible = "renesas,gpio-r8a7794",
346 .data = &gpio_rcar_info_gen2,
348 .compatible = "renesas,gpio-r8a7795",
349 /* Gen3 GPIO is identical to Gen2. */
350 .data = &gpio_rcar_info_gen2,
352 .compatible = "renesas,gpio-rcar",
353 .data = &gpio_rcar_info_gen1,
359 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
361 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
363 struct device_node *np = p->pdev->dev.of_node;
364 const struct of_device_id *match;
365 const struct gpio_rcar_info *info;
366 struct of_phandle_args args;
369 match = of_match_node(gpio_rcar_of_table, np);
375 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
376 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
377 p->has_both_edge_trigger = info->has_both_edge_trigger;
378 p->needs_clk = info->needs_clk;
380 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
381 dev_warn(&p->pdev->dev,
382 "Invalid number of gpio lines %u, using %u\n", *npins,
383 RCAR_MAX_GPIO_PER_BANK);
384 *npins = RCAR_MAX_GPIO_PER_BANK;
390 static int gpio_rcar_probe(struct platform_device *pdev)
392 struct gpio_rcar_priv *p;
393 struct resource *io, *irq;
394 struct gpio_chip *gpio_chip;
395 struct irq_chip *irq_chip;
396 struct device *dev = &pdev->dev;
397 const char *name = dev_name(dev);
401 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
406 spin_lock_init(&p->lock);
408 /* Get device configuration from DT node */
409 ret = gpio_rcar_parse_dt(p, &npins);
413 platform_set_drvdata(pdev, p);
415 p->clk = devm_clk_get(dev, NULL);
416 if (IS_ERR(p->clk)) {
418 dev_err(dev, "unable to get clock\n");
419 ret = PTR_ERR(p->clk);
425 pm_runtime_enable(dev);
427 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
428 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
431 dev_err(dev, "missing IRQ or IOMEM\n");
436 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
438 dev_err(dev, "failed to remap I/O memory\n");
443 gpio_chip = &p->gpio_chip;
444 gpio_chip->request = gpio_rcar_request;
445 gpio_chip->free = gpio_rcar_free;
446 gpio_chip->direction_input = gpio_rcar_direction_input;
447 gpio_chip->get = gpio_rcar_get;
448 gpio_chip->direction_output = gpio_rcar_direction_output;
449 gpio_chip->set = gpio_rcar_set;
450 gpio_chip->label = name;
451 gpio_chip->parent = dev;
452 gpio_chip->owner = THIS_MODULE;
453 gpio_chip->base = -1;
454 gpio_chip->ngpio = npins;
456 irq_chip = &p->irq_chip;
457 irq_chip->name = name;
458 irq_chip->irq_mask = gpio_rcar_irq_disable;
459 irq_chip->irq_unmask = gpio_rcar_irq_enable;
460 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
461 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
462 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
464 ret = gpiochip_add(gpio_chip);
466 dev_err(dev, "failed to add GPIO controller\n");
470 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
473 dev_err(dev, "cannot add irqchip\n");
477 p->irq_parent = irq->start;
478 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
479 IRQF_SHARED, name, p)) {
480 dev_err(dev, "failed to request IRQ\n");
485 dev_info(dev, "driving %d GPIOs\n", npins);
490 gpiochip_remove(gpio_chip);
492 pm_runtime_disable(dev);
496 static int gpio_rcar_remove(struct platform_device *pdev)
498 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
500 gpiochip_remove(&p->gpio_chip);
502 pm_runtime_disable(&pdev->dev);
506 static struct platform_driver gpio_rcar_device_driver = {
507 .probe = gpio_rcar_probe,
508 .remove = gpio_rcar_remove,
511 .of_match_table = of_match_ptr(gpio_rcar_of_table),
515 module_platform_driver(gpio_rcar_device_driver);
517 MODULE_AUTHOR("Magnus Damm");
518 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
519 MODULE_LICENSE("GPL v2");