2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
34 #include <mach/regs-gpio.h>
36 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
37 #include <mach/gpio-samsung.h>
41 #include <plat/gpio-core.h>
42 #include <plat/gpio-cfg.h>
43 #include <plat/gpio-cfg-helpers.h>
46 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
47 unsigned int off, samsung_gpio_pull_t pull)
49 void __iomem *reg = chip->base + 0x08;
53 pup = __raw_readl(reg);
56 __raw_writel(pup, reg);
61 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
64 void __iomem *reg = chip->base + 0x08;
66 u32 pup = __raw_readl(reg);
71 return (__force samsung_gpio_pull_t)pup;
74 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
75 unsigned int off, samsung_gpio_pull_t pull)
78 case S3C_GPIO_PULL_NONE:
81 case S3C_GPIO_PULL_UP:
84 case S3C_GPIO_PULL_DOWN:
88 return samsung_gpio_setpull_updown(chip, off, pull);
91 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
94 samsung_gpio_pull_t pull;
96 pull = samsung_gpio_getpull_updown(chip, off);
100 pull = S3C_GPIO_PULL_UP;
104 pull = S3C_GPIO_PULL_NONE;
107 pull = S3C_GPIO_PULL_DOWN;
114 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
115 unsigned int off, samsung_gpio_pull_t pull,
116 samsung_gpio_pull_t updown)
118 void __iomem *reg = chip->base + 0x08;
119 u32 pup = __raw_readl(reg);
123 else if (pull == S3C_GPIO_PULL_NONE)
128 __raw_writel(pup, reg);
132 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
134 samsung_gpio_pull_t updown)
136 void __iomem *reg = chip->base + 0x08;
137 u32 pup = __raw_readl(reg);
140 return pup ? S3C_GPIO_PULL_NONE : updown;
143 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
146 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
149 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
150 unsigned int off, samsung_gpio_pull_t pull)
152 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
155 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
158 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
161 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
162 unsigned int off, samsung_gpio_pull_t pull)
164 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
168 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
169 * @chip: The gpio chip that is being configured.
170 * @off: The offset for the GPIO being configured.
171 * @cfg: The configuration value to set.
173 * This helper deal with the GPIO cases where the control register
174 * has two bits of configuration per gpio, which have the following
178 * 1x = special function
181 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
182 unsigned int off, unsigned int cfg)
184 void __iomem *reg = chip->base;
185 unsigned int shift = off * 2;
188 if (samsung_gpio_is_cfg_special(cfg)) {
196 con = __raw_readl(reg);
197 con &= ~(0x3 << shift);
199 __raw_writel(con, reg);
205 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
206 * @chip: The gpio chip that is being configured.
207 * @off: The offset for the GPIO being configured.
209 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
210 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
211 * S3C_GPIO_SPECIAL() macro.
214 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
219 con = __raw_readl(chip->base);
223 /* this conversion works for IN and OUT as well as special mode */
224 return S3C_GPIO_SPECIAL(con);
228 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
229 * @chip: The gpio chip that is being configured.
230 * @off: The offset for the GPIO being configured.
231 * @cfg: The configuration value to set.
233 * This helper deal with the GPIO cases where the control register has 4 bits
234 * of control per GPIO, generally in the form of:
237 * others = Special functions (dependent on bank)
239 * Note, since the code to deal with the case where there are two control
240 * registers instead of one, we do not have a separate set of functions for
244 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
245 unsigned int off, unsigned int cfg)
247 void __iomem *reg = chip->base;
248 unsigned int shift = (off & 7) * 4;
251 if (off < 8 && chip->chip.ngpio > 8)
254 if (samsung_gpio_is_cfg_special(cfg)) {
259 con = __raw_readl(reg);
260 con &= ~(0xf << shift);
262 __raw_writel(con, reg);
268 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
269 * @chip: The gpio chip that is being configured.
270 * @off: The offset for the GPIO being configured.
272 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
273 * register setting into a value the software can use, such as could be passed
274 * to samsung_gpio_setcfg_4bit().
276 * @sa samsung_gpio_getcfg_2bit
279 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
282 void __iomem *reg = chip->base;
283 unsigned int shift = (off & 7) * 4;
286 if (off < 8 && chip->chip.ngpio > 8)
289 con = __raw_readl(reg);
293 /* this conversion works for IN and OUT as well as special mode */
294 return S3C_GPIO_SPECIAL(con);
297 #ifdef CONFIG_PLAT_S3C24XX
299 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
300 * @chip: The gpio chip that is being configured.
301 * @off: The offset for the GPIO being configured.
302 * @cfg: The configuration value to set.
304 * This helper deal with the GPIO cases where the control register
305 * has one bit of configuration for the gpio, where setting the bit
306 * means the pin is in special function mode and unset means output.
309 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
310 unsigned int off, unsigned int cfg)
312 void __iomem *reg = chip->base;
313 unsigned int shift = off;
316 if (samsung_gpio_is_cfg_special(cfg)) {
319 /* Map output to 0, and SFN2 to 1 */
327 con = __raw_readl(reg);
328 con &= ~(0x1 << shift);
330 __raw_writel(con, reg);
336 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
337 * @chip: The gpio chip that is being configured.
338 * @off: The offset for the GPIO being configured.
340 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
341 * GPIO configuration value.
343 * @sa samsung_gpio_getcfg_2bit
344 * @sa samsung_gpio_getcfg_4bit
347 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
352 con = __raw_readl(chip->base);
357 return S3C_GPIO_SFN(con);
361 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
362 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
363 unsigned int off, unsigned int cfg)
365 void __iomem *reg = chip->base;
376 shift = (off & 7) * 4;
380 shift = ((off + 1) & 7) * 4;
384 shift = ((off + 1) & 7) * 4;
388 if (samsung_gpio_is_cfg_special(cfg)) {
393 con = __raw_readl(reg);
394 con &= ~(0xf << shift);
396 __raw_writel(con, reg);
402 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
405 for (; nr_chips > 0; nr_chips--, chipcfg++) {
406 if (!chipcfg->set_config)
407 chipcfg->set_config = samsung_gpio_setcfg_4bit;
408 if (!chipcfg->get_config)
409 chipcfg->get_config = samsung_gpio_getcfg_4bit;
410 if (!chipcfg->set_pull)
411 chipcfg->set_pull = samsung_gpio_setpull_updown;
412 if (!chipcfg->get_pull)
413 chipcfg->get_pull = samsung_gpio_getpull_updown;
417 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
418 .set_config = samsung_gpio_setcfg_2bit,
419 .get_config = samsung_gpio_getcfg_2bit,
422 #ifdef CONFIG_PLAT_S3C24XX
423 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
424 .set_config = s3c24xx_gpio_setcfg_abank,
425 .get_config = s3c24xx_gpio_getcfg_abank,
429 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
430 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
432 .set_config = s5p64x0_gpio_setcfg_rbank,
433 .get_config = samsung_gpio_getcfg_4bit,
434 .set_pull = samsung_gpio_setpull_updown,
435 .get_pull = samsung_gpio_getpull_updown,
439 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
454 .set_config = samsung_gpio_setcfg_2bit,
455 .get_config = samsung_gpio_getcfg_2bit,
459 .set_config = samsung_gpio_setcfg_2bit,
460 .get_config = samsung_gpio_getcfg_2bit,
464 .set_config = samsung_gpio_setcfg_2bit,
465 .get_config = samsung_gpio_getcfg_2bit,
468 .set_config = samsung_gpio_setcfg_2bit,
469 .get_config = samsung_gpio_getcfg_2bit,
474 * Default routines for controlling GPIO, based on the original S3C24XX
475 * GPIO functions which deal with the case where each gpio bank of the
476 * chip is as following:
478 * base + 0x00: Control register, 2 bits per gpio
479 * gpio n: 2 bits starting at (2*n)
480 * 00 = input, 01 = output, others mean special-function
481 * base + 0x04: Data register, 1 bit per gpio
485 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
487 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
488 void __iomem *base = ourchip->base;
492 samsung_gpio_lock(ourchip, flags);
494 con = __raw_readl(base + 0x00);
495 con &= ~(3 << (offset * 2));
497 __raw_writel(con, base + 0x00);
499 samsung_gpio_unlock(ourchip, flags);
503 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
504 unsigned offset, int value)
506 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
507 void __iomem *base = ourchip->base;
512 samsung_gpio_lock(ourchip, flags);
514 dat = __raw_readl(base + 0x04);
515 dat &= ~(1 << offset);
518 __raw_writel(dat, base + 0x04);
520 con = __raw_readl(base + 0x00);
521 con &= ~(3 << (offset * 2));
522 con |= 1 << (offset * 2);
524 __raw_writel(con, base + 0x00);
525 __raw_writel(dat, base + 0x04);
527 samsung_gpio_unlock(ourchip, flags);
532 * The samsung_gpiolib_4bit routines are to control the gpio banks where
533 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
536 * base + 0x00: Control register, 4 bits per gpio
537 * gpio n: 4 bits starting at (4*n)
538 * 0000 = input, 0001 = output, others mean special-function
539 * base + 0x04: Data register, 1 bit per gpio
542 * Note, since the data register is one bit per gpio and is at base + 0x4
543 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
544 * state of the output.
547 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
550 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
551 void __iomem *base = ourchip->base;
554 con = __raw_readl(base + GPIOCON_OFF);
555 if (ourchip->bitmap_gpio_int & BIT(offset))
556 con |= 0xf << con_4bit_shift(offset);
558 con &= ~(0xf << con_4bit_shift(offset));
559 __raw_writel(con, base + GPIOCON_OFF);
561 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
566 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
567 unsigned int offset, int value)
569 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
570 void __iomem *base = ourchip->base;
574 con = __raw_readl(base + GPIOCON_OFF);
575 con &= ~(0xf << con_4bit_shift(offset));
576 con |= 0x1 << con_4bit_shift(offset);
578 dat = __raw_readl(base + GPIODAT_OFF);
583 dat &= ~(1 << offset);
585 __raw_writel(dat, base + GPIODAT_OFF);
586 __raw_writel(con, base + GPIOCON_OFF);
587 __raw_writel(dat, base + GPIODAT_OFF);
589 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
595 * The next set of routines are for the case where the GPIO configuration
596 * registers are 4 bits per GPIO but there is more than one register (the
597 * bank has more than 8 GPIOs.
599 * This case is the similar to the 4 bit case, but the registers are as
602 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
603 * gpio n: 4 bits starting at (4*n)
604 * 0000 = input, 0001 = output, others mean special-function
605 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
606 * gpio n: 4 bits starting at (4*n)
607 * 0000 = input, 0001 = output, others mean special-function
608 * base + 0x08: Data register, 1 bit per gpio
611 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
612 * routines we store the 'base + 0x4' address so that these routines see
613 * the data register at ourchip->base + 0x04.
616 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
619 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
620 void __iomem *base = ourchip->base;
621 void __iomem *regcon = base;
629 con = __raw_readl(regcon);
630 con &= ~(0xf << con_4bit_shift(offset));
631 __raw_writel(con, regcon);
633 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
638 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
639 unsigned int offset, int value)
641 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
642 void __iomem *base = ourchip->base;
643 void __iomem *regcon = base;
646 unsigned con_offset = offset;
653 con = __raw_readl(regcon);
654 con &= ~(0xf << con_4bit_shift(con_offset));
655 con |= 0x1 << con_4bit_shift(con_offset);
657 dat = __raw_readl(base + GPIODAT_OFF);
662 dat &= ~(1 << offset);
664 __raw_writel(dat, base + GPIODAT_OFF);
665 __raw_writel(con, regcon);
666 __raw_writel(dat, base + GPIODAT_OFF);
668 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
673 #ifdef CONFIG_PLAT_S3C24XX
674 /* The next set of routines are for the case of s3c24xx bank a */
676 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
681 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
682 unsigned offset, int value)
684 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
685 void __iomem *base = ourchip->base;
690 local_irq_save(flags);
692 con = __raw_readl(base + 0x00);
693 dat = __raw_readl(base + 0x04);
695 dat &= ~(1 << offset);
699 __raw_writel(dat, base + 0x04);
701 con &= ~(1 << offset);
703 __raw_writel(con, base + 0x00);
704 __raw_writel(dat, base + 0x04);
706 local_irq_restore(flags);
711 /* The next set of routines are for the case of s5p64x0 bank r */
713 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
716 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
717 void __iomem *base = ourchip->base;
718 void __iomem *regcon = base;
738 samsung_gpio_lock(ourchip, flags);
740 con = __raw_readl(regcon);
741 con &= ~(0xf << con_4bit_shift(offset));
742 __raw_writel(con, regcon);
744 samsung_gpio_unlock(ourchip, flags);
749 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
750 unsigned int offset, int value)
752 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
753 void __iomem *base = ourchip->base;
754 void __iomem *regcon = base;
758 unsigned con_offset = offset;
760 switch (con_offset) {
776 samsung_gpio_lock(ourchip, flags);
778 con = __raw_readl(regcon);
779 con &= ~(0xf << con_4bit_shift(con_offset));
780 con |= 0x1 << con_4bit_shift(con_offset);
782 dat = __raw_readl(base + GPIODAT_OFF);
786 dat &= ~(1 << offset);
788 __raw_writel(con, regcon);
789 __raw_writel(dat, base + GPIODAT_OFF);
791 samsung_gpio_unlock(ourchip, flags);
796 static void samsung_gpiolib_set(struct gpio_chip *chip,
797 unsigned offset, int value)
799 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
800 void __iomem *base = ourchip->base;
804 samsung_gpio_lock(ourchip, flags);
806 dat = __raw_readl(base + 0x04);
807 dat &= ~(1 << offset);
810 __raw_writel(dat, base + 0x04);
812 samsung_gpio_unlock(ourchip, flags);
815 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
817 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
820 val = __raw_readl(ourchip->base + 0x04);
828 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
829 * for use with the configuration calls, and other parts of the s3c gpiolib
832 * Not all s3c support code will need this, as some configurations of cpu
833 * may only support one or two different configuration options and have an
834 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
835 * the machine support file should provide its own samsung_gpiolib_getchip()
836 * and any other necessary functions.
839 #ifdef CONFIG_S3C_GPIO_TRACK
840 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
842 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
847 gpn = chip->chip.base;
848 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
849 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
850 s3c_gpios[gpn] = chip;
853 #endif /* CONFIG_S3C_GPIO_TRACK */
856 * samsung_gpiolib_add() - add the Samsung gpio_chip.
857 * @chip: The chip to register
859 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
860 * information and makes the necessary alterations for the platform and
861 * notes the information for use with the configuration systems and any
862 * other parts of the system.
865 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
867 struct gpio_chip *gc = &chip->chip;
874 spin_lock_init(&chip->lock);
876 if (!gc->direction_input)
877 gc->direction_input = samsung_gpiolib_2bit_input;
878 if (!gc->direction_output)
879 gc->direction_output = samsung_gpiolib_2bit_output;
881 gc->set = samsung_gpiolib_set;
883 gc->get = samsung_gpiolib_get;
886 if (chip->pm != NULL) {
887 if (!chip->pm->save || !chip->pm->resume)
888 pr_err("gpio: %s has missing PM functions\n",
891 pr_err("gpio: %s has no PM function\n", gc->label);
894 /* gpiochip_add() prints own failure message on error. */
895 ret = gpiochip_add(gc);
897 s3c_gpiolib_track(chip);
900 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
901 int nr_chips, void __iomem *base)
904 struct gpio_chip *gc = &chip->chip;
906 for (i = 0 ; i < nr_chips; i++, chip++) {
907 /* skip banks not present on SoC */
908 if (chip->chip.base >= S3C_GPIO_END)
912 chip->config = &s3c24xx_gpiocfg_default;
914 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
915 if ((base != NULL) && (chip->base == NULL))
916 chip->base = base + ((i) * 0x10);
918 if (!gc->direction_input)
919 gc->direction_input = samsung_gpiolib_2bit_input;
920 if (!gc->direction_output)
921 gc->direction_output = samsung_gpiolib_2bit_output;
923 samsung_gpiolib_add(chip);
927 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
928 int nr_chips, void __iomem *base,
933 for (i = 0 ; i < nr_chips; i++, chip++) {
934 chip->chip.direction_input = samsung_gpiolib_2bit_input;
935 chip->chip.direction_output = samsung_gpiolib_2bit_output;
938 chip->config = &samsung_gpio_cfgs[7];
940 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
941 if ((base != NULL) && (chip->base == NULL))
942 chip->base = base + ((i) * offset);
944 samsung_gpiolib_add(chip);
949 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
950 * @chip: The gpio chip that is being configured.
951 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
953 * This helper deal with the GPIO cases where the control register has 4 bits
954 * of control per GPIO, generally in the form of:
957 * others = Special functions (dependent on bank)
959 * Note, since the code to deal with the case where there are two control
960 * registers instead of one, we do not have a separate set of function
961 * (samsung_gpiolib_add_4bit2_chips)for each case.
964 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
965 int nr_chips, void __iomem *base)
969 for (i = 0 ; i < nr_chips; i++, chip++) {
970 chip->chip.direction_input = samsung_gpiolib_4bit_input;
971 chip->chip.direction_output = samsung_gpiolib_4bit_output;
974 chip->config = &samsung_gpio_cfgs[2];
976 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
977 if ((base != NULL) && (chip->base == NULL))
978 chip->base = base + ((i) * 0x20);
980 chip->bitmap_gpio_int = 0;
982 samsung_gpiolib_add(chip);
986 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
989 for (; nr_chips > 0; nr_chips--, chip++) {
990 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
991 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
994 chip->config = &samsung_gpio_cfgs[2];
996 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
998 samsung_gpiolib_add(chip);
1002 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1005 for (; nr_chips > 0; nr_chips--, chip++) {
1006 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1007 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1010 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1012 samsung_gpiolib_add(chip);
1016 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1018 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1020 return samsung_chip->irq_base + offset;
1023 #ifdef CONFIG_PLAT_S3C24XX
1024 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1027 if (soc_is_s3c2412())
1028 return IRQ_EINT0_2412 + offset;
1030 return IRQ_EINT0 + offset;
1034 return IRQ_EINT4 + offset - 4;
1040 #ifdef CONFIG_ARCH_S3C64XX
1041 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1043 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1046 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1048 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1052 struct samsung_gpio_chip s3c24xx_gpios[] = {
1053 #ifdef CONFIG_PLAT_S3C24XX
1055 .config = &s3c24xx_gpiocfg_banka,
1057 .base = S3C2410_GPA(0),
1058 .owner = THIS_MODULE,
1061 .direction_input = s3c24xx_gpiolib_banka_input,
1062 .direction_output = s3c24xx_gpiolib_banka_output,
1066 .base = S3C2410_GPB(0),
1067 .owner = THIS_MODULE,
1073 .base = S3C2410_GPC(0),
1074 .owner = THIS_MODULE,
1080 .base = S3C2410_GPD(0),
1081 .owner = THIS_MODULE,
1087 .base = S3C2410_GPE(0),
1089 .owner = THIS_MODULE,
1094 .base = S3C2410_GPF(0),
1095 .owner = THIS_MODULE,
1098 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1101 .irq_base = IRQ_EINT8,
1103 .base = S3C2410_GPG(0),
1104 .owner = THIS_MODULE,
1107 .to_irq = samsung_gpiolib_to_irq,
1111 .base = S3C2410_GPH(0),
1112 .owner = THIS_MODULE,
1117 /* GPIOS for the S3C2443 and later devices. */
1119 .base = S3C2440_GPJCON,
1121 .base = S3C2410_GPJ(0),
1122 .owner = THIS_MODULE,
1127 .base = S3C2443_GPKCON,
1129 .base = S3C2410_GPK(0),
1130 .owner = THIS_MODULE,
1135 .base = S3C2443_GPLCON,
1137 .base = S3C2410_GPL(0),
1138 .owner = THIS_MODULE,
1143 .base = S3C2443_GPMCON,
1145 .base = S3C2410_GPM(0),
1146 .owner = THIS_MODULE,
1155 * GPIO bank summary:
1157 * Bank GPIOs Style SlpCon ExtInt Group
1163 * F 16 2Bit Yes 4 [1]
1165 * H 10 4Bit[2] Yes 6
1166 * I 16 2Bit Yes None
1167 * J 12 2Bit Yes None
1168 * K 16 4Bit[2] No None
1169 * L 15 4Bit[2] No None
1170 * M 6 4Bit No IRQ_EINT
1171 * N 16 2Bit No IRQ_EINT
1176 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1177 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1180 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1181 #ifdef CONFIG_ARCH_S3C64XX
1184 .base = S3C64XX_GPA(0),
1185 .ngpio = S3C64XX_GPIO_A_NR,
1190 .base = S3C64XX_GPB(0),
1191 .ngpio = S3C64XX_GPIO_B_NR,
1196 .base = S3C64XX_GPC(0),
1197 .ngpio = S3C64XX_GPIO_C_NR,
1202 .base = S3C64XX_GPD(0),
1203 .ngpio = S3C64XX_GPIO_D_NR,
1207 .config = &samsung_gpio_cfgs[0],
1209 .base = S3C64XX_GPE(0),
1210 .ngpio = S3C64XX_GPIO_E_NR,
1214 .base = S3C64XX_GPG_BASE,
1216 .base = S3C64XX_GPG(0),
1217 .ngpio = S3C64XX_GPIO_G_NR,
1221 .base = S3C64XX_GPM_BASE,
1222 .config = &samsung_gpio_cfgs[1],
1224 .base = S3C64XX_GPM(0),
1225 .ngpio = S3C64XX_GPIO_M_NR,
1227 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1233 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1234 #ifdef CONFIG_ARCH_S3C64XX
1236 .base = S3C64XX_GPH_BASE + 0x4,
1238 .base = S3C64XX_GPH(0),
1239 .ngpio = S3C64XX_GPIO_H_NR,
1243 .base = S3C64XX_GPK_BASE + 0x4,
1244 .config = &samsung_gpio_cfgs[0],
1246 .base = S3C64XX_GPK(0),
1247 .ngpio = S3C64XX_GPIO_K_NR,
1251 .base = S3C64XX_GPL_BASE + 0x4,
1252 .config = &samsung_gpio_cfgs[1],
1254 .base = S3C64XX_GPL(0),
1255 .ngpio = S3C64XX_GPIO_L_NR,
1257 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1263 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1264 #ifdef CONFIG_ARCH_S3C64XX
1266 .base = S3C64XX_GPF_BASE,
1267 .config = &samsung_gpio_cfgs[6],
1269 .base = S3C64XX_GPF(0),
1270 .ngpio = S3C64XX_GPIO_F_NR,
1274 .config = &samsung_gpio_cfgs[7],
1276 .base = S3C64XX_GPI(0),
1277 .ngpio = S3C64XX_GPIO_I_NR,
1281 .config = &samsung_gpio_cfgs[7],
1283 .base = S3C64XX_GPJ(0),
1284 .ngpio = S3C64XX_GPIO_J_NR,
1288 .config = &samsung_gpio_cfgs[6],
1290 .base = S3C64XX_GPO(0),
1291 .ngpio = S3C64XX_GPIO_O_NR,
1295 .config = &samsung_gpio_cfgs[6],
1297 .base = S3C64XX_GPP(0),
1298 .ngpio = S3C64XX_GPIO_P_NR,
1302 .config = &samsung_gpio_cfgs[6],
1304 .base = S3C64XX_GPQ(0),
1305 .ngpio = S3C64XX_GPIO_Q_NR,
1309 .base = S3C64XX_GPN_BASE,
1310 .irq_base = IRQ_EINT(0),
1311 .config = &samsung_gpio_cfgs[5],
1313 .base = S3C64XX_GPN(0),
1314 .ngpio = S3C64XX_GPIO_N_NR,
1316 .to_irq = samsung_gpiolib_to_irq,
1323 * S5P6440 GPIO bank summary:
1325 * Bank GPIOs Style SlpCon ExtInt Group
1329 * F 2 2Bit Yes 4 [1]
1331 * H 10 4Bit[2] Yes 6
1332 * I 16 2Bit Yes None
1333 * J 12 2Bit Yes None
1334 * N 16 2Bit No IRQ_EINT
1336 * R 15 4Bit[2] Yes 8
1339 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1340 #ifdef CONFIG_CPU_S5P6440
1343 .base = S5P6440_GPA(0),
1344 .ngpio = S5P6440_GPIO_A_NR,
1349 .base = S5P6440_GPB(0),
1350 .ngpio = S5P6440_GPIO_B_NR,
1355 .base = S5P6440_GPC(0),
1356 .ngpio = S5P6440_GPIO_C_NR,
1360 .base = S5P64X0_GPG_BASE,
1362 .base = S5P6440_GPG(0),
1363 .ngpio = S5P6440_GPIO_G_NR,
1370 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1371 #ifdef CONFIG_CPU_S5P6440
1373 .base = S5P64X0_GPH_BASE + 0x4,
1375 .base = S5P6440_GPH(0),
1376 .ngpio = S5P6440_GPIO_H_NR,
1383 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1384 #ifdef CONFIG_CPU_S5P6440
1386 .base = S5P64X0_GPR_BASE + 0x4,
1387 .config = &s5p64x0_gpio_cfg_rbank,
1389 .base = S5P6440_GPR(0),
1390 .ngpio = S5P6440_GPIO_R_NR,
1397 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1398 #ifdef CONFIG_CPU_S5P6440
1400 .base = S5P64X0_GPF_BASE,
1401 .config = &samsung_gpio_cfgs[6],
1403 .base = S5P6440_GPF(0),
1404 .ngpio = S5P6440_GPIO_F_NR,
1408 .base = S5P64X0_GPI_BASE,
1409 .config = &samsung_gpio_cfgs[4],
1411 .base = S5P6440_GPI(0),
1412 .ngpio = S5P6440_GPIO_I_NR,
1416 .base = S5P64X0_GPJ_BASE,
1417 .config = &samsung_gpio_cfgs[4],
1419 .base = S5P6440_GPJ(0),
1420 .ngpio = S5P6440_GPIO_J_NR,
1424 .base = S5P64X0_GPN_BASE,
1425 .config = &samsung_gpio_cfgs[5],
1427 .base = S5P6440_GPN(0),
1428 .ngpio = S5P6440_GPIO_N_NR,
1432 .base = S5P64X0_GPP_BASE,
1433 .config = &samsung_gpio_cfgs[6],
1435 .base = S5P6440_GPP(0),
1436 .ngpio = S5P6440_GPIO_P_NR,
1444 * S5P6450 GPIO bank summary:
1446 * Bank GPIOs Style SlpCon ExtInt Group
1452 * G 14 4Bit[2] Yes 5
1453 * H 10 4Bit[2] Yes 6
1454 * I 16 2Bit Yes None
1455 * J 12 2Bit Yes None
1457 * N 16 2Bit No IRQ_EINT
1459 * Q 14 2Bit Yes None
1460 * R 15 4Bit[2] Yes None
1463 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1464 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1467 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1468 #ifdef CONFIG_CPU_S5P6450
1471 .base = S5P6450_GPA(0),
1472 .ngpio = S5P6450_GPIO_A_NR,
1477 .base = S5P6450_GPB(0),
1478 .ngpio = S5P6450_GPIO_B_NR,
1483 .base = S5P6450_GPC(0),
1484 .ngpio = S5P6450_GPIO_C_NR,
1489 .base = S5P6450_GPD(0),
1490 .ngpio = S5P6450_GPIO_D_NR,
1494 .base = S5P6450_GPK_BASE,
1496 .base = S5P6450_GPK(0),
1497 .ngpio = S5P6450_GPIO_K_NR,
1504 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1505 #ifdef CONFIG_CPU_S5P6450
1507 .base = S5P64X0_GPG_BASE + 0x4,
1509 .base = S5P6450_GPG(0),
1510 .ngpio = S5P6450_GPIO_G_NR,
1514 .base = S5P64X0_GPH_BASE + 0x4,
1516 .base = S5P6450_GPH(0),
1517 .ngpio = S5P6450_GPIO_H_NR,
1524 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1525 #ifdef CONFIG_CPU_S5P6450
1527 .base = S5P64X0_GPR_BASE + 0x4,
1528 .config = &s5p64x0_gpio_cfg_rbank,
1530 .base = S5P6450_GPR(0),
1531 .ngpio = S5P6450_GPIO_R_NR,
1538 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1539 #ifdef CONFIG_CPU_S5P6450
1541 .base = S5P64X0_GPF_BASE,
1542 .config = &samsung_gpio_cfgs[6],
1544 .base = S5P6450_GPF(0),
1545 .ngpio = S5P6450_GPIO_F_NR,
1549 .base = S5P64X0_GPI_BASE,
1550 .config = &samsung_gpio_cfgs[4],
1552 .base = S5P6450_GPI(0),
1553 .ngpio = S5P6450_GPIO_I_NR,
1557 .base = S5P64X0_GPJ_BASE,
1558 .config = &samsung_gpio_cfgs[4],
1560 .base = S5P6450_GPJ(0),
1561 .ngpio = S5P6450_GPIO_J_NR,
1565 .base = S5P64X0_GPN_BASE,
1566 .config = &samsung_gpio_cfgs[5],
1568 .base = S5P6450_GPN(0),
1569 .ngpio = S5P6450_GPIO_N_NR,
1573 .base = S5P64X0_GPP_BASE,
1574 .config = &samsung_gpio_cfgs[6],
1576 .base = S5P6450_GPP(0),
1577 .ngpio = S5P6450_GPIO_P_NR,
1581 .base = S5P6450_GPQ_BASE,
1582 .config = &samsung_gpio_cfgs[5],
1584 .base = S5P6450_GPQ(0),
1585 .ngpio = S5P6450_GPIO_Q_NR,
1589 .base = S5P6450_GPS_BASE,
1590 .config = &samsung_gpio_cfgs[6],
1592 .base = S5P6450_GPS(0),
1593 .ngpio = S5P6450_GPIO_S_NR,
1601 * S5PC100 GPIO bank summary:
1603 * Bank GPIOs Style INT Type
1604 * A0 8 4Bit GPIO_INT0
1605 * A1 5 4Bit GPIO_INT1
1606 * B 8 4Bit GPIO_INT2
1607 * C 5 4Bit GPIO_INT3
1608 * D 7 4Bit GPIO_INT4
1609 * E0 8 4Bit GPIO_INT5
1610 * E1 6 4Bit GPIO_INT6
1611 * F0 8 4Bit GPIO_INT7
1612 * F1 8 4Bit GPIO_INT8
1613 * F2 8 4Bit GPIO_INT9
1614 * F3 4 4Bit GPIO_INT10
1615 * G0 8 4Bit GPIO_INT11
1616 * G1 3 4Bit GPIO_INT12
1617 * G2 7 4Bit GPIO_INT13
1618 * G3 7 4Bit GPIO_INT14
1619 * H0 8 4Bit WKUP_INT
1620 * H1 8 4Bit WKUP_INT
1621 * H2 8 4Bit WKUP_INT
1622 * H3 8 4Bit WKUP_INT
1623 * I 8 4Bit GPIO_INT15
1624 * J0 8 4Bit GPIO_INT16
1625 * J1 5 4Bit GPIO_INT17
1626 * J2 8 4Bit GPIO_INT18
1627 * J3 8 4Bit GPIO_INT19
1628 * J4 4 4Bit GPIO_INT20
1639 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1640 #ifdef CONFIG_CPU_S5PC100
1643 .base = S5PC100_GPA0(0),
1644 .ngpio = S5PC100_GPIO_A0_NR,
1649 .base = S5PC100_GPA1(0),
1650 .ngpio = S5PC100_GPIO_A1_NR,
1655 .base = S5PC100_GPB(0),
1656 .ngpio = S5PC100_GPIO_B_NR,
1661 .base = S5PC100_GPC(0),
1662 .ngpio = S5PC100_GPIO_C_NR,
1667 .base = S5PC100_GPD(0),
1668 .ngpio = S5PC100_GPIO_D_NR,
1673 .base = S5PC100_GPE0(0),
1674 .ngpio = S5PC100_GPIO_E0_NR,
1679 .base = S5PC100_GPE1(0),
1680 .ngpio = S5PC100_GPIO_E1_NR,
1685 .base = S5PC100_GPF0(0),
1686 .ngpio = S5PC100_GPIO_F0_NR,
1691 .base = S5PC100_GPF1(0),
1692 .ngpio = S5PC100_GPIO_F1_NR,
1697 .base = S5PC100_GPF2(0),
1698 .ngpio = S5PC100_GPIO_F2_NR,
1703 .base = S5PC100_GPF3(0),
1704 .ngpio = S5PC100_GPIO_F3_NR,
1709 .base = S5PC100_GPG0(0),
1710 .ngpio = S5PC100_GPIO_G0_NR,
1715 .base = S5PC100_GPG1(0),
1716 .ngpio = S5PC100_GPIO_G1_NR,
1721 .base = S5PC100_GPG2(0),
1722 .ngpio = S5PC100_GPIO_G2_NR,
1727 .base = S5PC100_GPG3(0),
1728 .ngpio = S5PC100_GPIO_G3_NR,
1733 .base = S5PC100_GPI(0),
1734 .ngpio = S5PC100_GPIO_I_NR,
1739 .base = S5PC100_GPJ0(0),
1740 .ngpio = S5PC100_GPIO_J0_NR,
1745 .base = S5PC100_GPJ1(0),
1746 .ngpio = S5PC100_GPIO_J1_NR,
1751 .base = S5PC100_GPJ2(0),
1752 .ngpio = S5PC100_GPIO_J2_NR,
1757 .base = S5PC100_GPJ3(0),
1758 .ngpio = S5PC100_GPIO_J3_NR,
1763 .base = S5PC100_GPJ4(0),
1764 .ngpio = S5PC100_GPIO_J4_NR,
1769 .base = S5PC100_GPK0(0),
1770 .ngpio = S5PC100_GPIO_K0_NR,
1775 .base = S5PC100_GPK1(0),
1776 .ngpio = S5PC100_GPIO_K1_NR,
1781 .base = S5PC100_GPK2(0),
1782 .ngpio = S5PC100_GPIO_K2_NR,
1787 .base = S5PC100_GPK3(0),
1788 .ngpio = S5PC100_GPIO_K3_NR,
1793 .base = S5PC100_GPL0(0),
1794 .ngpio = S5PC100_GPIO_L0_NR,
1799 .base = S5PC100_GPL1(0),
1800 .ngpio = S5PC100_GPIO_L1_NR,
1805 .base = S5PC100_GPL2(0),
1806 .ngpio = S5PC100_GPIO_L2_NR,
1811 .base = S5PC100_GPL3(0),
1812 .ngpio = S5PC100_GPIO_L3_NR,
1817 .base = S5PC100_GPL4(0),
1818 .ngpio = S5PC100_GPIO_L4_NR,
1822 .base = (S5P_VA_GPIO + 0xC00),
1823 .irq_base = IRQ_EINT(0),
1825 .base = S5PC100_GPH0(0),
1826 .ngpio = S5PC100_GPIO_H0_NR,
1828 .to_irq = samsung_gpiolib_to_irq,
1831 .base = (S5P_VA_GPIO + 0xC20),
1832 .irq_base = IRQ_EINT(8),
1834 .base = S5PC100_GPH1(0),
1835 .ngpio = S5PC100_GPIO_H1_NR,
1837 .to_irq = samsung_gpiolib_to_irq,
1840 .base = (S5P_VA_GPIO + 0xC40),
1841 .irq_base = IRQ_EINT(16),
1843 .base = S5PC100_GPH2(0),
1844 .ngpio = S5PC100_GPIO_H2_NR,
1846 .to_irq = samsung_gpiolib_to_irq,
1849 .base = (S5P_VA_GPIO + 0xC60),
1850 .irq_base = IRQ_EINT(24),
1852 .base = S5PC100_GPH3(0),
1853 .ngpio = S5PC100_GPIO_H3_NR,
1855 .to_irq = samsung_gpiolib_to_irq,
1862 * Followings are the gpio banks in S5PV210/S5PC110
1864 * The 'config' member when left to NULL, is initialized to the default
1865 * structure samsung_gpio_cfgs[3] in the init function below.
1867 * The 'base' member is also initialized in the init function below.
1868 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1869 * uses the above macro and depends on the banks being listed in order here.
1872 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1873 #ifdef CONFIG_CPU_S5PV210
1876 .base = S5PV210_GPA0(0),
1877 .ngpio = S5PV210_GPIO_A0_NR,
1882 .base = S5PV210_GPA1(0),
1883 .ngpio = S5PV210_GPIO_A1_NR,
1888 .base = S5PV210_GPB(0),
1889 .ngpio = S5PV210_GPIO_B_NR,
1894 .base = S5PV210_GPC0(0),
1895 .ngpio = S5PV210_GPIO_C0_NR,
1900 .base = S5PV210_GPC1(0),
1901 .ngpio = S5PV210_GPIO_C1_NR,
1906 .base = S5PV210_GPD0(0),
1907 .ngpio = S5PV210_GPIO_D0_NR,
1912 .base = S5PV210_GPD1(0),
1913 .ngpio = S5PV210_GPIO_D1_NR,
1918 .base = S5PV210_GPE0(0),
1919 .ngpio = S5PV210_GPIO_E0_NR,
1924 .base = S5PV210_GPE1(0),
1925 .ngpio = S5PV210_GPIO_E1_NR,
1930 .base = S5PV210_GPF0(0),
1931 .ngpio = S5PV210_GPIO_F0_NR,
1936 .base = S5PV210_GPF1(0),
1937 .ngpio = S5PV210_GPIO_F1_NR,
1942 .base = S5PV210_GPF2(0),
1943 .ngpio = S5PV210_GPIO_F2_NR,
1948 .base = S5PV210_GPF3(0),
1949 .ngpio = S5PV210_GPIO_F3_NR,
1954 .base = S5PV210_GPG0(0),
1955 .ngpio = S5PV210_GPIO_G0_NR,
1960 .base = S5PV210_GPG1(0),
1961 .ngpio = S5PV210_GPIO_G1_NR,
1966 .base = S5PV210_GPG2(0),
1967 .ngpio = S5PV210_GPIO_G2_NR,
1972 .base = S5PV210_GPG3(0),
1973 .ngpio = S5PV210_GPIO_G3_NR,
1978 .base = S5PV210_GPI(0),
1979 .ngpio = S5PV210_GPIO_I_NR,
1984 .base = S5PV210_GPJ0(0),
1985 .ngpio = S5PV210_GPIO_J0_NR,
1990 .base = S5PV210_GPJ1(0),
1991 .ngpio = S5PV210_GPIO_J1_NR,
1996 .base = S5PV210_GPJ2(0),
1997 .ngpio = S5PV210_GPIO_J2_NR,
2002 .base = S5PV210_GPJ3(0),
2003 .ngpio = S5PV210_GPIO_J3_NR,
2008 .base = S5PV210_GPJ4(0),
2009 .ngpio = S5PV210_GPIO_J4_NR,
2014 .base = S5PV210_MP01(0),
2015 .ngpio = S5PV210_GPIO_MP01_NR,
2020 .base = S5PV210_MP02(0),
2021 .ngpio = S5PV210_GPIO_MP02_NR,
2026 .base = S5PV210_MP03(0),
2027 .ngpio = S5PV210_GPIO_MP03_NR,
2032 .base = S5PV210_MP04(0),
2033 .ngpio = S5PV210_GPIO_MP04_NR,
2038 .base = S5PV210_MP05(0),
2039 .ngpio = S5PV210_GPIO_MP05_NR,
2043 .base = (S5P_VA_GPIO + 0xC00),
2044 .irq_base = IRQ_EINT(0),
2046 .base = S5PV210_GPH0(0),
2047 .ngpio = S5PV210_GPIO_H0_NR,
2049 .to_irq = samsung_gpiolib_to_irq,
2052 .base = (S5P_VA_GPIO + 0xC20),
2053 .irq_base = IRQ_EINT(8),
2055 .base = S5PV210_GPH1(0),
2056 .ngpio = S5PV210_GPIO_H1_NR,
2058 .to_irq = samsung_gpiolib_to_irq,
2061 .base = (S5P_VA_GPIO + 0xC40),
2062 .irq_base = IRQ_EINT(16),
2064 .base = S5PV210_GPH2(0),
2065 .ngpio = S5PV210_GPIO_H2_NR,
2067 .to_irq = samsung_gpiolib_to_irq,
2070 .base = (S5P_VA_GPIO + 0xC60),
2071 .irq_base = IRQ_EINT(24),
2073 .base = S5PV210_GPH3(0),
2074 .ngpio = S5PV210_GPIO_H3_NR,
2076 .to_irq = samsung_gpiolib_to_irq,
2082 /* TODO: cleanup soc_is_* */
2083 static __init int samsung_gpiolib_init(void)
2085 struct samsung_gpio_chip *chip;
2090 * Currently there are two drivers that can provide GPIO support for
2091 * Samsung SoCs. For device tree enabled platforms, the new
2092 * pinctrl-samsung driver is used, providing both GPIO and pin control
2093 * interfaces. For legacy (non-DT) platforms this driver is used.
2095 if (of_have_populated_dt())
2098 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2100 if (soc_is_s3c24xx()) {
2101 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
2102 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
2103 } else if (soc_is_s3c64xx()) {
2104 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
2105 ARRAY_SIZE(s3c64xx_gpios_2bit),
2106 S3C64XX_VA_GPIO + 0xE0, 0x20);
2107 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
2108 ARRAY_SIZE(s3c64xx_gpios_4bit),
2110 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2111 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2112 } else if (soc_is_s5p6440()) {
2113 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2114 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2115 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2116 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
2117 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
2118 ARRAY_SIZE(s5p6440_gpios_4bit2));
2119 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
2120 ARRAY_SIZE(s5p6440_gpios_rbank));
2121 } else if (soc_is_s5p6450()) {
2122 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
2123 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
2124 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
2125 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
2126 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
2127 ARRAY_SIZE(s5p6450_gpios_4bit2));
2128 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
2129 ARRAY_SIZE(s5p6450_gpios_rbank));
2130 } else if (soc_is_s5pc100()) {
2132 chip = s5pc100_gpios_4bit;
2133 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
2135 for (i = 0; i < nr_chips; i++, chip++) {
2136 if (!chip->config) {
2137 chip->config = &samsung_gpio_cfgs[3];
2138 chip->group = group++;
2141 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
2142 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2143 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2145 } else if (soc_is_s5pv210()) {
2147 chip = s5pv210_gpios_4bit;
2148 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
2150 for (i = 0; i < nr_chips; i++, chip++) {
2151 if (!chip->config) {
2152 chip->config = &samsung_gpio_cfgs[3];
2153 chip->group = group++;
2156 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
2157 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
2158 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2161 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
2167 core_initcall(samsung_gpiolib_init);
2169 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
2171 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2172 unsigned long flags;
2179 offset = pin - chip->chip.base;
2181 samsung_gpio_lock(chip, flags);
2182 ret = samsung_gpio_do_setcfg(chip, offset, config);
2183 samsung_gpio_unlock(chip, flags);
2187 EXPORT_SYMBOL(s3c_gpio_cfgpin);
2189 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
2194 for (; nr > 0; nr--, start++) {
2195 ret = s3c_gpio_cfgpin(start, cfg);
2202 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
2204 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
2205 unsigned int cfg, samsung_gpio_pull_t pull)
2209 for (; nr > 0; nr--, start++) {
2210 s3c_gpio_setpull(start, pull);
2211 ret = s3c_gpio_cfgpin(start, cfg);
2218 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
2220 unsigned s3c_gpio_getcfg(unsigned int pin)
2222 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2223 unsigned long flags;
2228 offset = pin - chip->chip.base;
2230 samsung_gpio_lock(chip, flags);
2231 ret = samsung_gpio_do_getcfg(chip, offset);
2232 samsung_gpio_unlock(chip, flags);
2237 EXPORT_SYMBOL(s3c_gpio_getcfg);
2239 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
2241 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2242 unsigned long flags;
2248 offset = pin - chip->chip.base;
2250 samsung_gpio_lock(chip, flags);
2251 ret = samsung_gpio_do_setpull(chip, offset, pull);
2252 samsung_gpio_unlock(chip, flags);
2256 EXPORT_SYMBOL(s3c_gpio_setpull);
2258 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
2260 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2261 unsigned long flags;
2266 offset = pin - chip->chip.base;
2268 samsung_gpio_lock(chip, flags);
2269 pup = samsung_gpio_do_getpull(chip, offset);
2270 samsung_gpio_unlock(chip, flags);
2273 return (__force samsung_gpio_pull_t)pup;
2275 EXPORT_SYMBOL(s3c_gpio_getpull);
2277 #ifdef CONFIG_S5P_GPIO_DRVSTR
2278 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
2280 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2289 off = pin - chip->chip.base;
2291 reg = chip->base + 0x0C;
2293 drvstr = __raw_readl(reg);
2294 drvstr = drvstr >> shift;
2297 return (__force s5p_gpio_drvstr_t)drvstr;
2299 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
2301 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
2303 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2312 off = pin - chip->chip.base;
2314 reg = chip->base + 0x0C;
2316 tmp = __raw_readl(reg);
2317 tmp &= ~(0x3 << shift);
2318 tmp |= drvstr << shift;
2320 __raw_writel(tmp, reg);
2324 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
2325 #endif /* CONFIG_S5P_GPIO_DRVSTR */
2327 #ifdef CONFIG_PLAT_S3C24XX
2328 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
2330 unsigned long flags;
2331 unsigned long misccr;
2333 local_irq_save(flags);
2334 misccr = __raw_readl(S3C24XX_MISCCR);
2337 __raw_writel(misccr, S3C24XX_MISCCR);
2338 local_irq_restore(flags);
2342 EXPORT_SYMBOL(s3c2410_modify_misccr);