2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
33 #include <mach/hardware.h>
35 #include <mach/regs-clock.h>
36 #include <mach/regs-gpio.h>
39 #include <plat/gpio-core.h>
40 #include <plat/gpio-cfg.h>
41 #include <plat/gpio-cfg-helpers.h>
42 #include <plat/gpio-fns.h>
46 #define gpio_dbg(x...) do { } while (0)
48 #define gpio_dbg(x...) printk(KERN_DEBUG x)
51 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
52 unsigned int off, samsung_gpio_pull_t pull)
54 void __iomem *reg = chip->base + 0x08;
58 pup = __raw_readl(reg);
61 __raw_writel(pup, reg);
66 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
69 void __iomem *reg = chip->base + 0x08;
71 u32 pup = __raw_readl(reg);
76 return (__force samsung_gpio_pull_t)pup;
79 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
80 unsigned int off, samsung_gpio_pull_t pull)
83 case S3C_GPIO_PULL_NONE:
86 case S3C_GPIO_PULL_UP:
89 case S3C_GPIO_PULL_DOWN:
93 return samsung_gpio_setpull_updown(chip, off, pull);
96 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
99 samsung_gpio_pull_t pull;
101 pull = samsung_gpio_getpull_updown(chip, off);
105 pull = S3C_GPIO_PULL_UP;
109 pull = S3C_GPIO_PULL_NONE;
112 pull = S3C_GPIO_PULL_DOWN;
119 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
120 unsigned int off, samsung_gpio_pull_t pull,
121 samsung_gpio_pull_t updown)
123 void __iomem *reg = chip->base + 0x08;
124 u32 pup = __raw_readl(reg);
128 else if (pull == S3C_GPIO_PULL_NONE)
133 __raw_writel(pup, reg);
137 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
139 samsung_gpio_pull_t updown)
141 void __iomem *reg = chip->base + 0x08;
142 u32 pup = __raw_readl(reg);
145 return pup ? S3C_GPIO_PULL_NONE : updown;
148 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
151 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
154 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
155 unsigned int off, samsung_gpio_pull_t pull)
157 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
160 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
163 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
166 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
167 unsigned int off, samsung_gpio_pull_t pull)
169 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
172 static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
173 unsigned int off, samsung_gpio_pull_t pull)
175 if (pull == S3C_GPIO_PULL_UP)
178 return samsung_gpio_setpull_updown(chip, off, pull);
181 static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
184 samsung_gpio_pull_t pull;
186 pull = samsung_gpio_getpull_updown(chip, off);
189 pull = S3C_GPIO_PULL_UP;
195 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
196 * @chip: The gpio chip that is being configured.
197 * @off: The offset for the GPIO being configured.
198 * @cfg: The configuration value to set.
200 * This helper deal with the GPIO cases where the control register
201 * has two bits of configuration per gpio, which have the following
205 * 1x = special function
208 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
209 unsigned int off, unsigned int cfg)
211 void __iomem *reg = chip->base;
212 unsigned int shift = off * 2;
215 if (samsung_gpio_is_cfg_special(cfg)) {
223 con = __raw_readl(reg);
224 con &= ~(0x3 << shift);
226 __raw_writel(con, reg);
232 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
233 * @chip: The gpio chip that is being configured.
234 * @off: The offset for the GPIO being configured.
236 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
237 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
238 * S3C_GPIO_SPECIAL() macro.
241 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
246 con = __raw_readl(chip->base);
250 /* this conversion works for IN and OUT as well as special mode */
251 return S3C_GPIO_SPECIAL(con);
255 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
256 * @chip: The gpio chip that is being configured.
257 * @off: The offset for the GPIO being configured.
258 * @cfg: The configuration value to set.
260 * This helper deal with the GPIO cases where the control register has 4 bits
261 * of control per GPIO, generally in the form of:
264 * others = Special functions (dependent on bank)
266 * Note, since the code to deal with the case where there are two control
267 * registers instead of one, we do not have a separate set of functions for
271 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
272 unsigned int off, unsigned int cfg)
274 void __iomem *reg = chip->base;
275 unsigned int shift = (off & 7) * 4;
278 if (off < 8 && chip->chip.ngpio > 8)
281 if (samsung_gpio_is_cfg_special(cfg)) {
286 con = __raw_readl(reg);
287 con &= ~(0xf << shift);
289 __raw_writel(con, reg);
295 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
296 * @chip: The gpio chip that is being configured.
297 * @off: The offset for the GPIO being configured.
299 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
300 * register setting into a value the software can use, such as could be passed
301 * to samsung_gpio_setcfg_4bit().
303 * @sa samsung_gpio_getcfg_2bit
306 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
309 void __iomem *reg = chip->base;
310 unsigned int shift = (off & 7) * 4;
313 if (off < 8 && chip->chip.ngpio > 8)
316 con = __raw_readl(reg);
320 /* this conversion works for IN and OUT as well as special mode */
321 return S3C_GPIO_SPECIAL(con);
324 #ifdef CONFIG_PLAT_S3C24XX
326 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
327 * @chip: The gpio chip that is being configured.
328 * @off: The offset for the GPIO being configured.
329 * @cfg: The configuration value to set.
331 * This helper deal with the GPIO cases where the control register
332 * has one bit of configuration for the gpio, where setting the bit
333 * means the pin is in special function mode and unset means output.
336 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
337 unsigned int off, unsigned int cfg)
339 void __iomem *reg = chip->base;
340 unsigned int shift = off;
343 if (samsung_gpio_is_cfg_special(cfg)) {
346 /* Map output to 0, and SFN2 to 1 */
354 con = __raw_readl(reg);
355 con &= ~(0x1 << shift);
357 __raw_writel(con, reg);
363 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
364 * @chip: The gpio chip that is being configured.
365 * @off: The offset for the GPIO being configured.
367 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
368 * GPIO configuration value.
370 * @sa samsung_gpio_getcfg_2bit
371 * @sa samsung_gpio_getcfg_4bit
374 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
379 con = __raw_readl(chip->base);
384 return S3C_GPIO_SFN(con);
388 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
389 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
390 unsigned int off, unsigned int cfg)
392 void __iomem *reg = chip->base;
403 shift = (off & 7) * 4;
407 shift = ((off + 1) & 7) * 4;
410 shift = ((off + 1) & 7) * 4;
414 if (samsung_gpio_is_cfg_special(cfg)) {
419 con = __raw_readl(reg);
420 con &= ~(0xf << shift);
422 __raw_writel(con, reg);
428 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
431 for (; nr_chips > 0; nr_chips--, chipcfg++) {
432 if (!chipcfg->set_config)
433 chipcfg->set_config = samsung_gpio_setcfg_4bit;
434 if (!chipcfg->get_config)
435 chipcfg->get_config = samsung_gpio_getcfg_4bit;
436 if (!chipcfg->set_pull)
437 chipcfg->set_pull = samsung_gpio_setpull_updown;
438 if (!chipcfg->get_pull)
439 chipcfg->get_pull = samsung_gpio_getpull_updown;
443 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
444 .set_config = samsung_gpio_setcfg_2bit,
445 .get_config = samsung_gpio_getcfg_2bit,
448 #ifdef CONFIG_PLAT_S3C24XX
449 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
450 .set_config = s3c24xx_gpio_setcfg_abank,
451 .get_config = s3c24xx_gpio_getcfg_abank,
455 #if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
456 static struct samsung_gpio_cfg exynos_gpio_cfg = {
457 .set_pull = exynos_gpio_setpull,
458 .get_pull = exynos_gpio_getpull,
459 .set_config = samsung_gpio_setcfg_4bit,
460 .get_config = samsung_gpio_getcfg_4bit,
464 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
465 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
467 .set_config = s5p64x0_gpio_setcfg_rbank,
468 .get_config = samsung_gpio_getcfg_4bit,
469 .set_pull = samsung_gpio_setpull_updown,
470 .get_pull = samsung_gpio_getpull_updown,
474 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
489 .set_config = samsung_gpio_setcfg_2bit,
490 .get_config = samsung_gpio_getcfg_2bit,
494 .set_config = samsung_gpio_setcfg_2bit,
495 .get_config = samsung_gpio_getcfg_2bit,
499 .set_config = samsung_gpio_setcfg_2bit,
500 .get_config = samsung_gpio_getcfg_2bit,
503 .set_config = samsung_gpio_setcfg_2bit,
504 .get_config = samsung_gpio_getcfg_2bit,
507 .set_pull = exynos_gpio_setpull,
508 .get_pull = exynos_gpio_getpull,
512 .set_pull = exynos_gpio_setpull,
513 .get_pull = exynos_gpio_getpull,
518 * Default routines for controlling GPIO, based on the original S3C24XX
519 * GPIO functions which deal with the case where each gpio bank of the
520 * chip is as following:
522 * base + 0x00: Control register, 2 bits per gpio
523 * gpio n: 2 bits starting at (2*n)
524 * 00 = input, 01 = output, others mean special-function
525 * base + 0x04: Data register, 1 bit per gpio
529 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
531 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
532 void __iomem *base = ourchip->base;
536 samsung_gpio_lock(ourchip, flags);
538 con = __raw_readl(base + 0x00);
539 con &= ~(3 << (offset * 2));
541 __raw_writel(con, base + 0x00);
543 samsung_gpio_unlock(ourchip, flags);
547 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
548 unsigned offset, int value)
550 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
551 void __iomem *base = ourchip->base;
556 samsung_gpio_lock(ourchip, flags);
558 dat = __raw_readl(base + 0x04);
559 dat &= ~(1 << offset);
562 __raw_writel(dat, base + 0x04);
564 con = __raw_readl(base + 0x00);
565 con &= ~(3 << (offset * 2));
566 con |= 1 << (offset * 2);
568 __raw_writel(con, base + 0x00);
569 __raw_writel(dat, base + 0x04);
571 samsung_gpio_unlock(ourchip, flags);
576 * The samsung_gpiolib_4bit routines are to control the gpio banks where
577 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
580 * base + 0x00: Control register, 4 bits per gpio
581 * gpio n: 4 bits starting at (4*n)
582 * 0000 = input, 0001 = output, others mean special-function
583 * base + 0x04: Data register, 1 bit per gpio
586 * Note, since the data register is one bit per gpio and is at base + 0x4
587 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
588 * state of the output.
591 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
594 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
595 void __iomem *base = ourchip->base;
598 con = __raw_readl(base + GPIOCON_OFF);
599 con &= ~(0xf << con_4bit_shift(offset));
600 __raw_writel(con, base + GPIOCON_OFF);
602 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
607 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
608 unsigned int offset, int value)
610 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
611 void __iomem *base = ourchip->base;
615 con = __raw_readl(base + GPIOCON_OFF);
616 con &= ~(0xf << con_4bit_shift(offset));
617 con |= 0x1 << con_4bit_shift(offset);
619 dat = __raw_readl(base + GPIODAT_OFF);
624 dat &= ~(1 << offset);
626 __raw_writel(dat, base + GPIODAT_OFF);
627 __raw_writel(con, base + GPIOCON_OFF);
628 __raw_writel(dat, base + GPIODAT_OFF);
630 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
636 * The next set of routines are for the case where the GPIO configuration
637 * registers are 4 bits per GPIO but there is more than one register (the
638 * bank has more than 8 GPIOs.
640 * This case is the similar to the 4 bit case, but the registers are as
643 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
644 * gpio n: 4 bits starting at (4*n)
645 * 0000 = input, 0001 = output, others mean special-function
646 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
647 * gpio n: 4 bits starting at (4*n)
648 * 0000 = input, 0001 = output, others mean special-function
649 * base + 0x08: Data register, 1 bit per gpio
652 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
653 * routines we store the 'base + 0x4' address so that these routines see
654 * the data register at ourchip->base + 0x04.
657 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
660 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
661 void __iomem *base = ourchip->base;
662 void __iomem *regcon = base;
670 con = __raw_readl(regcon);
671 con &= ~(0xf << con_4bit_shift(offset));
672 __raw_writel(con, regcon);
674 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
679 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
680 unsigned int offset, int value)
682 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
683 void __iomem *base = ourchip->base;
684 void __iomem *regcon = base;
687 unsigned con_offset = offset;
694 con = __raw_readl(regcon);
695 con &= ~(0xf << con_4bit_shift(con_offset));
696 con |= 0x1 << con_4bit_shift(con_offset);
698 dat = __raw_readl(base + GPIODAT_OFF);
703 dat &= ~(1 << offset);
705 __raw_writel(dat, base + GPIODAT_OFF);
706 __raw_writel(con, regcon);
707 __raw_writel(dat, base + GPIODAT_OFF);
709 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
714 #ifdef CONFIG_PLAT_S3C24XX
715 /* The next set of routines are for the case of s3c24xx bank a */
717 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
722 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
723 unsigned offset, int value)
725 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
726 void __iomem *base = ourchip->base;
731 local_irq_save(flags);
733 con = __raw_readl(base + 0x00);
734 dat = __raw_readl(base + 0x04);
736 dat &= ~(1 << offset);
740 __raw_writel(dat, base + 0x04);
742 con &= ~(1 << offset);
744 __raw_writel(con, base + 0x00);
745 __raw_writel(dat, base + 0x04);
747 local_irq_restore(flags);
752 /* The next set of routines are for the case of s5p64x0 bank r */
754 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
757 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
758 void __iomem *base = ourchip->base;
759 void __iomem *regcon = base;
779 samsung_gpio_lock(ourchip, flags);
781 con = __raw_readl(regcon);
782 con &= ~(0xf << con_4bit_shift(offset));
783 __raw_writel(con, regcon);
785 samsung_gpio_unlock(ourchip, flags);
790 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
791 unsigned int offset, int value)
793 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
794 void __iomem *base = ourchip->base;
795 void __iomem *regcon = base;
799 unsigned con_offset = offset;
801 switch (con_offset) {
817 samsung_gpio_lock(ourchip, flags);
819 con = __raw_readl(regcon);
820 con &= ~(0xf << con_4bit_shift(con_offset));
821 con |= 0x1 << con_4bit_shift(con_offset);
823 dat = __raw_readl(base + GPIODAT_OFF);
827 dat &= ~(1 << offset);
829 __raw_writel(con, regcon);
830 __raw_writel(dat, base + GPIODAT_OFF);
832 samsung_gpio_unlock(ourchip, flags);
837 static void samsung_gpiolib_set(struct gpio_chip *chip,
838 unsigned offset, int value)
840 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
841 void __iomem *base = ourchip->base;
845 samsung_gpio_lock(ourchip, flags);
847 dat = __raw_readl(base + 0x04);
848 dat &= ~(1 << offset);
851 __raw_writel(dat, base + 0x04);
853 samsung_gpio_unlock(ourchip, flags);
856 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
858 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
861 val = __raw_readl(ourchip->base + 0x04);
869 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
870 * for use with the configuration calls, and other parts of the s3c gpiolib
873 * Not all s3c support code will need this, as some configurations of cpu
874 * may only support one or two different configuration options and have an
875 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
876 * the machine support file should provide its own samsung_gpiolib_getchip()
877 * and any other necessary functions.
880 #ifdef CONFIG_S3C_GPIO_TRACK
881 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
883 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
888 gpn = chip->chip.base;
889 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
890 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
891 s3c_gpios[gpn] = chip;
894 #endif /* CONFIG_S3C_GPIO_TRACK */
897 * samsung_gpiolib_add() - add the Samsung gpio_chip.
898 * @chip: The chip to register
900 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
901 * information and makes the necessary alterations for the platform and
902 * notes the information for use with the configuration systems and any
903 * other parts of the system.
906 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
908 struct gpio_chip *gc = &chip->chip;
915 spin_lock_init(&chip->lock);
917 if (!gc->direction_input)
918 gc->direction_input = samsung_gpiolib_2bit_input;
919 if (!gc->direction_output)
920 gc->direction_output = samsung_gpiolib_2bit_output;
922 gc->set = samsung_gpiolib_set;
924 gc->get = samsung_gpiolib_get;
927 if (chip->pm != NULL) {
928 if (!chip->pm->save || !chip->pm->resume)
929 printk(KERN_ERR "gpio: %s has missing PM functions\n",
932 printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
935 /* gpiochip_add() prints own failure message on error. */
936 ret = gpiochip_add(gc);
938 s3c_gpiolib_track(chip);
941 #if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
942 static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
943 const struct of_phandle_args *gpiospec, u32 *flags)
947 if (WARN_ON(gc->of_gpio_n_cells < 3))
950 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
953 if (gpiospec->args[0] > gc->ngpio)
956 pin = gc->base + gpiospec->args[0];
958 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
959 pr_warn("gpio_xlate: failed to set pin function\n");
960 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
961 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
964 *flags = gpiospec->args[2] >> 16;
966 return gpiospec->args[0];
969 static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
970 { .compatible = "samsung,s3c24xx-gpio", },
974 static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
975 u64 base, u64 offset)
977 struct gpio_chip *gc = &chip->chip;
980 if (!of_have_populated_dt())
983 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
984 gc->of_node = of_find_matching_node_by_address(NULL,
985 s3c24xx_gpio_dt_match, address);
987 pr_info("gpio: device tree node not found for gpio controller"
988 " with base address %08llx\n", address);
991 gc->of_gpio_n_cells = 3;
992 gc->of_xlate = s3c24xx_gpio_xlate;
995 static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
996 u64 base, u64 offset)
1000 #endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
1002 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
1003 int nr_chips, void __iomem *base)
1006 struct gpio_chip *gc = &chip->chip;
1008 for (i = 0 ; i < nr_chips; i++, chip++) {
1009 /* skip banks not present on SoC */
1010 if (chip->chip.base >= S3C_GPIO_END)
1014 chip->config = &s3c24xx_gpiocfg_default;
1016 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1017 if ((base != NULL) && (chip->base == NULL))
1018 chip->base = base + ((i) * 0x10);
1020 if (!gc->direction_input)
1021 gc->direction_input = samsung_gpiolib_2bit_input;
1022 if (!gc->direction_output)
1023 gc->direction_output = samsung_gpiolib_2bit_output;
1025 samsung_gpiolib_add(chip);
1027 s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
1031 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
1032 int nr_chips, void __iomem *base,
1033 unsigned int offset)
1037 for (i = 0 ; i < nr_chips; i++, chip++) {
1038 chip->chip.direction_input = samsung_gpiolib_2bit_input;
1039 chip->chip.direction_output = samsung_gpiolib_2bit_output;
1042 chip->config = &samsung_gpio_cfgs[7];
1044 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1045 if ((base != NULL) && (chip->base == NULL))
1046 chip->base = base + ((i) * offset);
1048 samsung_gpiolib_add(chip);
1053 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
1054 * @chip: The gpio chip that is being configured.
1055 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
1057 * This helper deal with the GPIO cases where the control register has 4 bits
1058 * of control per GPIO, generally in the form of:
1061 * others = Special functions (dependent on bank)
1063 * Note, since the code to deal with the case where there are two control
1064 * registers instead of one, we do not have a separate set of function
1065 * (samsung_gpiolib_add_4bit2_chips)for each case.
1068 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1069 int nr_chips, void __iomem *base)
1073 for (i = 0 ; i < nr_chips; i++, chip++) {
1074 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1075 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1078 chip->config = &samsung_gpio_cfgs[2];
1080 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1081 if ((base != NULL) && (chip->base == NULL))
1082 chip->base = base + ((i) * 0x20);
1084 samsung_gpiolib_add(chip);
1088 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1091 for (; nr_chips > 0; nr_chips--, chip++) {
1092 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1093 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1096 chip->config = &samsung_gpio_cfgs[2];
1098 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1100 samsung_gpiolib_add(chip);
1104 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1107 for (; nr_chips > 0; nr_chips--, chip++) {
1108 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1109 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1112 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1114 samsung_gpiolib_add(chip);
1118 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1120 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1122 return samsung_chip->irq_base + offset;
1125 #ifdef CONFIG_PLAT_S3C24XX
1126 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1129 return IRQ_EINT0 + offset;
1132 return IRQ_EINT4 + offset - 4;
1138 #ifdef CONFIG_PLAT_S3C64XX
1139 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1141 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1144 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1146 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1150 struct samsung_gpio_chip s3c24xx_gpios[] = {
1151 #ifdef CONFIG_PLAT_S3C24XX
1153 .config = &s3c24xx_gpiocfg_banka,
1155 .base = S3C2410_GPA(0),
1156 .owner = THIS_MODULE,
1159 .direction_input = s3c24xx_gpiolib_banka_input,
1160 .direction_output = s3c24xx_gpiolib_banka_output,
1164 .base = S3C2410_GPB(0),
1165 .owner = THIS_MODULE,
1171 .base = S3C2410_GPC(0),
1172 .owner = THIS_MODULE,
1178 .base = S3C2410_GPD(0),
1179 .owner = THIS_MODULE,
1185 .base = S3C2410_GPE(0),
1187 .owner = THIS_MODULE,
1192 .base = S3C2410_GPF(0),
1193 .owner = THIS_MODULE,
1196 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1199 .irq_base = IRQ_EINT8,
1201 .base = S3C2410_GPG(0),
1202 .owner = THIS_MODULE,
1205 .to_irq = samsung_gpiolib_to_irq,
1209 .base = S3C2410_GPH(0),
1210 .owner = THIS_MODULE,
1215 /* GPIOS for the S3C2443 and later devices. */
1217 .base = S3C2440_GPJCON,
1219 .base = S3C2410_GPJ(0),
1220 .owner = THIS_MODULE,
1225 .base = S3C2443_GPKCON,
1227 .base = S3C2410_GPK(0),
1228 .owner = THIS_MODULE,
1233 .base = S3C2443_GPLCON,
1235 .base = S3C2410_GPL(0),
1236 .owner = THIS_MODULE,
1241 .base = S3C2443_GPMCON,
1243 .base = S3C2410_GPM(0),
1244 .owner = THIS_MODULE,
1253 * GPIO bank summary:
1255 * Bank GPIOs Style SlpCon ExtInt Group
1261 * F 16 2Bit Yes 4 [1]
1263 * H 10 4Bit[2] Yes 6
1264 * I 16 2Bit Yes None
1265 * J 12 2Bit Yes None
1266 * K 16 4Bit[2] No None
1267 * L 15 4Bit[2] No None
1268 * M 6 4Bit No IRQ_EINT
1269 * N 16 2Bit No IRQ_EINT
1274 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1275 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1278 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1279 #ifdef CONFIG_PLAT_S3C64XX
1282 .base = S3C64XX_GPA(0),
1283 .ngpio = S3C64XX_GPIO_A_NR,
1288 .base = S3C64XX_GPB(0),
1289 .ngpio = S3C64XX_GPIO_B_NR,
1294 .base = S3C64XX_GPC(0),
1295 .ngpio = S3C64XX_GPIO_C_NR,
1300 .base = S3C64XX_GPD(0),
1301 .ngpio = S3C64XX_GPIO_D_NR,
1305 .config = &samsung_gpio_cfgs[0],
1307 .base = S3C64XX_GPE(0),
1308 .ngpio = S3C64XX_GPIO_E_NR,
1312 .base = S3C64XX_GPG_BASE,
1314 .base = S3C64XX_GPG(0),
1315 .ngpio = S3C64XX_GPIO_G_NR,
1319 .base = S3C64XX_GPM_BASE,
1320 .config = &samsung_gpio_cfgs[1],
1322 .base = S3C64XX_GPM(0),
1323 .ngpio = S3C64XX_GPIO_M_NR,
1325 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1331 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1332 #ifdef CONFIG_PLAT_S3C64XX
1334 .base = S3C64XX_GPH_BASE + 0x4,
1336 .base = S3C64XX_GPH(0),
1337 .ngpio = S3C64XX_GPIO_H_NR,
1341 .base = S3C64XX_GPK_BASE + 0x4,
1342 .config = &samsung_gpio_cfgs[0],
1344 .base = S3C64XX_GPK(0),
1345 .ngpio = S3C64XX_GPIO_K_NR,
1349 .base = S3C64XX_GPL_BASE + 0x4,
1350 .config = &samsung_gpio_cfgs[1],
1352 .base = S3C64XX_GPL(0),
1353 .ngpio = S3C64XX_GPIO_L_NR,
1355 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1361 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1362 #ifdef CONFIG_PLAT_S3C64XX
1364 .base = S3C64XX_GPF_BASE,
1365 .config = &samsung_gpio_cfgs[6],
1367 .base = S3C64XX_GPF(0),
1368 .ngpio = S3C64XX_GPIO_F_NR,
1372 .config = &samsung_gpio_cfgs[7],
1374 .base = S3C64XX_GPI(0),
1375 .ngpio = S3C64XX_GPIO_I_NR,
1379 .config = &samsung_gpio_cfgs[7],
1381 .base = S3C64XX_GPJ(0),
1382 .ngpio = S3C64XX_GPIO_J_NR,
1386 .config = &samsung_gpio_cfgs[6],
1388 .base = S3C64XX_GPO(0),
1389 .ngpio = S3C64XX_GPIO_O_NR,
1393 .config = &samsung_gpio_cfgs[6],
1395 .base = S3C64XX_GPP(0),
1396 .ngpio = S3C64XX_GPIO_P_NR,
1400 .config = &samsung_gpio_cfgs[6],
1402 .base = S3C64XX_GPQ(0),
1403 .ngpio = S3C64XX_GPIO_Q_NR,
1407 .base = S3C64XX_GPN_BASE,
1408 .irq_base = IRQ_EINT(0),
1409 .config = &samsung_gpio_cfgs[5],
1411 .base = S3C64XX_GPN(0),
1412 .ngpio = S3C64XX_GPIO_N_NR,
1414 .to_irq = samsung_gpiolib_to_irq,
1421 * S5P6440 GPIO bank summary:
1423 * Bank GPIOs Style SlpCon ExtInt Group
1427 * F 2 2Bit Yes 4 [1]
1429 * H 10 4Bit[2] Yes 6
1430 * I 16 2Bit Yes None
1431 * J 12 2Bit Yes None
1432 * N 16 2Bit No IRQ_EINT
1434 * R 15 4Bit[2] Yes 8
1437 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1438 #ifdef CONFIG_CPU_S5P6440
1441 .base = S5P6440_GPA(0),
1442 .ngpio = S5P6440_GPIO_A_NR,
1447 .base = S5P6440_GPB(0),
1448 .ngpio = S5P6440_GPIO_B_NR,
1453 .base = S5P6440_GPC(0),
1454 .ngpio = S5P6440_GPIO_C_NR,
1458 .base = S5P64X0_GPG_BASE,
1460 .base = S5P6440_GPG(0),
1461 .ngpio = S5P6440_GPIO_G_NR,
1468 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1469 #ifdef CONFIG_CPU_S5P6440
1471 .base = S5P64X0_GPH_BASE + 0x4,
1473 .base = S5P6440_GPH(0),
1474 .ngpio = S5P6440_GPIO_H_NR,
1481 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1482 #ifdef CONFIG_CPU_S5P6440
1484 .base = S5P64X0_GPR_BASE + 0x4,
1485 .config = &s5p64x0_gpio_cfg_rbank,
1487 .base = S5P6440_GPR(0),
1488 .ngpio = S5P6440_GPIO_R_NR,
1495 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1496 #ifdef CONFIG_CPU_S5P6440
1498 .base = S5P64X0_GPF_BASE,
1499 .config = &samsung_gpio_cfgs[6],
1501 .base = S5P6440_GPF(0),
1502 .ngpio = S5P6440_GPIO_F_NR,
1506 .base = S5P64X0_GPI_BASE,
1507 .config = &samsung_gpio_cfgs[4],
1509 .base = S5P6440_GPI(0),
1510 .ngpio = S5P6440_GPIO_I_NR,
1514 .base = S5P64X0_GPJ_BASE,
1515 .config = &samsung_gpio_cfgs[4],
1517 .base = S5P6440_GPJ(0),
1518 .ngpio = S5P6440_GPIO_J_NR,
1522 .base = S5P64X0_GPN_BASE,
1523 .config = &samsung_gpio_cfgs[5],
1525 .base = S5P6440_GPN(0),
1526 .ngpio = S5P6440_GPIO_N_NR,
1530 .base = S5P64X0_GPP_BASE,
1531 .config = &samsung_gpio_cfgs[6],
1533 .base = S5P6440_GPP(0),
1534 .ngpio = S5P6440_GPIO_P_NR,
1542 * S5P6450 GPIO bank summary:
1544 * Bank GPIOs Style SlpCon ExtInt Group
1550 * G 14 4Bit[2] Yes 5
1551 * H 10 4Bit[2] Yes 6
1552 * I 16 2Bit Yes None
1553 * J 12 2Bit Yes None
1555 * N 16 2Bit No IRQ_EINT
1557 * Q 14 2Bit Yes None
1558 * R 15 4Bit[2] Yes None
1561 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1562 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1565 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1566 #ifdef CONFIG_CPU_S5P6450
1569 .base = S5P6450_GPA(0),
1570 .ngpio = S5P6450_GPIO_A_NR,
1575 .base = S5P6450_GPB(0),
1576 .ngpio = S5P6450_GPIO_B_NR,
1581 .base = S5P6450_GPC(0),
1582 .ngpio = S5P6450_GPIO_C_NR,
1587 .base = S5P6450_GPD(0),
1588 .ngpio = S5P6450_GPIO_D_NR,
1592 .base = S5P6450_GPK_BASE,
1594 .base = S5P6450_GPK(0),
1595 .ngpio = S5P6450_GPIO_K_NR,
1602 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1603 #ifdef CONFIG_CPU_S5P6450
1605 .base = S5P64X0_GPG_BASE + 0x4,
1607 .base = S5P6450_GPG(0),
1608 .ngpio = S5P6450_GPIO_G_NR,
1612 .base = S5P64X0_GPH_BASE + 0x4,
1614 .base = S5P6450_GPH(0),
1615 .ngpio = S5P6450_GPIO_H_NR,
1622 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1623 #ifdef CONFIG_CPU_S5P6450
1625 .base = S5P64X0_GPR_BASE + 0x4,
1626 .config = &s5p64x0_gpio_cfg_rbank,
1628 .base = S5P6450_GPR(0),
1629 .ngpio = S5P6450_GPIO_R_NR,
1636 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1637 #ifdef CONFIG_CPU_S5P6450
1639 .base = S5P64X0_GPF_BASE,
1640 .config = &samsung_gpio_cfgs[6],
1642 .base = S5P6450_GPF(0),
1643 .ngpio = S5P6450_GPIO_F_NR,
1647 .base = S5P64X0_GPI_BASE,
1648 .config = &samsung_gpio_cfgs[4],
1650 .base = S5P6450_GPI(0),
1651 .ngpio = S5P6450_GPIO_I_NR,
1655 .base = S5P64X0_GPJ_BASE,
1656 .config = &samsung_gpio_cfgs[4],
1658 .base = S5P6450_GPJ(0),
1659 .ngpio = S5P6450_GPIO_J_NR,
1663 .base = S5P64X0_GPN_BASE,
1664 .config = &samsung_gpio_cfgs[5],
1666 .base = S5P6450_GPN(0),
1667 .ngpio = S5P6450_GPIO_N_NR,
1671 .base = S5P64X0_GPP_BASE,
1672 .config = &samsung_gpio_cfgs[6],
1674 .base = S5P6450_GPP(0),
1675 .ngpio = S5P6450_GPIO_P_NR,
1679 .base = S5P6450_GPQ_BASE,
1680 .config = &samsung_gpio_cfgs[5],
1682 .base = S5P6450_GPQ(0),
1683 .ngpio = S5P6450_GPIO_Q_NR,
1687 .base = S5P6450_GPS_BASE,
1688 .config = &samsung_gpio_cfgs[6],
1690 .base = S5P6450_GPS(0),
1691 .ngpio = S5P6450_GPIO_S_NR,
1699 * S5PC100 GPIO bank summary:
1701 * Bank GPIOs Style INT Type
1702 * A0 8 4Bit GPIO_INT0
1703 * A1 5 4Bit GPIO_INT1
1704 * B 8 4Bit GPIO_INT2
1705 * C 5 4Bit GPIO_INT3
1706 * D 7 4Bit GPIO_INT4
1707 * E0 8 4Bit GPIO_INT5
1708 * E1 6 4Bit GPIO_INT6
1709 * F0 8 4Bit GPIO_INT7
1710 * F1 8 4Bit GPIO_INT8
1711 * F2 8 4Bit GPIO_INT9
1712 * F3 4 4Bit GPIO_INT10
1713 * G0 8 4Bit GPIO_INT11
1714 * G1 3 4Bit GPIO_INT12
1715 * G2 7 4Bit GPIO_INT13
1716 * G3 7 4Bit GPIO_INT14
1717 * H0 8 4Bit WKUP_INT
1718 * H1 8 4Bit WKUP_INT
1719 * H2 8 4Bit WKUP_INT
1720 * H3 8 4Bit WKUP_INT
1721 * I 8 4Bit GPIO_INT15
1722 * J0 8 4Bit GPIO_INT16
1723 * J1 5 4Bit GPIO_INT17
1724 * J2 8 4Bit GPIO_INT18
1725 * J3 8 4Bit GPIO_INT19
1726 * J4 4 4Bit GPIO_INT20
1737 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1738 #ifdef CONFIG_CPU_S5PC100
1741 .base = S5PC100_GPA0(0),
1742 .ngpio = S5PC100_GPIO_A0_NR,
1747 .base = S5PC100_GPA1(0),
1748 .ngpio = S5PC100_GPIO_A1_NR,
1753 .base = S5PC100_GPB(0),
1754 .ngpio = S5PC100_GPIO_B_NR,
1759 .base = S5PC100_GPC(0),
1760 .ngpio = S5PC100_GPIO_C_NR,
1765 .base = S5PC100_GPD(0),
1766 .ngpio = S5PC100_GPIO_D_NR,
1771 .base = S5PC100_GPE0(0),
1772 .ngpio = S5PC100_GPIO_E0_NR,
1777 .base = S5PC100_GPE1(0),
1778 .ngpio = S5PC100_GPIO_E1_NR,
1783 .base = S5PC100_GPF0(0),
1784 .ngpio = S5PC100_GPIO_F0_NR,
1789 .base = S5PC100_GPF1(0),
1790 .ngpio = S5PC100_GPIO_F1_NR,
1795 .base = S5PC100_GPF2(0),
1796 .ngpio = S5PC100_GPIO_F2_NR,
1801 .base = S5PC100_GPF3(0),
1802 .ngpio = S5PC100_GPIO_F3_NR,
1807 .base = S5PC100_GPG0(0),
1808 .ngpio = S5PC100_GPIO_G0_NR,
1813 .base = S5PC100_GPG1(0),
1814 .ngpio = S5PC100_GPIO_G1_NR,
1819 .base = S5PC100_GPG2(0),
1820 .ngpio = S5PC100_GPIO_G2_NR,
1825 .base = S5PC100_GPG3(0),
1826 .ngpio = S5PC100_GPIO_G3_NR,
1831 .base = S5PC100_GPI(0),
1832 .ngpio = S5PC100_GPIO_I_NR,
1837 .base = S5PC100_GPJ0(0),
1838 .ngpio = S5PC100_GPIO_J0_NR,
1843 .base = S5PC100_GPJ1(0),
1844 .ngpio = S5PC100_GPIO_J1_NR,
1849 .base = S5PC100_GPJ2(0),
1850 .ngpio = S5PC100_GPIO_J2_NR,
1855 .base = S5PC100_GPJ3(0),
1856 .ngpio = S5PC100_GPIO_J3_NR,
1861 .base = S5PC100_GPJ4(0),
1862 .ngpio = S5PC100_GPIO_J4_NR,
1867 .base = S5PC100_GPK0(0),
1868 .ngpio = S5PC100_GPIO_K0_NR,
1873 .base = S5PC100_GPK1(0),
1874 .ngpio = S5PC100_GPIO_K1_NR,
1879 .base = S5PC100_GPK2(0),
1880 .ngpio = S5PC100_GPIO_K2_NR,
1885 .base = S5PC100_GPK3(0),
1886 .ngpio = S5PC100_GPIO_K3_NR,
1891 .base = S5PC100_GPL0(0),
1892 .ngpio = S5PC100_GPIO_L0_NR,
1897 .base = S5PC100_GPL1(0),
1898 .ngpio = S5PC100_GPIO_L1_NR,
1903 .base = S5PC100_GPL2(0),
1904 .ngpio = S5PC100_GPIO_L2_NR,
1909 .base = S5PC100_GPL3(0),
1910 .ngpio = S5PC100_GPIO_L3_NR,
1915 .base = S5PC100_GPL4(0),
1916 .ngpio = S5PC100_GPIO_L4_NR,
1920 .base = (S5P_VA_GPIO + 0xC00),
1921 .irq_base = IRQ_EINT(0),
1923 .base = S5PC100_GPH0(0),
1924 .ngpio = S5PC100_GPIO_H0_NR,
1926 .to_irq = samsung_gpiolib_to_irq,
1929 .base = (S5P_VA_GPIO + 0xC20),
1930 .irq_base = IRQ_EINT(8),
1932 .base = S5PC100_GPH1(0),
1933 .ngpio = S5PC100_GPIO_H1_NR,
1935 .to_irq = samsung_gpiolib_to_irq,
1938 .base = (S5P_VA_GPIO + 0xC40),
1939 .irq_base = IRQ_EINT(16),
1941 .base = S5PC100_GPH2(0),
1942 .ngpio = S5PC100_GPIO_H2_NR,
1944 .to_irq = samsung_gpiolib_to_irq,
1947 .base = (S5P_VA_GPIO + 0xC60),
1948 .irq_base = IRQ_EINT(24),
1950 .base = S5PC100_GPH3(0),
1951 .ngpio = S5PC100_GPIO_H3_NR,
1953 .to_irq = samsung_gpiolib_to_irq,
1960 * Followings are the gpio banks in S5PV210/S5PC110
1962 * The 'config' member when left to NULL, is initialized to the default
1963 * structure samsung_gpio_cfgs[3] in the init function below.
1965 * The 'base' member is also initialized in the init function below.
1966 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1967 * uses the above macro and depends on the banks being listed in order here.
1970 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1971 #ifdef CONFIG_CPU_S5PV210
1974 .base = S5PV210_GPA0(0),
1975 .ngpio = S5PV210_GPIO_A0_NR,
1980 .base = S5PV210_GPA1(0),
1981 .ngpio = S5PV210_GPIO_A1_NR,
1986 .base = S5PV210_GPB(0),
1987 .ngpio = S5PV210_GPIO_B_NR,
1992 .base = S5PV210_GPC0(0),
1993 .ngpio = S5PV210_GPIO_C0_NR,
1998 .base = S5PV210_GPC1(0),
1999 .ngpio = S5PV210_GPIO_C1_NR,
2004 .base = S5PV210_GPD0(0),
2005 .ngpio = S5PV210_GPIO_D0_NR,
2010 .base = S5PV210_GPD1(0),
2011 .ngpio = S5PV210_GPIO_D1_NR,
2016 .base = S5PV210_GPE0(0),
2017 .ngpio = S5PV210_GPIO_E0_NR,
2022 .base = S5PV210_GPE1(0),
2023 .ngpio = S5PV210_GPIO_E1_NR,
2028 .base = S5PV210_GPF0(0),
2029 .ngpio = S5PV210_GPIO_F0_NR,
2034 .base = S5PV210_GPF1(0),
2035 .ngpio = S5PV210_GPIO_F1_NR,
2040 .base = S5PV210_GPF2(0),
2041 .ngpio = S5PV210_GPIO_F2_NR,
2046 .base = S5PV210_GPF3(0),
2047 .ngpio = S5PV210_GPIO_F3_NR,
2052 .base = S5PV210_GPG0(0),
2053 .ngpio = S5PV210_GPIO_G0_NR,
2058 .base = S5PV210_GPG1(0),
2059 .ngpio = S5PV210_GPIO_G1_NR,
2064 .base = S5PV210_GPG2(0),
2065 .ngpio = S5PV210_GPIO_G2_NR,
2070 .base = S5PV210_GPG3(0),
2071 .ngpio = S5PV210_GPIO_G3_NR,
2076 .base = S5PV210_GPI(0),
2077 .ngpio = S5PV210_GPIO_I_NR,
2082 .base = S5PV210_GPJ0(0),
2083 .ngpio = S5PV210_GPIO_J0_NR,
2088 .base = S5PV210_GPJ1(0),
2089 .ngpio = S5PV210_GPIO_J1_NR,
2094 .base = S5PV210_GPJ2(0),
2095 .ngpio = S5PV210_GPIO_J2_NR,
2100 .base = S5PV210_GPJ3(0),
2101 .ngpio = S5PV210_GPIO_J3_NR,
2106 .base = S5PV210_GPJ4(0),
2107 .ngpio = S5PV210_GPIO_J4_NR,
2112 .base = S5PV210_MP01(0),
2113 .ngpio = S5PV210_GPIO_MP01_NR,
2118 .base = S5PV210_MP02(0),
2119 .ngpio = S5PV210_GPIO_MP02_NR,
2124 .base = S5PV210_MP03(0),
2125 .ngpio = S5PV210_GPIO_MP03_NR,
2130 .base = S5PV210_MP04(0),
2131 .ngpio = S5PV210_GPIO_MP04_NR,
2136 .base = S5PV210_MP05(0),
2137 .ngpio = S5PV210_GPIO_MP05_NR,
2141 .base = (S5P_VA_GPIO + 0xC00),
2142 .irq_base = IRQ_EINT(0),
2144 .base = S5PV210_GPH0(0),
2145 .ngpio = S5PV210_GPIO_H0_NR,
2147 .to_irq = samsung_gpiolib_to_irq,
2150 .base = (S5P_VA_GPIO + 0xC20),
2151 .irq_base = IRQ_EINT(8),
2153 .base = S5PV210_GPH1(0),
2154 .ngpio = S5PV210_GPIO_H1_NR,
2156 .to_irq = samsung_gpiolib_to_irq,
2159 .base = (S5P_VA_GPIO + 0xC40),
2160 .irq_base = IRQ_EINT(16),
2162 .base = S5PV210_GPH2(0),
2163 .ngpio = S5PV210_GPIO_H2_NR,
2165 .to_irq = samsung_gpiolib_to_irq,
2168 .base = (S5P_VA_GPIO + 0xC60),
2169 .irq_base = IRQ_EINT(24),
2171 .base = S5PV210_GPH3(0),
2172 .ngpio = S5PV210_GPIO_H3_NR,
2174 .to_irq = samsung_gpiolib_to_irq,
2181 * Followings are the gpio banks in EXYNOS SoCs
2183 * The 'config' member when left to NULL, is initialized to the default
2184 * structure exynos_gpio_cfg in the init function below.
2186 * The 'base' member is also initialized in the init function below.
2187 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2188 * uses the above macro and depends on the banks being listed in order here.
2191 #ifdef CONFIG_ARCH_EXYNOS4
2192 static struct samsung_gpio_chip exynos4_gpios_1[] = {
2195 .base = EXYNOS4_GPA0(0),
2196 .ngpio = EXYNOS4_GPIO_A0_NR,
2201 .base = EXYNOS4_GPA1(0),
2202 .ngpio = EXYNOS4_GPIO_A1_NR,
2207 .base = EXYNOS4_GPB(0),
2208 .ngpio = EXYNOS4_GPIO_B_NR,
2213 .base = EXYNOS4_GPC0(0),
2214 .ngpio = EXYNOS4_GPIO_C0_NR,
2219 .base = EXYNOS4_GPC1(0),
2220 .ngpio = EXYNOS4_GPIO_C1_NR,
2225 .base = EXYNOS4_GPD0(0),
2226 .ngpio = EXYNOS4_GPIO_D0_NR,
2231 .base = EXYNOS4_GPD1(0),
2232 .ngpio = EXYNOS4_GPIO_D1_NR,
2237 .base = EXYNOS4_GPE0(0),
2238 .ngpio = EXYNOS4_GPIO_E0_NR,
2243 .base = EXYNOS4_GPE1(0),
2244 .ngpio = EXYNOS4_GPIO_E1_NR,
2249 .base = EXYNOS4_GPE2(0),
2250 .ngpio = EXYNOS4_GPIO_E2_NR,
2255 .base = EXYNOS4_GPE3(0),
2256 .ngpio = EXYNOS4_GPIO_E3_NR,
2261 .base = EXYNOS4_GPE4(0),
2262 .ngpio = EXYNOS4_GPIO_E4_NR,
2267 .base = EXYNOS4_GPF0(0),
2268 .ngpio = EXYNOS4_GPIO_F0_NR,
2273 .base = EXYNOS4_GPF1(0),
2274 .ngpio = EXYNOS4_GPIO_F1_NR,
2279 .base = EXYNOS4_GPF2(0),
2280 .ngpio = EXYNOS4_GPIO_F2_NR,
2285 .base = EXYNOS4_GPF3(0),
2286 .ngpio = EXYNOS4_GPIO_F3_NR,
2293 #ifdef CONFIG_ARCH_EXYNOS4
2294 static struct samsung_gpio_chip exynos4_gpios_2[] = {
2297 .base = EXYNOS4_GPJ0(0),
2298 .ngpio = EXYNOS4_GPIO_J0_NR,
2303 .base = EXYNOS4_GPJ1(0),
2304 .ngpio = EXYNOS4_GPIO_J1_NR,
2309 .base = EXYNOS4_GPK0(0),
2310 .ngpio = EXYNOS4_GPIO_K0_NR,
2315 .base = EXYNOS4_GPK1(0),
2316 .ngpio = EXYNOS4_GPIO_K1_NR,
2321 .base = EXYNOS4_GPK2(0),
2322 .ngpio = EXYNOS4_GPIO_K2_NR,
2327 .base = EXYNOS4_GPK3(0),
2328 .ngpio = EXYNOS4_GPIO_K3_NR,
2333 .base = EXYNOS4_GPL0(0),
2334 .ngpio = EXYNOS4_GPIO_L0_NR,
2339 .base = EXYNOS4_GPL1(0),
2340 .ngpio = EXYNOS4_GPIO_L1_NR,
2345 .base = EXYNOS4_GPL2(0),
2346 .ngpio = EXYNOS4_GPIO_L2_NR,
2350 .config = &samsung_gpio_cfgs[8],
2352 .base = EXYNOS4_GPY0(0),
2353 .ngpio = EXYNOS4_GPIO_Y0_NR,
2357 .config = &samsung_gpio_cfgs[8],
2359 .base = EXYNOS4_GPY1(0),
2360 .ngpio = EXYNOS4_GPIO_Y1_NR,
2364 .config = &samsung_gpio_cfgs[8],
2366 .base = EXYNOS4_GPY2(0),
2367 .ngpio = EXYNOS4_GPIO_Y2_NR,
2371 .config = &samsung_gpio_cfgs[8],
2373 .base = EXYNOS4_GPY3(0),
2374 .ngpio = EXYNOS4_GPIO_Y3_NR,
2378 .config = &samsung_gpio_cfgs[8],
2380 .base = EXYNOS4_GPY4(0),
2381 .ngpio = EXYNOS4_GPIO_Y4_NR,
2385 .config = &samsung_gpio_cfgs[8],
2387 .base = EXYNOS4_GPY5(0),
2388 .ngpio = EXYNOS4_GPIO_Y5_NR,
2392 .config = &samsung_gpio_cfgs[8],
2394 .base = EXYNOS4_GPY6(0),
2395 .ngpio = EXYNOS4_GPIO_Y6_NR,
2399 .config = &samsung_gpio_cfgs[9],
2400 .irq_base = IRQ_EINT(0),
2402 .base = EXYNOS4_GPX0(0),
2403 .ngpio = EXYNOS4_GPIO_X0_NR,
2405 .to_irq = samsung_gpiolib_to_irq,
2408 .config = &samsung_gpio_cfgs[9],
2409 .irq_base = IRQ_EINT(8),
2411 .base = EXYNOS4_GPX1(0),
2412 .ngpio = EXYNOS4_GPIO_X1_NR,
2414 .to_irq = samsung_gpiolib_to_irq,
2417 .config = &samsung_gpio_cfgs[9],
2418 .irq_base = IRQ_EINT(16),
2420 .base = EXYNOS4_GPX2(0),
2421 .ngpio = EXYNOS4_GPIO_X2_NR,
2423 .to_irq = samsung_gpiolib_to_irq,
2426 .config = &samsung_gpio_cfgs[9],
2427 .irq_base = IRQ_EINT(24),
2429 .base = EXYNOS4_GPX3(0),
2430 .ngpio = EXYNOS4_GPIO_X3_NR,
2432 .to_irq = samsung_gpiolib_to_irq,
2438 #ifdef CONFIG_ARCH_EXYNOS4
2439 static struct samsung_gpio_chip exynos4_gpios_3[] = {
2442 .base = EXYNOS4_GPZ(0),
2443 .ngpio = EXYNOS4_GPIO_Z_NR,
2450 #ifdef CONFIG_ARCH_EXYNOS5
2451 static struct samsung_gpio_chip exynos5_gpios_1[] = {
2454 .base = EXYNOS5_GPA0(0),
2455 .ngpio = EXYNOS5_GPIO_A0_NR,
2460 .base = EXYNOS5_GPA1(0),
2461 .ngpio = EXYNOS5_GPIO_A1_NR,
2466 .base = EXYNOS5_GPA2(0),
2467 .ngpio = EXYNOS5_GPIO_A2_NR,
2472 .base = EXYNOS5_GPB0(0),
2473 .ngpio = EXYNOS5_GPIO_B0_NR,
2478 .base = EXYNOS5_GPB1(0),
2479 .ngpio = EXYNOS5_GPIO_B1_NR,
2484 .base = EXYNOS5_GPB2(0),
2485 .ngpio = EXYNOS5_GPIO_B2_NR,
2490 .base = EXYNOS5_GPB3(0),
2491 .ngpio = EXYNOS5_GPIO_B3_NR,
2496 .base = EXYNOS5_GPC0(0),
2497 .ngpio = EXYNOS5_GPIO_C0_NR,
2502 .base = EXYNOS5_GPC1(0),
2503 .ngpio = EXYNOS5_GPIO_C1_NR,
2508 .base = EXYNOS5_GPC2(0),
2509 .ngpio = EXYNOS5_GPIO_C2_NR,
2514 .base = EXYNOS5_GPC3(0),
2515 .ngpio = EXYNOS5_GPIO_C3_NR,
2520 .base = EXYNOS5_GPD0(0),
2521 .ngpio = EXYNOS5_GPIO_D0_NR,
2526 .base = EXYNOS5_GPD1(0),
2527 .ngpio = EXYNOS5_GPIO_D1_NR,
2532 .base = EXYNOS5_GPY0(0),
2533 .ngpio = EXYNOS5_GPIO_Y0_NR,
2538 .base = EXYNOS5_GPY1(0),
2539 .ngpio = EXYNOS5_GPIO_Y1_NR,
2544 .base = EXYNOS5_GPY2(0),
2545 .ngpio = EXYNOS5_GPIO_Y2_NR,
2550 .base = EXYNOS5_GPY3(0),
2551 .ngpio = EXYNOS5_GPIO_Y3_NR,
2556 .base = EXYNOS5_GPY4(0),
2557 .ngpio = EXYNOS5_GPIO_Y4_NR,
2562 .base = EXYNOS5_GPY5(0),
2563 .ngpio = EXYNOS5_GPIO_Y5_NR,
2568 .base = EXYNOS5_GPY6(0),
2569 .ngpio = EXYNOS5_GPIO_Y6_NR,
2574 .base = EXYNOS5_GPC4(0),
2575 .ngpio = EXYNOS5_GPIO_C4_NR,
2579 .config = &samsung_gpio_cfgs[9],
2580 .irq_base = IRQ_EINT(0),
2582 .base = EXYNOS5_GPX0(0),
2583 .ngpio = EXYNOS5_GPIO_X0_NR,
2585 .to_irq = samsung_gpiolib_to_irq,
2588 .config = &samsung_gpio_cfgs[9],
2589 .irq_base = IRQ_EINT(8),
2591 .base = EXYNOS5_GPX1(0),
2592 .ngpio = EXYNOS5_GPIO_X1_NR,
2594 .to_irq = samsung_gpiolib_to_irq,
2597 .config = &samsung_gpio_cfgs[9],
2598 .irq_base = IRQ_EINT(16),
2600 .base = EXYNOS5_GPX2(0),
2601 .ngpio = EXYNOS5_GPIO_X2_NR,
2603 .to_irq = samsung_gpiolib_to_irq,
2606 .config = &samsung_gpio_cfgs[9],
2607 .irq_base = IRQ_EINT(24),
2609 .base = EXYNOS5_GPX3(0),
2610 .ngpio = EXYNOS5_GPIO_X3_NR,
2612 .to_irq = samsung_gpiolib_to_irq,
2618 #ifdef CONFIG_ARCH_EXYNOS5
2619 static struct samsung_gpio_chip exynos5_gpios_2[] = {
2622 .base = EXYNOS5_GPE0(0),
2623 .ngpio = EXYNOS5_GPIO_E0_NR,
2628 .base = EXYNOS5_GPE1(0),
2629 .ngpio = EXYNOS5_GPIO_E1_NR,
2634 .base = EXYNOS5_GPF0(0),
2635 .ngpio = EXYNOS5_GPIO_F0_NR,
2640 .base = EXYNOS5_GPF1(0),
2641 .ngpio = EXYNOS5_GPIO_F1_NR,
2646 .base = EXYNOS5_GPG0(0),
2647 .ngpio = EXYNOS5_GPIO_G0_NR,
2652 .base = EXYNOS5_GPG1(0),
2653 .ngpio = EXYNOS5_GPIO_G1_NR,
2658 .base = EXYNOS5_GPG2(0),
2659 .ngpio = EXYNOS5_GPIO_G2_NR,
2664 .base = EXYNOS5_GPH0(0),
2665 .ngpio = EXYNOS5_GPIO_H0_NR,
2670 .base = EXYNOS5_GPH1(0),
2671 .ngpio = EXYNOS5_GPIO_H1_NR,
2679 #ifdef CONFIG_ARCH_EXYNOS5
2680 static struct samsung_gpio_chip exynos5_gpios_3[] = {
2683 .base = EXYNOS5_GPV0(0),
2684 .ngpio = EXYNOS5_GPIO_V0_NR,
2689 .base = EXYNOS5_GPV1(0),
2690 .ngpio = EXYNOS5_GPIO_V1_NR,
2695 .base = EXYNOS5_GPV2(0),
2696 .ngpio = EXYNOS5_GPIO_V2_NR,
2701 .base = EXYNOS5_GPV3(0),
2702 .ngpio = EXYNOS5_GPIO_V3_NR,
2707 .base = EXYNOS5_GPV4(0),
2708 .ngpio = EXYNOS5_GPIO_V4_NR,
2715 #ifdef CONFIG_ARCH_EXYNOS5
2716 static struct samsung_gpio_chip exynos5_gpios_4[] = {
2719 .base = EXYNOS5_GPZ(0),
2720 .ngpio = EXYNOS5_GPIO_Z_NR,
2728 #if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2729 static int exynos_gpio_xlate(struct gpio_chip *gc,
2730 const struct of_phandle_args *gpiospec, u32 *flags)
2734 if (WARN_ON(gc->of_gpio_n_cells < 4))
2737 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
2740 if (gpiospec->args[0] > gc->ngpio)
2743 pin = gc->base + gpiospec->args[0];
2745 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
2746 pr_warn("gpio_xlate: failed to set pin function\n");
2747 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
2748 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
2749 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
2750 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2753 *flags = gpiospec->args[2] >> 16;
2755 return gpiospec->args[0];
2758 static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2759 { .compatible = "samsung,exynos4-gpio", },
2763 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2764 u64 base, u64 offset)
2766 struct gpio_chip *gc = &chip->chip;
2769 if (!of_have_populated_dt())
2772 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2773 gc->of_node = of_find_matching_node_by_address(NULL,
2774 exynos_gpio_dt_match, address);
2776 pr_info("gpio: device tree node not found for gpio controller"
2777 " with base address %08llx\n", address);
2780 gc->of_gpio_n_cells = 4;
2781 gc->of_xlate = exynos_gpio_xlate;
2783 #elif defined(CONFIG_ARCH_EXYNOS)
2784 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2785 u64 base, u64 offset)
2789 #endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2791 static __init void exynos4_gpiolib_init(void)
2793 #ifdef CONFIG_CPU_EXYNOS4210
2794 struct samsung_gpio_chip *chip;
2796 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2798 void __iomem *gpx_base;
2801 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2802 if (gpio_base1 == NULL) {
2803 pr_err("unable to ioremap for gpio_base1\n");
2807 chip = exynos4_gpios_1;
2808 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2810 for (i = 0; i < nr_chips; i++, chip++) {
2811 if (!chip->config) {
2812 chip->config = &exynos_gpio_cfg;
2813 chip->group = group++;
2815 exynos_gpiolib_attach_ofnode(chip,
2816 EXYNOS4_PA_GPIO1, i * 0x20);
2818 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2819 nr_chips, gpio_base1);
2822 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2823 if (gpio_base2 == NULL) {
2824 pr_err("unable to ioremap for gpio_base2\n");
2828 /* need to set base address for gpx */
2829 chip = &exynos4_gpios_2[16];
2830 gpx_base = gpio_base2 + 0xC00;
2831 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2832 chip->base = gpx_base;
2834 chip = exynos4_gpios_2;
2835 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2837 for (i = 0; i < nr_chips; i++, chip++) {
2838 if (!chip->config) {
2839 chip->config = &exynos_gpio_cfg;
2840 chip->group = group++;
2842 exynos_gpiolib_attach_ofnode(chip,
2843 EXYNOS4_PA_GPIO2, i * 0x20);
2845 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2846 nr_chips, gpio_base2);
2849 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2850 if (gpio_base3 == NULL) {
2851 pr_err("unable to ioremap for gpio_base3\n");
2855 chip = exynos4_gpios_3;
2856 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2858 for (i = 0; i < nr_chips; i++, chip++) {
2859 if (!chip->config) {
2860 chip->config = &exynos_gpio_cfg;
2861 chip->group = group++;
2863 exynos_gpiolib_attach_ofnode(chip,
2864 EXYNOS4_PA_GPIO3, i * 0x20);
2866 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2867 nr_chips, gpio_base3);
2869 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2870 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2871 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2877 iounmap(gpio_base2);
2879 iounmap(gpio_base1);
2882 #endif /* CONFIG_CPU_EXYNOS4210 */
2885 static __init void exynos5_gpiolib_init(void)
2887 #ifdef CONFIG_SOC_EXYNOS5250
2888 struct samsung_gpio_chip *chip;
2890 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2892 void __iomem *gpx_base;
2895 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2896 if (gpio_base1 == NULL) {
2897 pr_err("unable to ioremap for gpio_base1\n");
2901 /* need to set base address for gpc4 */
2902 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
2904 /* need to set base address for gpx */
2905 chip = &exynos5_gpios_1[21];
2906 gpx_base = gpio_base1 + 0xC00;
2907 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2908 chip->base = gpx_base;
2910 chip = exynos5_gpios_1;
2911 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2913 for (i = 0; i < nr_chips; i++, chip++) {
2914 if (!chip->config) {
2915 chip->config = &exynos_gpio_cfg;
2916 chip->group = group++;
2918 exynos_gpiolib_attach_ofnode(chip,
2919 EXYNOS5_PA_GPIO1, i * 0x20);
2921 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2922 nr_chips, gpio_base1);
2925 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2926 if (gpio_base2 == NULL) {
2927 pr_err("unable to ioremap for gpio_base2\n");
2931 chip = exynos5_gpios_2;
2932 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2934 for (i = 0; i < nr_chips; i++, chip++) {
2935 if (!chip->config) {
2936 chip->config = &exynos_gpio_cfg;
2937 chip->group = group++;
2939 exynos_gpiolib_attach_ofnode(chip,
2940 EXYNOS5_PA_GPIO2, i * 0x20);
2942 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2943 nr_chips, gpio_base2);
2946 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2947 if (gpio_base3 == NULL) {
2948 pr_err("unable to ioremap for gpio_base3\n");
2952 /* need to set base address for gpv */
2953 exynos5_gpios_3[0].base = gpio_base3;
2954 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2955 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2956 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2957 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2959 chip = exynos5_gpios_3;
2960 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2962 for (i = 0; i < nr_chips; i++, chip++) {
2963 if (!chip->config) {
2964 chip->config = &exynos_gpio_cfg;
2965 chip->group = group++;
2967 exynos_gpiolib_attach_ofnode(chip,
2968 EXYNOS5_PA_GPIO3, i * 0x20);
2970 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2971 nr_chips, gpio_base3);
2974 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2975 if (gpio_base4 == NULL) {
2976 pr_err("unable to ioremap for gpio_base4\n");
2980 chip = exynos5_gpios_4;
2981 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2983 for (i = 0; i < nr_chips; i++, chip++) {
2984 if (!chip->config) {
2985 chip->config = &exynos_gpio_cfg;
2986 chip->group = group++;
2988 exynos_gpiolib_attach_ofnode(chip,
2989 EXYNOS5_PA_GPIO4, i * 0x20);
2991 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2992 nr_chips, gpio_base4);
2996 iounmap(gpio_base3);
2998 iounmap(gpio_base2);
3000 iounmap(gpio_base1);
3004 #endif /* CONFIG_SOC_EXYNOS5250 */
3007 /* TODO: cleanup soc_is_* */
3008 static __init int samsung_gpiolib_init(void)
3010 struct samsung_gpio_chip *chip;
3014 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
3016 if (soc_is_s3c24xx()) {
3017 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
3018 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
3019 } else if (soc_is_s3c64xx()) {
3020 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
3021 ARRAY_SIZE(s3c64xx_gpios_2bit),
3022 S3C64XX_VA_GPIO + 0xE0, 0x20);
3023 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
3024 ARRAY_SIZE(s3c64xx_gpios_4bit),
3026 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
3027 ARRAY_SIZE(s3c64xx_gpios_4bit2));
3028 } else if (soc_is_s5p6440()) {
3029 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
3030 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
3031 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
3032 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
3033 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
3034 ARRAY_SIZE(s5p6440_gpios_4bit2));
3035 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
3036 ARRAY_SIZE(s5p6440_gpios_rbank));
3037 } else if (soc_is_s5p6450()) {
3038 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
3039 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
3040 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
3041 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
3042 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
3043 ARRAY_SIZE(s5p6450_gpios_4bit2));
3044 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
3045 ARRAY_SIZE(s5p6450_gpios_rbank));
3046 } else if (soc_is_s5pc100()) {
3048 chip = s5pc100_gpios_4bit;
3049 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
3051 for (i = 0; i < nr_chips; i++, chip++) {
3052 if (!chip->config) {
3053 chip->config = &samsung_gpio_cfgs[3];
3054 chip->group = group++;
3057 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
3058 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
3059 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3061 } else if (soc_is_s5pv210()) {
3063 chip = s5pv210_gpios_4bit;
3064 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
3066 for (i = 0; i < nr_chips; i++, chip++) {
3067 if (!chip->config) {
3068 chip->config = &samsung_gpio_cfgs[3];
3069 chip->group = group++;
3072 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
3073 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
3074 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3076 } else if (soc_is_exynos4210()) {
3077 exynos4_gpiolib_init();
3078 } else if (soc_is_exynos5250()) {
3079 exynos5_gpiolib_init();
3081 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3087 core_initcall(samsung_gpiolib_init);
3089 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
3091 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3092 unsigned long flags;
3099 offset = pin - chip->chip.base;
3101 samsung_gpio_lock(chip, flags);
3102 ret = samsung_gpio_do_setcfg(chip, offset, config);
3103 samsung_gpio_unlock(chip, flags);
3107 EXPORT_SYMBOL(s3c_gpio_cfgpin);
3109 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3114 for (; nr > 0; nr--, start++) {
3115 ret = s3c_gpio_cfgpin(start, cfg);
3122 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3124 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3125 unsigned int cfg, samsung_gpio_pull_t pull)
3129 for (; nr > 0; nr--, start++) {
3130 s3c_gpio_setpull(start, pull);
3131 ret = s3c_gpio_cfgpin(start, cfg);
3138 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3140 unsigned s3c_gpio_getcfg(unsigned int pin)
3142 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3143 unsigned long flags;
3148 offset = pin - chip->chip.base;
3150 samsung_gpio_lock(chip, flags);
3151 ret = samsung_gpio_do_getcfg(chip, offset);
3152 samsung_gpio_unlock(chip, flags);
3157 EXPORT_SYMBOL(s3c_gpio_getcfg);
3159 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3161 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3162 unsigned long flags;
3168 offset = pin - chip->chip.base;
3170 samsung_gpio_lock(chip, flags);
3171 ret = samsung_gpio_do_setpull(chip, offset, pull);
3172 samsung_gpio_unlock(chip, flags);
3176 EXPORT_SYMBOL(s3c_gpio_setpull);
3178 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3180 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3181 unsigned long flags;
3186 offset = pin - chip->chip.base;
3188 samsung_gpio_lock(chip, flags);
3189 pup = samsung_gpio_do_getpull(chip, offset);
3190 samsung_gpio_unlock(chip, flags);
3193 return (__force samsung_gpio_pull_t)pup;
3195 EXPORT_SYMBOL(s3c_gpio_getpull);
3197 #ifdef CONFIG_S5P_GPIO_DRVSTR
3198 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3200 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3209 off = pin - chip->chip.base;
3211 reg = chip->base + 0x0C;
3213 drvstr = __raw_readl(reg);
3214 drvstr = drvstr >> shift;
3217 return (__force s5p_gpio_drvstr_t)drvstr;
3219 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3221 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3223 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3232 off = pin - chip->chip.base;
3234 reg = chip->base + 0x0C;
3236 tmp = __raw_readl(reg);
3237 tmp &= ~(0x3 << shift);
3238 tmp |= drvstr << shift;
3240 __raw_writel(tmp, reg);
3244 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3245 #endif /* CONFIG_S5P_GPIO_DRVSTR */
3247 #ifdef CONFIG_PLAT_S3C24XX
3248 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3250 unsigned long flags;
3251 unsigned long misccr;
3253 local_irq_save(flags);
3254 misccr = __raw_readl(S3C24XX_MISCCR);
3257 __raw_writel(misccr, S3C24XX_MISCCR);
3258 local_irq_restore(flags);
3262 EXPORT_SYMBOL(s3c2410_modify_misccr);