2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
33 #include <mach/hardware.h>
35 #include <mach/regs-gpio.h>
38 #include <plat/gpio-core.h>
39 #include <plat/gpio-cfg.h>
40 #include <plat/gpio-cfg-helpers.h>
43 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
44 unsigned int off, samsung_gpio_pull_t pull)
46 void __iomem *reg = chip->base + 0x08;
50 pup = __raw_readl(reg);
53 __raw_writel(pup, reg);
58 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
61 void __iomem *reg = chip->base + 0x08;
63 u32 pup = __raw_readl(reg);
68 return (__force samsung_gpio_pull_t)pup;
71 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
72 unsigned int off, samsung_gpio_pull_t pull)
75 case S3C_GPIO_PULL_NONE:
78 case S3C_GPIO_PULL_UP:
81 case S3C_GPIO_PULL_DOWN:
85 return samsung_gpio_setpull_updown(chip, off, pull);
88 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
91 samsung_gpio_pull_t pull;
93 pull = samsung_gpio_getpull_updown(chip, off);
97 pull = S3C_GPIO_PULL_UP;
101 pull = S3C_GPIO_PULL_NONE;
104 pull = S3C_GPIO_PULL_DOWN;
111 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
112 unsigned int off, samsung_gpio_pull_t pull,
113 samsung_gpio_pull_t updown)
115 void __iomem *reg = chip->base + 0x08;
116 u32 pup = __raw_readl(reg);
120 else if (pull == S3C_GPIO_PULL_NONE)
125 __raw_writel(pup, reg);
129 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
131 samsung_gpio_pull_t updown)
133 void __iomem *reg = chip->base + 0x08;
134 u32 pup = __raw_readl(reg);
137 return pup ? S3C_GPIO_PULL_NONE : updown;
140 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
143 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
146 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
147 unsigned int off, samsung_gpio_pull_t pull)
149 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
152 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
155 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
158 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
159 unsigned int off, samsung_gpio_pull_t pull)
161 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
164 static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
165 unsigned int off, samsung_gpio_pull_t pull)
167 if (pull == S3C_GPIO_PULL_UP)
170 return samsung_gpio_setpull_updown(chip, off, pull);
173 static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
176 samsung_gpio_pull_t pull;
178 pull = samsung_gpio_getpull_updown(chip, off);
181 pull = S3C_GPIO_PULL_UP;
187 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
188 * @chip: The gpio chip that is being configured.
189 * @off: The offset for the GPIO being configured.
190 * @cfg: The configuration value to set.
192 * This helper deal with the GPIO cases where the control register
193 * has two bits of configuration per gpio, which have the following
197 * 1x = special function
200 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
201 unsigned int off, unsigned int cfg)
203 void __iomem *reg = chip->base;
204 unsigned int shift = off * 2;
207 if (samsung_gpio_is_cfg_special(cfg)) {
215 con = __raw_readl(reg);
216 con &= ~(0x3 << shift);
218 __raw_writel(con, reg);
224 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
225 * @chip: The gpio chip that is being configured.
226 * @off: The offset for the GPIO being configured.
228 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
229 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
230 * S3C_GPIO_SPECIAL() macro.
233 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
238 con = __raw_readl(chip->base);
242 /* this conversion works for IN and OUT as well as special mode */
243 return S3C_GPIO_SPECIAL(con);
247 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
248 * @chip: The gpio chip that is being configured.
249 * @off: The offset for the GPIO being configured.
250 * @cfg: The configuration value to set.
252 * This helper deal with the GPIO cases where the control register has 4 bits
253 * of control per GPIO, generally in the form of:
256 * others = Special functions (dependent on bank)
258 * Note, since the code to deal with the case where there are two control
259 * registers instead of one, we do not have a separate set of functions for
263 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
264 unsigned int off, unsigned int cfg)
266 void __iomem *reg = chip->base;
267 unsigned int shift = (off & 7) * 4;
270 if (off < 8 && chip->chip.ngpio > 8)
273 if (samsung_gpio_is_cfg_special(cfg)) {
278 con = __raw_readl(reg);
279 con &= ~(0xf << shift);
281 __raw_writel(con, reg);
287 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
288 * @chip: The gpio chip that is being configured.
289 * @off: The offset for the GPIO being configured.
291 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
292 * register setting into a value the software can use, such as could be passed
293 * to samsung_gpio_setcfg_4bit().
295 * @sa samsung_gpio_getcfg_2bit
298 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
301 void __iomem *reg = chip->base;
302 unsigned int shift = (off & 7) * 4;
305 if (off < 8 && chip->chip.ngpio > 8)
308 con = __raw_readl(reg);
312 /* this conversion works for IN and OUT as well as special mode */
313 return S3C_GPIO_SPECIAL(con);
316 #ifdef CONFIG_PLAT_S3C24XX
318 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
319 * @chip: The gpio chip that is being configured.
320 * @off: The offset for the GPIO being configured.
321 * @cfg: The configuration value to set.
323 * This helper deal with the GPIO cases where the control register
324 * has one bit of configuration for the gpio, where setting the bit
325 * means the pin is in special function mode and unset means output.
328 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
329 unsigned int off, unsigned int cfg)
331 void __iomem *reg = chip->base;
332 unsigned int shift = off;
335 if (samsung_gpio_is_cfg_special(cfg)) {
338 /* Map output to 0, and SFN2 to 1 */
346 con = __raw_readl(reg);
347 con &= ~(0x1 << shift);
349 __raw_writel(con, reg);
355 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
356 * @chip: The gpio chip that is being configured.
357 * @off: The offset for the GPIO being configured.
359 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
360 * GPIO configuration value.
362 * @sa samsung_gpio_getcfg_2bit
363 * @sa samsung_gpio_getcfg_4bit
366 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
371 con = __raw_readl(chip->base);
376 return S3C_GPIO_SFN(con);
380 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
381 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
382 unsigned int off, unsigned int cfg)
384 void __iomem *reg = chip->base;
395 shift = (off & 7) * 4;
399 shift = ((off + 1) & 7) * 4;
402 shift = ((off + 1) & 7) * 4;
406 if (samsung_gpio_is_cfg_special(cfg)) {
411 con = __raw_readl(reg);
412 con &= ~(0xf << shift);
414 __raw_writel(con, reg);
420 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
423 for (; nr_chips > 0; nr_chips--, chipcfg++) {
424 if (!chipcfg->set_config)
425 chipcfg->set_config = samsung_gpio_setcfg_4bit;
426 if (!chipcfg->get_config)
427 chipcfg->get_config = samsung_gpio_getcfg_4bit;
428 if (!chipcfg->set_pull)
429 chipcfg->set_pull = samsung_gpio_setpull_updown;
430 if (!chipcfg->get_pull)
431 chipcfg->get_pull = samsung_gpio_getpull_updown;
435 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
436 .set_config = samsung_gpio_setcfg_2bit,
437 .get_config = samsung_gpio_getcfg_2bit,
440 #ifdef CONFIG_PLAT_S3C24XX
441 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
442 .set_config = s3c24xx_gpio_setcfg_abank,
443 .get_config = s3c24xx_gpio_getcfg_abank,
447 #if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_SOC_EXYNOS5250)
448 static struct samsung_gpio_cfg exynos_gpio_cfg = {
449 .set_pull = exynos_gpio_setpull,
450 .get_pull = exynos_gpio_getpull,
451 .set_config = samsung_gpio_setcfg_4bit,
452 .get_config = samsung_gpio_getcfg_4bit,
456 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
457 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
459 .set_config = s5p64x0_gpio_setcfg_rbank,
460 .get_config = samsung_gpio_getcfg_4bit,
461 .set_pull = samsung_gpio_setpull_updown,
462 .get_pull = samsung_gpio_getpull_updown,
466 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
481 .set_config = samsung_gpio_setcfg_2bit,
482 .get_config = samsung_gpio_getcfg_2bit,
486 .set_config = samsung_gpio_setcfg_2bit,
487 .get_config = samsung_gpio_getcfg_2bit,
491 .set_config = samsung_gpio_setcfg_2bit,
492 .get_config = samsung_gpio_getcfg_2bit,
495 .set_config = samsung_gpio_setcfg_2bit,
496 .get_config = samsung_gpio_getcfg_2bit,
499 .set_pull = exynos_gpio_setpull,
500 .get_pull = exynos_gpio_getpull,
504 .set_pull = exynos_gpio_setpull,
505 .get_pull = exynos_gpio_getpull,
510 * Default routines for controlling GPIO, based on the original S3C24XX
511 * GPIO functions which deal with the case where each gpio bank of the
512 * chip is as following:
514 * base + 0x00: Control register, 2 bits per gpio
515 * gpio n: 2 bits starting at (2*n)
516 * 00 = input, 01 = output, others mean special-function
517 * base + 0x04: Data register, 1 bit per gpio
521 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
523 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
524 void __iomem *base = ourchip->base;
528 samsung_gpio_lock(ourchip, flags);
530 con = __raw_readl(base + 0x00);
531 con &= ~(3 << (offset * 2));
533 __raw_writel(con, base + 0x00);
535 samsung_gpio_unlock(ourchip, flags);
539 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
540 unsigned offset, int value)
542 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
543 void __iomem *base = ourchip->base;
548 samsung_gpio_lock(ourchip, flags);
550 dat = __raw_readl(base + 0x04);
551 dat &= ~(1 << offset);
554 __raw_writel(dat, base + 0x04);
556 con = __raw_readl(base + 0x00);
557 con &= ~(3 << (offset * 2));
558 con |= 1 << (offset * 2);
560 __raw_writel(con, base + 0x00);
561 __raw_writel(dat, base + 0x04);
563 samsung_gpio_unlock(ourchip, flags);
568 * The samsung_gpiolib_4bit routines are to control the gpio banks where
569 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
572 * base + 0x00: Control register, 4 bits per gpio
573 * gpio n: 4 bits starting at (4*n)
574 * 0000 = input, 0001 = output, others mean special-function
575 * base + 0x04: Data register, 1 bit per gpio
578 * Note, since the data register is one bit per gpio and is at base + 0x4
579 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
580 * state of the output.
583 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
586 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
587 void __iomem *base = ourchip->base;
590 con = __raw_readl(base + GPIOCON_OFF);
591 if (ourchip->bitmap_gpio_int & BIT(offset))
592 con |= 0xf << con_4bit_shift(offset);
594 con &= ~(0xf << con_4bit_shift(offset));
595 __raw_writel(con, base + GPIOCON_OFF);
597 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
602 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
603 unsigned int offset, int value)
605 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
606 void __iomem *base = ourchip->base;
610 con = __raw_readl(base + GPIOCON_OFF);
611 con &= ~(0xf << con_4bit_shift(offset));
612 con |= 0x1 << con_4bit_shift(offset);
614 dat = __raw_readl(base + GPIODAT_OFF);
619 dat &= ~(1 << offset);
621 __raw_writel(dat, base + GPIODAT_OFF);
622 __raw_writel(con, base + GPIOCON_OFF);
623 __raw_writel(dat, base + GPIODAT_OFF);
625 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
631 * The next set of routines are for the case where the GPIO configuration
632 * registers are 4 bits per GPIO but there is more than one register (the
633 * bank has more than 8 GPIOs.
635 * This case is the similar to the 4 bit case, but the registers are as
638 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
639 * gpio n: 4 bits starting at (4*n)
640 * 0000 = input, 0001 = output, others mean special-function
641 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
642 * gpio n: 4 bits starting at (4*n)
643 * 0000 = input, 0001 = output, others mean special-function
644 * base + 0x08: Data register, 1 bit per gpio
647 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
648 * routines we store the 'base + 0x4' address so that these routines see
649 * the data register at ourchip->base + 0x04.
652 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
655 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
656 void __iomem *base = ourchip->base;
657 void __iomem *regcon = base;
665 con = __raw_readl(regcon);
666 con &= ~(0xf << con_4bit_shift(offset));
667 __raw_writel(con, regcon);
669 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
674 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
675 unsigned int offset, int value)
677 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
678 void __iomem *base = ourchip->base;
679 void __iomem *regcon = base;
682 unsigned con_offset = offset;
689 con = __raw_readl(regcon);
690 con &= ~(0xf << con_4bit_shift(con_offset));
691 con |= 0x1 << con_4bit_shift(con_offset);
693 dat = __raw_readl(base + GPIODAT_OFF);
698 dat &= ~(1 << offset);
700 __raw_writel(dat, base + GPIODAT_OFF);
701 __raw_writel(con, regcon);
702 __raw_writel(dat, base + GPIODAT_OFF);
704 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
709 #ifdef CONFIG_PLAT_S3C24XX
710 /* The next set of routines are for the case of s3c24xx bank a */
712 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
717 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
718 unsigned offset, int value)
720 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
721 void __iomem *base = ourchip->base;
726 local_irq_save(flags);
728 con = __raw_readl(base + 0x00);
729 dat = __raw_readl(base + 0x04);
731 dat &= ~(1 << offset);
735 __raw_writel(dat, base + 0x04);
737 con &= ~(1 << offset);
739 __raw_writel(con, base + 0x00);
740 __raw_writel(dat, base + 0x04);
742 local_irq_restore(flags);
747 /* The next set of routines are for the case of s5p64x0 bank r */
749 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
752 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
753 void __iomem *base = ourchip->base;
754 void __iomem *regcon = base;
774 samsung_gpio_lock(ourchip, flags);
776 con = __raw_readl(regcon);
777 con &= ~(0xf << con_4bit_shift(offset));
778 __raw_writel(con, regcon);
780 samsung_gpio_unlock(ourchip, flags);
785 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
786 unsigned int offset, int value)
788 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
789 void __iomem *base = ourchip->base;
790 void __iomem *regcon = base;
794 unsigned con_offset = offset;
796 switch (con_offset) {
812 samsung_gpio_lock(ourchip, flags);
814 con = __raw_readl(regcon);
815 con &= ~(0xf << con_4bit_shift(con_offset));
816 con |= 0x1 << con_4bit_shift(con_offset);
818 dat = __raw_readl(base + GPIODAT_OFF);
822 dat &= ~(1 << offset);
824 __raw_writel(con, regcon);
825 __raw_writel(dat, base + GPIODAT_OFF);
827 samsung_gpio_unlock(ourchip, flags);
832 static void samsung_gpiolib_set(struct gpio_chip *chip,
833 unsigned offset, int value)
835 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
836 void __iomem *base = ourchip->base;
840 samsung_gpio_lock(ourchip, flags);
842 dat = __raw_readl(base + 0x04);
843 dat &= ~(1 << offset);
846 __raw_writel(dat, base + 0x04);
848 samsung_gpio_unlock(ourchip, flags);
851 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
853 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
856 val = __raw_readl(ourchip->base + 0x04);
864 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
865 * for use with the configuration calls, and other parts of the s3c gpiolib
868 * Not all s3c support code will need this, as some configurations of cpu
869 * may only support one or two different configuration options and have an
870 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
871 * the machine support file should provide its own samsung_gpiolib_getchip()
872 * and any other necessary functions.
875 #ifdef CONFIG_S3C_GPIO_TRACK
876 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
878 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
883 gpn = chip->chip.base;
884 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
885 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
886 s3c_gpios[gpn] = chip;
889 #endif /* CONFIG_S3C_GPIO_TRACK */
892 * samsung_gpiolib_add() - add the Samsung gpio_chip.
893 * @chip: The chip to register
895 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
896 * information and makes the necessary alterations for the platform and
897 * notes the information for use with the configuration systems and any
898 * other parts of the system.
901 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
903 struct gpio_chip *gc = &chip->chip;
910 spin_lock_init(&chip->lock);
912 if (!gc->direction_input)
913 gc->direction_input = samsung_gpiolib_2bit_input;
914 if (!gc->direction_output)
915 gc->direction_output = samsung_gpiolib_2bit_output;
917 gc->set = samsung_gpiolib_set;
919 gc->get = samsung_gpiolib_get;
922 if (chip->pm != NULL) {
923 if (!chip->pm->save || !chip->pm->resume)
924 pr_err("gpio: %s has missing PM functions\n",
927 pr_err("gpio: %s has no PM function\n", gc->label);
930 /* gpiochip_add() prints own failure message on error. */
931 ret = gpiochip_add(gc);
933 s3c_gpiolib_track(chip);
936 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
937 int nr_chips, void __iomem *base)
940 struct gpio_chip *gc = &chip->chip;
942 for (i = 0 ; i < nr_chips; i++, chip++) {
943 /* skip banks not present on SoC */
944 if (chip->chip.base >= S3C_GPIO_END)
948 chip->config = &s3c24xx_gpiocfg_default;
950 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
951 if ((base != NULL) && (chip->base == NULL))
952 chip->base = base + ((i) * 0x10);
954 if (!gc->direction_input)
955 gc->direction_input = samsung_gpiolib_2bit_input;
956 if (!gc->direction_output)
957 gc->direction_output = samsung_gpiolib_2bit_output;
959 samsung_gpiolib_add(chip);
963 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
964 int nr_chips, void __iomem *base,
969 for (i = 0 ; i < nr_chips; i++, chip++) {
970 chip->chip.direction_input = samsung_gpiolib_2bit_input;
971 chip->chip.direction_output = samsung_gpiolib_2bit_output;
974 chip->config = &samsung_gpio_cfgs[7];
976 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
977 if ((base != NULL) && (chip->base == NULL))
978 chip->base = base + ((i) * offset);
980 samsung_gpiolib_add(chip);
985 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
986 * @chip: The gpio chip that is being configured.
987 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
989 * This helper deal with the GPIO cases where the control register has 4 bits
990 * of control per GPIO, generally in the form of:
993 * others = Special functions (dependent on bank)
995 * Note, since the code to deal with the case where there are two control
996 * registers instead of one, we do not have a separate set of function
997 * (samsung_gpiolib_add_4bit2_chips)for each case.
1000 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1001 int nr_chips, void __iomem *base)
1005 for (i = 0 ; i < nr_chips; i++, chip++) {
1006 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1007 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1010 chip->config = &samsung_gpio_cfgs[2];
1012 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1013 if ((base != NULL) && (chip->base == NULL))
1014 chip->base = base + ((i) * 0x20);
1016 chip->bitmap_gpio_int = 0;
1018 samsung_gpiolib_add(chip);
1022 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1025 for (; nr_chips > 0; nr_chips--, chip++) {
1026 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1027 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1030 chip->config = &samsung_gpio_cfgs[2];
1032 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1034 samsung_gpiolib_add(chip);
1038 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1041 for (; nr_chips > 0; nr_chips--, chip++) {
1042 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1043 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1046 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1048 samsung_gpiolib_add(chip);
1052 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1054 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1056 return samsung_chip->irq_base + offset;
1059 #ifdef CONFIG_PLAT_S3C24XX
1060 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1063 if (soc_is_s3c2412())
1064 return IRQ_EINT0_2412 + offset;
1066 return IRQ_EINT0 + offset;
1070 return IRQ_EINT4 + offset - 4;
1076 #ifdef CONFIG_PLAT_S3C64XX
1077 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1079 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1082 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1084 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1088 struct samsung_gpio_chip s3c24xx_gpios[] = {
1089 #ifdef CONFIG_PLAT_S3C24XX
1091 .config = &s3c24xx_gpiocfg_banka,
1093 .base = S3C2410_GPA(0),
1094 .owner = THIS_MODULE,
1097 .direction_input = s3c24xx_gpiolib_banka_input,
1098 .direction_output = s3c24xx_gpiolib_banka_output,
1102 .base = S3C2410_GPB(0),
1103 .owner = THIS_MODULE,
1109 .base = S3C2410_GPC(0),
1110 .owner = THIS_MODULE,
1116 .base = S3C2410_GPD(0),
1117 .owner = THIS_MODULE,
1123 .base = S3C2410_GPE(0),
1125 .owner = THIS_MODULE,
1130 .base = S3C2410_GPF(0),
1131 .owner = THIS_MODULE,
1134 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1137 .irq_base = IRQ_EINT8,
1139 .base = S3C2410_GPG(0),
1140 .owner = THIS_MODULE,
1143 .to_irq = samsung_gpiolib_to_irq,
1147 .base = S3C2410_GPH(0),
1148 .owner = THIS_MODULE,
1153 /* GPIOS for the S3C2443 and later devices. */
1155 .base = S3C2440_GPJCON,
1157 .base = S3C2410_GPJ(0),
1158 .owner = THIS_MODULE,
1163 .base = S3C2443_GPKCON,
1165 .base = S3C2410_GPK(0),
1166 .owner = THIS_MODULE,
1171 .base = S3C2443_GPLCON,
1173 .base = S3C2410_GPL(0),
1174 .owner = THIS_MODULE,
1179 .base = S3C2443_GPMCON,
1181 .base = S3C2410_GPM(0),
1182 .owner = THIS_MODULE,
1191 * GPIO bank summary:
1193 * Bank GPIOs Style SlpCon ExtInt Group
1199 * F 16 2Bit Yes 4 [1]
1201 * H 10 4Bit[2] Yes 6
1202 * I 16 2Bit Yes None
1203 * J 12 2Bit Yes None
1204 * K 16 4Bit[2] No None
1205 * L 15 4Bit[2] No None
1206 * M 6 4Bit No IRQ_EINT
1207 * N 16 2Bit No IRQ_EINT
1212 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1213 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1216 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1217 #ifdef CONFIG_PLAT_S3C64XX
1220 .base = S3C64XX_GPA(0),
1221 .ngpio = S3C64XX_GPIO_A_NR,
1226 .base = S3C64XX_GPB(0),
1227 .ngpio = S3C64XX_GPIO_B_NR,
1232 .base = S3C64XX_GPC(0),
1233 .ngpio = S3C64XX_GPIO_C_NR,
1238 .base = S3C64XX_GPD(0),
1239 .ngpio = S3C64XX_GPIO_D_NR,
1243 .config = &samsung_gpio_cfgs[0],
1245 .base = S3C64XX_GPE(0),
1246 .ngpio = S3C64XX_GPIO_E_NR,
1250 .base = S3C64XX_GPG_BASE,
1252 .base = S3C64XX_GPG(0),
1253 .ngpio = S3C64XX_GPIO_G_NR,
1257 .base = S3C64XX_GPM_BASE,
1258 .config = &samsung_gpio_cfgs[1],
1260 .base = S3C64XX_GPM(0),
1261 .ngpio = S3C64XX_GPIO_M_NR,
1263 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1269 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1270 #ifdef CONFIG_PLAT_S3C64XX
1272 .base = S3C64XX_GPH_BASE + 0x4,
1274 .base = S3C64XX_GPH(0),
1275 .ngpio = S3C64XX_GPIO_H_NR,
1279 .base = S3C64XX_GPK_BASE + 0x4,
1280 .config = &samsung_gpio_cfgs[0],
1282 .base = S3C64XX_GPK(0),
1283 .ngpio = S3C64XX_GPIO_K_NR,
1287 .base = S3C64XX_GPL_BASE + 0x4,
1288 .config = &samsung_gpio_cfgs[1],
1290 .base = S3C64XX_GPL(0),
1291 .ngpio = S3C64XX_GPIO_L_NR,
1293 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1299 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1300 #ifdef CONFIG_PLAT_S3C64XX
1302 .base = S3C64XX_GPF_BASE,
1303 .config = &samsung_gpio_cfgs[6],
1305 .base = S3C64XX_GPF(0),
1306 .ngpio = S3C64XX_GPIO_F_NR,
1310 .config = &samsung_gpio_cfgs[7],
1312 .base = S3C64XX_GPI(0),
1313 .ngpio = S3C64XX_GPIO_I_NR,
1317 .config = &samsung_gpio_cfgs[7],
1319 .base = S3C64XX_GPJ(0),
1320 .ngpio = S3C64XX_GPIO_J_NR,
1324 .config = &samsung_gpio_cfgs[6],
1326 .base = S3C64XX_GPO(0),
1327 .ngpio = S3C64XX_GPIO_O_NR,
1331 .config = &samsung_gpio_cfgs[6],
1333 .base = S3C64XX_GPP(0),
1334 .ngpio = S3C64XX_GPIO_P_NR,
1338 .config = &samsung_gpio_cfgs[6],
1340 .base = S3C64XX_GPQ(0),
1341 .ngpio = S3C64XX_GPIO_Q_NR,
1345 .base = S3C64XX_GPN_BASE,
1346 .irq_base = IRQ_EINT(0),
1347 .config = &samsung_gpio_cfgs[5],
1349 .base = S3C64XX_GPN(0),
1350 .ngpio = S3C64XX_GPIO_N_NR,
1352 .to_irq = samsung_gpiolib_to_irq,
1359 * S5P6440 GPIO bank summary:
1361 * Bank GPIOs Style SlpCon ExtInt Group
1365 * F 2 2Bit Yes 4 [1]
1367 * H 10 4Bit[2] Yes 6
1368 * I 16 2Bit Yes None
1369 * J 12 2Bit Yes None
1370 * N 16 2Bit No IRQ_EINT
1372 * R 15 4Bit[2] Yes 8
1375 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1376 #ifdef CONFIG_CPU_S5P6440
1379 .base = S5P6440_GPA(0),
1380 .ngpio = S5P6440_GPIO_A_NR,
1385 .base = S5P6440_GPB(0),
1386 .ngpio = S5P6440_GPIO_B_NR,
1391 .base = S5P6440_GPC(0),
1392 .ngpio = S5P6440_GPIO_C_NR,
1396 .base = S5P64X0_GPG_BASE,
1398 .base = S5P6440_GPG(0),
1399 .ngpio = S5P6440_GPIO_G_NR,
1406 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1407 #ifdef CONFIG_CPU_S5P6440
1409 .base = S5P64X0_GPH_BASE + 0x4,
1411 .base = S5P6440_GPH(0),
1412 .ngpio = S5P6440_GPIO_H_NR,
1419 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1420 #ifdef CONFIG_CPU_S5P6440
1422 .base = S5P64X0_GPR_BASE + 0x4,
1423 .config = &s5p64x0_gpio_cfg_rbank,
1425 .base = S5P6440_GPR(0),
1426 .ngpio = S5P6440_GPIO_R_NR,
1433 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1434 #ifdef CONFIG_CPU_S5P6440
1436 .base = S5P64X0_GPF_BASE,
1437 .config = &samsung_gpio_cfgs[6],
1439 .base = S5P6440_GPF(0),
1440 .ngpio = S5P6440_GPIO_F_NR,
1444 .base = S5P64X0_GPI_BASE,
1445 .config = &samsung_gpio_cfgs[4],
1447 .base = S5P6440_GPI(0),
1448 .ngpio = S5P6440_GPIO_I_NR,
1452 .base = S5P64X0_GPJ_BASE,
1453 .config = &samsung_gpio_cfgs[4],
1455 .base = S5P6440_GPJ(0),
1456 .ngpio = S5P6440_GPIO_J_NR,
1460 .base = S5P64X0_GPN_BASE,
1461 .config = &samsung_gpio_cfgs[5],
1463 .base = S5P6440_GPN(0),
1464 .ngpio = S5P6440_GPIO_N_NR,
1468 .base = S5P64X0_GPP_BASE,
1469 .config = &samsung_gpio_cfgs[6],
1471 .base = S5P6440_GPP(0),
1472 .ngpio = S5P6440_GPIO_P_NR,
1480 * S5P6450 GPIO bank summary:
1482 * Bank GPIOs Style SlpCon ExtInt Group
1488 * G 14 4Bit[2] Yes 5
1489 * H 10 4Bit[2] Yes 6
1490 * I 16 2Bit Yes None
1491 * J 12 2Bit Yes None
1493 * N 16 2Bit No IRQ_EINT
1495 * Q 14 2Bit Yes None
1496 * R 15 4Bit[2] Yes None
1499 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1500 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1503 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1504 #ifdef CONFIG_CPU_S5P6450
1507 .base = S5P6450_GPA(0),
1508 .ngpio = S5P6450_GPIO_A_NR,
1513 .base = S5P6450_GPB(0),
1514 .ngpio = S5P6450_GPIO_B_NR,
1519 .base = S5P6450_GPC(0),
1520 .ngpio = S5P6450_GPIO_C_NR,
1525 .base = S5P6450_GPD(0),
1526 .ngpio = S5P6450_GPIO_D_NR,
1530 .base = S5P6450_GPK_BASE,
1532 .base = S5P6450_GPK(0),
1533 .ngpio = S5P6450_GPIO_K_NR,
1540 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1541 #ifdef CONFIG_CPU_S5P6450
1543 .base = S5P64X0_GPG_BASE + 0x4,
1545 .base = S5P6450_GPG(0),
1546 .ngpio = S5P6450_GPIO_G_NR,
1550 .base = S5P64X0_GPH_BASE + 0x4,
1552 .base = S5P6450_GPH(0),
1553 .ngpio = S5P6450_GPIO_H_NR,
1560 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1561 #ifdef CONFIG_CPU_S5P6450
1563 .base = S5P64X0_GPR_BASE + 0x4,
1564 .config = &s5p64x0_gpio_cfg_rbank,
1566 .base = S5P6450_GPR(0),
1567 .ngpio = S5P6450_GPIO_R_NR,
1574 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1575 #ifdef CONFIG_CPU_S5P6450
1577 .base = S5P64X0_GPF_BASE,
1578 .config = &samsung_gpio_cfgs[6],
1580 .base = S5P6450_GPF(0),
1581 .ngpio = S5P6450_GPIO_F_NR,
1585 .base = S5P64X0_GPI_BASE,
1586 .config = &samsung_gpio_cfgs[4],
1588 .base = S5P6450_GPI(0),
1589 .ngpio = S5P6450_GPIO_I_NR,
1593 .base = S5P64X0_GPJ_BASE,
1594 .config = &samsung_gpio_cfgs[4],
1596 .base = S5P6450_GPJ(0),
1597 .ngpio = S5P6450_GPIO_J_NR,
1601 .base = S5P64X0_GPN_BASE,
1602 .config = &samsung_gpio_cfgs[5],
1604 .base = S5P6450_GPN(0),
1605 .ngpio = S5P6450_GPIO_N_NR,
1609 .base = S5P64X0_GPP_BASE,
1610 .config = &samsung_gpio_cfgs[6],
1612 .base = S5P6450_GPP(0),
1613 .ngpio = S5P6450_GPIO_P_NR,
1617 .base = S5P6450_GPQ_BASE,
1618 .config = &samsung_gpio_cfgs[5],
1620 .base = S5P6450_GPQ(0),
1621 .ngpio = S5P6450_GPIO_Q_NR,
1625 .base = S5P6450_GPS_BASE,
1626 .config = &samsung_gpio_cfgs[6],
1628 .base = S5P6450_GPS(0),
1629 .ngpio = S5P6450_GPIO_S_NR,
1637 * S5PC100 GPIO bank summary:
1639 * Bank GPIOs Style INT Type
1640 * A0 8 4Bit GPIO_INT0
1641 * A1 5 4Bit GPIO_INT1
1642 * B 8 4Bit GPIO_INT2
1643 * C 5 4Bit GPIO_INT3
1644 * D 7 4Bit GPIO_INT4
1645 * E0 8 4Bit GPIO_INT5
1646 * E1 6 4Bit GPIO_INT6
1647 * F0 8 4Bit GPIO_INT7
1648 * F1 8 4Bit GPIO_INT8
1649 * F2 8 4Bit GPIO_INT9
1650 * F3 4 4Bit GPIO_INT10
1651 * G0 8 4Bit GPIO_INT11
1652 * G1 3 4Bit GPIO_INT12
1653 * G2 7 4Bit GPIO_INT13
1654 * G3 7 4Bit GPIO_INT14
1655 * H0 8 4Bit WKUP_INT
1656 * H1 8 4Bit WKUP_INT
1657 * H2 8 4Bit WKUP_INT
1658 * H3 8 4Bit WKUP_INT
1659 * I 8 4Bit GPIO_INT15
1660 * J0 8 4Bit GPIO_INT16
1661 * J1 5 4Bit GPIO_INT17
1662 * J2 8 4Bit GPIO_INT18
1663 * J3 8 4Bit GPIO_INT19
1664 * J4 4 4Bit GPIO_INT20
1675 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1676 #ifdef CONFIG_CPU_S5PC100
1679 .base = S5PC100_GPA0(0),
1680 .ngpio = S5PC100_GPIO_A0_NR,
1685 .base = S5PC100_GPA1(0),
1686 .ngpio = S5PC100_GPIO_A1_NR,
1691 .base = S5PC100_GPB(0),
1692 .ngpio = S5PC100_GPIO_B_NR,
1697 .base = S5PC100_GPC(0),
1698 .ngpio = S5PC100_GPIO_C_NR,
1703 .base = S5PC100_GPD(0),
1704 .ngpio = S5PC100_GPIO_D_NR,
1709 .base = S5PC100_GPE0(0),
1710 .ngpio = S5PC100_GPIO_E0_NR,
1715 .base = S5PC100_GPE1(0),
1716 .ngpio = S5PC100_GPIO_E1_NR,
1721 .base = S5PC100_GPF0(0),
1722 .ngpio = S5PC100_GPIO_F0_NR,
1727 .base = S5PC100_GPF1(0),
1728 .ngpio = S5PC100_GPIO_F1_NR,
1733 .base = S5PC100_GPF2(0),
1734 .ngpio = S5PC100_GPIO_F2_NR,
1739 .base = S5PC100_GPF3(0),
1740 .ngpio = S5PC100_GPIO_F3_NR,
1745 .base = S5PC100_GPG0(0),
1746 .ngpio = S5PC100_GPIO_G0_NR,
1751 .base = S5PC100_GPG1(0),
1752 .ngpio = S5PC100_GPIO_G1_NR,
1757 .base = S5PC100_GPG2(0),
1758 .ngpio = S5PC100_GPIO_G2_NR,
1763 .base = S5PC100_GPG3(0),
1764 .ngpio = S5PC100_GPIO_G3_NR,
1769 .base = S5PC100_GPI(0),
1770 .ngpio = S5PC100_GPIO_I_NR,
1775 .base = S5PC100_GPJ0(0),
1776 .ngpio = S5PC100_GPIO_J0_NR,
1781 .base = S5PC100_GPJ1(0),
1782 .ngpio = S5PC100_GPIO_J1_NR,
1787 .base = S5PC100_GPJ2(0),
1788 .ngpio = S5PC100_GPIO_J2_NR,
1793 .base = S5PC100_GPJ3(0),
1794 .ngpio = S5PC100_GPIO_J3_NR,
1799 .base = S5PC100_GPJ4(0),
1800 .ngpio = S5PC100_GPIO_J4_NR,
1805 .base = S5PC100_GPK0(0),
1806 .ngpio = S5PC100_GPIO_K0_NR,
1811 .base = S5PC100_GPK1(0),
1812 .ngpio = S5PC100_GPIO_K1_NR,
1817 .base = S5PC100_GPK2(0),
1818 .ngpio = S5PC100_GPIO_K2_NR,
1823 .base = S5PC100_GPK3(0),
1824 .ngpio = S5PC100_GPIO_K3_NR,
1829 .base = S5PC100_GPL0(0),
1830 .ngpio = S5PC100_GPIO_L0_NR,
1835 .base = S5PC100_GPL1(0),
1836 .ngpio = S5PC100_GPIO_L1_NR,
1841 .base = S5PC100_GPL2(0),
1842 .ngpio = S5PC100_GPIO_L2_NR,
1847 .base = S5PC100_GPL3(0),
1848 .ngpio = S5PC100_GPIO_L3_NR,
1853 .base = S5PC100_GPL4(0),
1854 .ngpio = S5PC100_GPIO_L4_NR,
1858 .base = (S5P_VA_GPIO + 0xC00),
1859 .irq_base = IRQ_EINT(0),
1861 .base = S5PC100_GPH0(0),
1862 .ngpio = S5PC100_GPIO_H0_NR,
1864 .to_irq = samsung_gpiolib_to_irq,
1867 .base = (S5P_VA_GPIO + 0xC20),
1868 .irq_base = IRQ_EINT(8),
1870 .base = S5PC100_GPH1(0),
1871 .ngpio = S5PC100_GPIO_H1_NR,
1873 .to_irq = samsung_gpiolib_to_irq,
1876 .base = (S5P_VA_GPIO + 0xC40),
1877 .irq_base = IRQ_EINT(16),
1879 .base = S5PC100_GPH2(0),
1880 .ngpio = S5PC100_GPIO_H2_NR,
1882 .to_irq = samsung_gpiolib_to_irq,
1885 .base = (S5P_VA_GPIO + 0xC60),
1886 .irq_base = IRQ_EINT(24),
1888 .base = S5PC100_GPH3(0),
1889 .ngpio = S5PC100_GPIO_H3_NR,
1891 .to_irq = samsung_gpiolib_to_irq,
1898 * Followings are the gpio banks in S5PV210/S5PC110
1900 * The 'config' member when left to NULL, is initialized to the default
1901 * structure samsung_gpio_cfgs[3] in the init function below.
1903 * The 'base' member is also initialized in the init function below.
1904 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1905 * uses the above macro and depends on the banks being listed in order here.
1908 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1909 #ifdef CONFIG_CPU_S5PV210
1912 .base = S5PV210_GPA0(0),
1913 .ngpio = S5PV210_GPIO_A0_NR,
1918 .base = S5PV210_GPA1(0),
1919 .ngpio = S5PV210_GPIO_A1_NR,
1924 .base = S5PV210_GPB(0),
1925 .ngpio = S5PV210_GPIO_B_NR,
1930 .base = S5PV210_GPC0(0),
1931 .ngpio = S5PV210_GPIO_C0_NR,
1936 .base = S5PV210_GPC1(0),
1937 .ngpio = S5PV210_GPIO_C1_NR,
1942 .base = S5PV210_GPD0(0),
1943 .ngpio = S5PV210_GPIO_D0_NR,
1948 .base = S5PV210_GPD1(0),
1949 .ngpio = S5PV210_GPIO_D1_NR,
1954 .base = S5PV210_GPE0(0),
1955 .ngpio = S5PV210_GPIO_E0_NR,
1960 .base = S5PV210_GPE1(0),
1961 .ngpio = S5PV210_GPIO_E1_NR,
1966 .base = S5PV210_GPF0(0),
1967 .ngpio = S5PV210_GPIO_F0_NR,
1972 .base = S5PV210_GPF1(0),
1973 .ngpio = S5PV210_GPIO_F1_NR,
1978 .base = S5PV210_GPF2(0),
1979 .ngpio = S5PV210_GPIO_F2_NR,
1984 .base = S5PV210_GPF3(0),
1985 .ngpio = S5PV210_GPIO_F3_NR,
1990 .base = S5PV210_GPG0(0),
1991 .ngpio = S5PV210_GPIO_G0_NR,
1996 .base = S5PV210_GPG1(0),
1997 .ngpio = S5PV210_GPIO_G1_NR,
2002 .base = S5PV210_GPG2(0),
2003 .ngpio = S5PV210_GPIO_G2_NR,
2008 .base = S5PV210_GPG3(0),
2009 .ngpio = S5PV210_GPIO_G3_NR,
2014 .base = S5PV210_GPI(0),
2015 .ngpio = S5PV210_GPIO_I_NR,
2020 .base = S5PV210_GPJ0(0),
2021 .ngpio = S5PV210_GPIO_J0_NR,
2026 .base = S5PV210_GPJ1(0),
2027 .ngpio = S5PV210_GPIO_J1_NR,
2032 .base = S5PV210_GPJ2(0),
2033 .ngpio = S5PV210_GPIO_J2_NR,
2038 .base = S5PV210_GPJ3(0),
2039 .ngpio = S5PV210_GPIO_J3_NR,
2044 .base = S5PV210_GPJ4(0),
2045 .ngpio = S5PV210_GPIO_J4_NR,
2050 .base = S5PV210_MP01(0),
2051 .ngpio = S5PV210_GPIO_MP01_NR,
2056 .base = S5PV210_MP02(0),
2057 .ngpio = S5PV210_GPIO_MP02_NR,
2062 .base = S5PV210_MP03(0),
2063 .ngpio = S5PV210_GPIO_MP03_NR,
2068 .base = S5PV210_MP04(0),
2069 .ngpio = S5PV210_GPIO_MP04_NR,
2074 .base = S5PV210_MP05(0),
2075 .ngpio = S5PV210_GPIO_MP05_NR,
2079 .base = (S5P_VA_GPIO + 0xC00),
2080 .irq_base = IRQ_EINT(0),
2082 .base = S5PV210_GPH0(0),
2083 .ngpio = S5PV210_GPIO_H0_NR,
2085 .to_irq = samsung_gpiolib_to_irq,
2088 .base = (S5P_VA_GPIO + 0xC20),
2089 .irq_base = IRQ_EINT(8),
2091 .base = S5PV210_GPH1(0),
2092 .ngpio = S5PV210_GPIO_H1_NR,
2094 .to_irq = samsung_gpiolib_to_irq,
2097 .base = (S5P_VA_GPIO + 0xC40),
2098 .irq_base = IRQ_EINT(16),
2100 .base = S5PV210_GPH2(0),
2101 .ngpio = S5PV210_GPIO_H2_NR,
2103 .to_irq = samsung_gpiolib_to_irq,
2106 .base = (S5P_VA_GPIO + 0xC60),
2107 .irq_base = IRQ_EINT(24),
2109 .base = S5PV210_GPH3(0),
2110 .ngpio = S5PV210_GPIO_H3_NR,
2112 .to_irq = samsung_gpiolib_to_irq,
2119 * Followings are the gpio banks in EXYNOS SoCs
2121 * The 'config' member when left to NULL, is initialized to the default
2122 * structure exynos_gpio_cfg in the init function below.
2124 * The 'base' member is also initialized in the init function below.
2125 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2126 * uses the above macro and depends on the banks being listed in order here.
2129 #ifdef CONFIG_ARCH_EXYNOS4
2130 static struct samsung_gpio_chip exynos4_gpios_1[] = {
2133 .base = EXYNOS4_GPA0(0),
2134 .ngpio = EXYNOS4_GPIO_A0_NR,
2139 .base = EXYNOS4_GPA1(0),
2140 .ngpio = EXYNOS4_GPIO_A1_NR,
2145 .base = EXYNOS4_GPB(0),
2146 .ngpio = EXYNOS4_GPIO_B_NR,
2151 .base = EXYNOS4_GPC0(0),
2152 .ngpio = EXYNOS4_GPIO_C0_NR,
2157 .base = EXYNOS4_GPC1(0),
2158 .ngpio = EXYNOS4_GPIO_C1_NR,
2163 .base = EXYNOS4_GPD0(0),
2164 .ngpio = EXYNOS4_GPIO_D0_NR,
2169 .base = EXYNOS4_GPD1(0),
2170 .ngpio = EXYNOS4_GPIO_D1_NR,
2175 .base = EXYNOS4_GPE0(0),
2176 .ngpio = EXYNOS4_GPIO_E0_NR,
2181 .base = EXYNOS4_GPE1(0),
2182 .ngpio = EXYNOS4_GPIO_E1_NR,
2187 .base = EXYNOS4_GPE2(0),
2188 .ngpio = EXYNOS4_GPIO_E2_NR,
2193 .base = EXYNOS4_GPE3(0),
2194 .ngpio = EXYNOS4_GPIO_E3_NR,
2199 .base = EXYNOS4_GPE4(0),
2200 .ngpio = EXYNOS4_GPIO_E4_NR,
2205 .base = EXYNOS4_GPF0(0),
2206 .ngpio = EXYNOS4_GPIO_F0_NR,
2211 .base = EXYNOS4_GPF1(0),
2212 .ngpio = EXYNOS4_GPIO_F1_NR,
2217 .base = EXYNOS4_GPF2(0),
2218 .ngpio = EXYNOS4_GPIO_F2_NR,
2223 .base = EXYNOS4_GPF3(0),
2224 .ngpio = EXYNOS4_GPIO_F3_NR,
2231 #ifdef CONFIG_ARCH_EXYNOS4
2232 static struct samsung_gpio_chip exynos4_gpios_2[] = {
2235 .base = EXYNOS4_GPJ0(0),
2236 .ngpio = EXYNOS4_GPIO_J0_NR,
2241 .base = EXYNOS4_GPJ1(0),
2242 .ngpio = EXYNOS4_GPIO_J1_NR,
2247 .base = EXYNOS4_GPK0(0),
2248 .ngpio = EXYNOS4_GPIO_K0_NR,
2253 .base = EXYNOS4_GPK1(0),
2254 .ngpio = EXYNOS4_GPIO_K1_NR,
2259 .base = EXYNOS4_GPK2(0),
2260 .ngpio = EXYNOS4_GPIO_K2_NR,
2265 .base = EXYNOS4_GPK3(0),
2266 .ngpio = EXYNOS4_GPIO_K3_NR,
2271 .base = EXYNOS4_GPL0(0),
2272 .ngpio = EXYNOS4_GPIO_L0_NR,
2277 .base = EXYNOS4_GPL1(0),
2278 .ngpio = EXYNOS4_GPIO_L1_NR,
2283 .base = EXYNOS4_GPL2(0),
2284 .ngpio = EXYNOS4_GPIO_L2_NR,
2288 .config = &samsung_gpio_cfgs[8],
2290 .base = EXYNOS4_GPY0(0),
2291 .ngpio = EXYNOS4_GPIO_Y0_NR,
2295 .config = &samsung_gpio_cfgs[8],
2297 .base = EXYNOS4_GPY1(0),
2298 .ngpio = EXYNOS4_GPIO_Y1_NR,
2302 .config = &samsung_gpio_cfgs[8],
2304 .base = EXYNOS4_GPY2(0),
2305 .ngpio = EXYNOS4_GPIO_Y2_NR,
2309 .config = &samsung_gpio_cfgs[8],
2311 .base = EXYNOS4_GPY3(0),
2312 .ngpio = EXYNOS4_GPIO_Y3_NR,
2316 .config = &samsung_gpio_cfgs[8],
2318 .base = EXYNOS4_GPY4(0),
2319 .ngpio = EXYNOS4_GPIO_Y4_NR,
2323 .config = &samsung_gpio_cfgs[8],
2325 .base = EXYNOS4_GPY5(0),
2326 .ngpio = EXYNOS4_GPIO_Y5_NR,
2330 .config = &samsung_gpio_cfgs[8],
2332 .base = EXYNOS4_GPY6(0),
2333 .ngpio = EXYNOS4_GPIO_Y6_NR,
2337 .config = &samsung_gpio_cfgs[9],
2338 .irq_base = IRQ_EINT(0),
2340 .base = EXYNOS4_GPX0(0),
2341 .ngpio = EXYNOS4_GPIO_X0_NR,
2343 .to_irq = samsung_gpiolib_to_irq,
2346 .config = &samsung_gpio_cfgs[9],
2347 .irq_base = IRQ_EINT(8),
2349 .base = EXYNOS4_GPX1(0),
2350 .ngpio = EXYNOS4_GPIO_X1_NR,
2352 .to_irq = samsung_gpiolib_to_irq,
2355 .config = &samsung_gpio_cfgs[9],
2356 .irq_base = IRQ_EINT(16),
2358 .base = EXYNOS4_GPX2(0),
2359 .ngpio = EXYNOS4_GPIO_X2_NR,
2361 .to_irq = samsung_gpiolib_to_irq,
2364 .config = &samsung_gpio_cfgs[9],
2365 .irq_base = IRQ_EINT(24),
2367 .base = EXYNOS4_GPX3(0),
2368 .ngpio = EXYNOS4_GPIO_X3_NR,
2370 .to_irq = samsung_gpiolib_to_irq,
2376 #ifdef CONFIG_ARCH_EXYNOS4
2377 static struct samsung_gpio_chip exynos4_gpios_3[] = {
2380 .base = EXYNOS4_GPZ(0),
2381 .ngpio = EXYNOS4_GPIO_Z_NR,
2388 #ifdef CONFIG_SOC_EXYNOS5250
2389 static struct samsung_gpio_chip exynos5_gpios_1[] = {
2392 .base = EXYNOS5_GPA0(0),
2393 .ngpio = EXYNOS5_GPIO_A0_NR,
2398 .base = EXYNOS5_GPA1(0),
2399 .ngpio = EXYNOS5_GPIO_A1_NR,
2404 .base = EXYNOS5_GPA2(0),
2405 .ngpio = EXYNOS5_GPIO_A2_NR,
2410 .base = EXYNOS5_GPB0(0),
2411 .ngpio = EXYNOS5_GPIO_B0_NR,
2416 .base = EXYNOS5_GPB1(0),
2417 .ngpio = EXYNOS5_GPIO_B1_NR,
2422 .base = EXYNOS5_GPB2(0),
2423 .ngpio = EXYNOS5_GPIO_B2_NR,
2428 .base = EXYNOS5_GPB3(0),
2429 .ngpio = EXYNOS5_GPIO_B3_NR,
2434 .base = EXYNOS5_GPC0(0),
2435 .ngpio = EXYNOS5_GPIO_C0_NR,
2440 .base = EXYNOS5_GPC1(0),
2441 .ngpio = EXYNOS5_GPIO_C1_NR,
2446 .base = EXYNOS5_GPC2(0),
2447 .ngpio = EXYNOS5_GPIO_C2_NR,
2452 .base = EXYNOS5_GPC3(0),
2453 .ngpio = EXYNOS5_GPIO_C3_NR,
2458 .base = EXYNOS5_GPD0(0),
2459 .ngpio = EXYNOS5_GPIO_D0_NR,
2464 .base = EXYNOS5_GPD1(0),
2465 .ngpio = EXYNOS5_GPIO_D1_NR,
2470 .base = EXYNOS5_GPY0(0),
2471 .ngpio = EXYNOS5_GPIO_Y0_NR,
2476 .base = EXYNOS5_GPY1(0),
2477 .ngpio = EXYNOS5_GPIO_Y1_NR,
2482 .base = EXYNOS5_GPY2(0),
2483 .ngpio = EXYNOS5_GPIO_Y2_NR,
2488 .base = EXYNOS5_GPY3(0),
2489 .ngpio = EXYNOS5_GPIO_Y3_NR,
2494 .base = EXYNOS5_GPY4(0),
2495 .ngpio = EXYNOS5_GPIO_Y4_NR,
2500 .base = EXYNOS5_GPY5(0),
2501 .ngpio = EXYNOS5_GPIO_Y5_NR,
2506 .base = EXYNOS5_GPY6(0),
2507 .ngpio = EXYNOS5_GPIO_Y6_NR,
2512 .base = EXYNOS5_GPC4(0),
2513 .ngpio = EXYNOS5_GPIO_C4_NR,
2517 .config = &samsung_gpio_cfgs[9],
2518 .irq_base = IRQ_EINT(0),
2520 .base = EXYNOS5_GPX0(0),
2521 .ngpio = EXYNOS5_GPIO_X0_NR,
2523 .to_irq = samsung_gpiolib_to_irq,
2526 .config = &samsung_gpio_cfgs[9],
2527 .irq_base = IRQ_EINT(8),
2529 .base = EXYNOS5_GPX1(0),
2530 .ngpio = EXYNOS5_GPIO_X1_NR,
2532 .to_irq = samsung_gpiolib_to_irq,
2535 .config = &samsung_gpio_cfgs[9],
2536 .irq_base = IRQ_EINT(16),
2538 .base = EXYNOS5_GPX2(0),
2539 .ngpio = EXYNOS5_GPIO_X2_NR,
2541 .to_irq = samsung_gpiolib_to_irq,
2544 .config = &samsung_gpio_cfgs[9],
2545 .irq_base = IRQ_EINT(24),
2547 .base = EXYNOS5_GPX3(0),
2548 .ngpio = EXYNOS5_GPIO_X3_NR,
2550 .to_irq = samsung_gpiolib_to_irq,
2556 #ifdef CONFIG_SOC_EXYNOS5250
2557 static struct samsung_gpio_chip exynos5_gpios_2[] = {
2560 .base = EXYNOS5_GPE0(0),
2561 .ngpio = EXYNOS5_GPIO_E0_NR,
2566 .base = EXYNOS5_GPE1(0),
2567 .ngpio = EXYNOS5_GPIO_E1_NR,
2572 .base = EXYNOS5_GPF0(0),
2573 .ngpio = EXYNOS5_GPIO_F0_NR,
2578 .base = EXYNOS5_GPF1(0),
2579 .ngpio = EXYNOS5_GPIO_F1_NR,
2584 .base = EXYNOS5_GPG0(0),
2585 .ngpio = EXYNOS5_GPIO_G0_NR,
2590 .base = EXYNOS5_GPG1(0),
2591 .ngpio = EXYNOS5_GPIO_G1_NR,
2596 .base = EXYNOS5_GPG2(0),
2597 .ngpio = EXYNOS5_GPIO_G2_NR,
2602 .base = EXYNOS5_GPH0(0),
2603 .ngpio = EXYNOS5_GPIO_H0_NR,
2608 .base = EXYNOS5_GPH1(0),
2609 .ngpio = EXYNOS5_GPIO_H1_NR,
2617 #ifdef CONFIG_SOC_EXYNOS5250
2618 static struct samsung_gpio_chip exynos5_gpios_3[] = {
2621 .base = EXYNOS5_GPV0(0),
2622 .ngpio = EXYNOS5_GPIO_V0_NR,
2627 .base = EXYNOS5_GPV1(0),
2628 .ngpio = EXYNOS5_GPIO_V1_NR,
2633 .base = EXYNOS5_GPV2(0),
2634 .ngpio = EXYNOS5_GPIO_V2_NR,
2639 .base = EXYNOS5_GPV3(0),
2640 .ngpio = EXYNOS5_GPIO_V3_NR,
2645 .base = EXYNOS5_GPV4(0),
2646 .ngpio = EXYNOS5_GPIO_V4_NR,
2653 #ifdef CONFIG_SOC_EXYNOS5250
2654 static struct samsung_gpio_chip exynos5_gpios_4[] = {
2657 .base = EXYNOS5_GPZ(0),
2658 .ngpio = EXYNOS5_GPIO_Z_NR,
2666 #if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2667 static int exynos_gpio_xlate(struct gpio_chip *gc,
2668 const struct of_phandle_args *gpiospec, u32 *flags)
2672 if (WARN_ON(gc->of_gpio_n_cells < 4))
2675 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
2678 if (gpiospec->args[0] > gc->ngpio)
2681 pin = gc->base + gpiospec->args[0];
2683 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
2684 pr_warn("gpio_xlate: failed to set pin function\n");
2685 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
2686 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
2687 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
2688 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2691 *flags = gpiospec->args[2] >> 16;
2693 return gpiospec->args[0];
2696 static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2697 { .compatible = "samsung,exynos4-gpio", },
2701 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2702 u64 base, u64 offset)
2704 struct gpio_chip *gc = &chip->chip;
2707 if (!of_have_populated_dt())
2710 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2711 gc->of_node = of_find_matching_node_by_address(NULL,
2712 exynos_gpio_dt_match, address);
2714 pr_info("gpio: device tree node not found for gpio controller"
2715 " with base address %08llx\n", address);
2718 gc->of_gpio_n_cells = 4;
2719 gc->of_xlate = exynos_gpio_xlate;
2721 #elif defined(CONFIG_ARCH_EXYNOS)
2722 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2723 u64 base, u64 offset)
2727 #endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2729 static __init void exynos4_gpiolib_init(void)
2731 #ifdef CONFIG_CPU_EXYNOS4210
2732 struct samsung_gpio_chip *chip;
2734 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2736 void __iomem *gpx_base;
2739 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2740 if (gpio_base1 == NULL) {
2741 pr_err("unable to ioremap for gpio_base1\n");
2745 chip = exynos4_gpios_1;
2746 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2748 for (i = 0; i < nr_chips; i++, chip++) {
2749 if (!chip->config) {
2750 chip->config = &exynos_gpio_cfg;
2751 chip->group = group++;
2753 exynos_gpiolib_attach_ofnode(chip,
2754 EXYNOS4_PA_GPIO1, i * 0x20);
2756 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2757 nr_chips, gpio_base1);
2760 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2761 if (gpio_base2 == NULL) {
2762 pr_err("unable to ioremap for gpio_base2\n");
2766 /* need to set base address for gpx */
2767 chip = &exynos4_gpios_2[16];
2768 gpx_base = gpio_base2 + 0xC00;
2769 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2770 chip->base = gpx_base;
2772 chip = exynos4_gpios_2;
2773 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2775 for (i = 0; i < nr_chips; i++, chip++) {
2776 if (!chip->config) {
2777 chip->config = &exynos_gpio_cfg;
2778 chip->group = group++;
2780 exynos_gpiolib_attach_ofnode(chip,
2781 EXYNOS4_PA_GPIO2, i * 0x20);
2783 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2784 nr_chips, gpio_base2);
2787 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2788 if (gpio_base3 == NULL) {
2789 pr_err("unable to ioremap for gpio_base3\n");
2793 chip = exynos4_gpios_3;
2794 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2796 for (i = 0; i < nr_chips; i++, chip++) {
2797 if (!chip->config) {
2798 chip->config = &exynos_gpio_cfg;
2799 chip->group = group++;
2801 exynos_gpiolib_attach_ofnode(chip,
2802 EXYNOS4_PA_GPIO3, i * 0x20);
2804 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2805 nr_chips, gpio_base3);
2807 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2808 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2809 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2815 iounmap(gpio_base2);
2817 iounmap(gpio_base1);
2820 #endif /* CONFIG_CPU_EXYNOS4210 */
2823 static __init void exynos5_gpiolib_init(void)
2825 #ifdef CONFIG_SOC_EXYNOS5250
2826 struct samsung_gpio_chip *chip;
2828 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2830 void __iomem *gpx_base;
2833 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2834 if (gpio_base1 == NULL) {
2835 pr_err("unable to ioremap for gpio_base1\n");
2839 /* need to set base address for gpc4 */
2840 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
2842 /* need to set base address for gpx */
2843 chip = &exynos5_gpios_1[21];
2844 gpx_base = gpio_base1 + 0xC00;
2845 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2846 chip->base = gpx_base;
2848 chip = exynos5_gpios_1;
2849 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2851 for (i = 0; i < nr_chips; i++, chip++) {
2852 if (!chip->config) {
2853 chip->config = &exynos_gpio_cfg;
2854 chip->group = group++;
2856 exynos_gpiolib_attach_ofnode(chip,
2857 EXYNOS5_PA_GPIO1, i * 0x20);
2859 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2860 nr_chips, gpio_base1);
2863 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2864 if (gpio_base2 == NULL) {
2865 pr_err("unable to ioremap for gpio_base2\n");
2869 chip = exynos5_gpios_2;
2870 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2872 for (i = 0; i < nr_chips; i++, chip++) {
2873 if (!chip->config) {
2874 chip->config = &exynos_gpio_cfg;
2875 chip->group = group++;
2877 exynos_gpiolib_attach_ofnode(chip,
2878 EXYNOS5_PA_GPIO2, i * 0x20);
2880 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2881 nr_chips, gpio_base2);
2884 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2885 if (gpio_base3 == NULL) {
2886 pr_err("unable to ioremap for gpio_base3\n");
2890 /* need to set base address for gpv */
2891 exynos5_gpios_3[0].base = gpio_base3;
2892 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2893 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2894 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2895 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2897 chip = exynos5_gpios_3;
2898 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2900 for (i = 0; i < nr_chips; i++, chip++) {
2901 if (!chip->config) {
2902 chip->config = &exynos_gpio_cfg;
2903 chip->group = group++;
2905 exynos_gpiolib_attach_ofnode(chip,
2906 EXYNOS5_PA_GPIO3, i * 0x20);
2908 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2909 nr_chips, gpio_base3);
2912 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2913 if (gpio_base4 == NULL) {
2914 pr_err("unable to ioremap for gpio_base4\n");
2918 chip = exynos5_gpios_4;
2919 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2921 for (i = 0; i < nr_chips; i++, chip++) {
2922 if (!chip->config) {
2923 chip->config = &exynos_gpio_cfg;
2924 chip->group = group++;
2926 exynos_gpiolib_attach_ofnode(chip,
2927 EXYNOS5_PA_GPIO4, i * 0x20);
2929 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2930 nr_chips, gpio_base4);
2934 iounmap(gpio_base3);
2936 iounmap(gpio_base2);
2938 iounmap(gpio_base1);
2942 #endif /* CONFIG_SOC_EXYNOS5250 */
2945 /* TODO: cleanup soc_is_* */
2946 static __init int samsung_gpiolib_init(void)
2948 struct samsung_gpio_chip *chip;
2952 #if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
2954 * This gpio driver includes support for device tree support and there
2955 * are platforms using it. In order to maintain compatibility with those
2956 * platforms, and to allow non-dt Exynos4210 platforms to use this
2957 * gpiolib support, a check is added to find out if there is a active
2958 * pin-controller driver support available. If it is available, this
2959 * gpiolib support is ignored and the gpiolib support available in
2960 * pin-controller driver is used. This is a temporary check and will go
2961 * away when all of the Exynos4210 platforms have switched to using
2962 * device tree and the pin-ctrl driver.
2964 struct device_node *pctrl_np;
2965 static const struct of_device_id exynos_pinctrl_ids[] = {
2966 { .compatible = "samsung,s3c2412-pinctrl", },
2967 { .compatible = "samsung,s3c2416-pinctrl", },
2968 { .compatible = "samsung,s3c2440-pinctrl", },
2969 { .compatible = "samsung,s3c2450-pinctrl", },
2970 { .compatible = "samsung,exynos4210-pinctrl", },
2971 { .compatible = "samsung,exynos4x12-pinctrl", },
2972 { .compatible = "samsung,exynos5250-pinctrl", },
2973 { .compatible = "samsung,exynos5440-pinctrl", },
2976 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
2977 if (pctrl_np && of_device_is_available(pctrl_np))
2981 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2983 if (soc_is_s3c24xx()) {
2984 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
2985 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
2986 } else if (soc_is_s3c64xx()) {
2987 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
2988 ARRAY_SIZE(s3c64xx_gpios_2bit),
2989 S3C64XX_VA_GPIO + 0xE0, 0x20);
2990 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
2991 ARRAY_SIZE(s3c64xx_gpios_4bit),
2993 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2994 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2995 } else if (soc_is_s5p6440()) {
2996 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2997 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2998 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2999 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
3000 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
3001 ARRAY_SIZE(s5p6440_gpios_4bit2));
3002 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
3003 ARRAY_SIZE(s5p6440_gpios_rbank));
3004 } else if (soc_is_s5p6450()) {
3005 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
3006 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
3007 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
3008 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
3009 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
3010 ARRAY_SIZE(s5p6450_gpios_4bit2));
3011 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
3012 ARRAY_SIZE(s5p6450_gpios_rbank));
3013 } else if (soc_is_s5pc100()) {
3015 chip = s5pc100_gpios_4bit;
3016 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
3018 for (i = 0; i < nr_chips; i++, chip++) {
3019 if (!chip->config) {
3020 chip->config = &samsung_gpio_cfgs[3];
3021 chip->group = group++;
3024 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
3025 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
3026 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3028 } else if (soc_is_s5pv210()) {
3030 chip = s5pv210_gpios_4bit;
3031 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
3033 for (i = 0; i < nr_chips; i++, chip++) {
3034 if (!chip->config) {
3035 chip->config = &samsung_gpio_cfgs[3];
3036 chip->group = group++;
3039 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
3040 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
3041 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3043 } else if (soc_is_exynos4210()) {
3044 exynos4_gpiolib_init();
3045 } else if (soc_is_exynos5250()) {
3046 exynos5_gpiolib_init();
3048 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3054 core_initcall(samsung_gpiolib_init);
3056 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
3058 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3059 unsigned long flags;
3066 offset = pin - chip->chip.base;
3068 samsung_gpio_lock(chip, flags);
3069 ret = samsung_gpio_do_setcfg(chip, offset, config);
3070 samsung_gpio_unlock(chip, flags);
3074 EXPORT_SYMBOL(s3c_gpio_cfgpin);
3076 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3081 for (; nr > 0; nr--, start++) {
3082 ret = s3c_gpio_cfgpin(start, cfg);
3089 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3091 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3092 unsigned int cfg, samsung_gpio_pull_t pull)
3096 for (; nr > 0; nr--, start++) {
3097 s3c_gpio_setpull(start, pull);
3098 ret = s3c_gpio_cfgpin(start, cfg);
3105 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3107 unsigned s3c_gpio_getcfg(unsigned int pin)
3109 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3110 unsigned long flags;
3115 offset = pin - chip->chip.base;
3117 samsung_gpio_lock(chip, flags);
3118 ret = samsung_gpio_do_getcfg(chip, offset);
3119 samsung_gpio_unlock(chip, flags);
3124 EXPORT_SYMBOL(s3c_gpio_getcfg);
3126 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3128 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3129 unsigned long flags;
3135 offset = pin - chip->chip.base;
3137 samsung_gpio_lock(chip, flags);
3138 ret = samsung_gpio_do_setpull(chip, offset, pull);
3139 samsung_gpio_unlock(chip, flags);
3143 EXPORT_SYMBOL(s3c_gpio_setpull);
3145 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3147 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3148 unsigned long flags;
3153 offset = pin - chip->chip.base;
3155 samsung_gpio_lock(chip, flags);
3156 pup = samsung_gpio_do_getpull(chip, offset);
3157 samsung_gpio_unlock(chip, flags);
3160 return (__force samsung_gpio_pull_t)pup;
3162 EXPORT_SYMBOL(s3c_gpio_getpull);
3164 #ifdef CONFIG_S5P_GPIO_DRVSTR
3165 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3167 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3176 off = pin - chip->chip.base;
3178 reg = chip->base + 0x0C;
3180 drvstr = __raw_readl(reg);
3181 drvstr = drvstr >> shift;
3184 return (__force s5p_gpio_drvstr_t)drvstr;
3186 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3188 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3190 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3199 off = pin - chip->chip.base;
3201 reg = chip->base + 0x0C;
3203 tmp = __raw_readl(reg);
3204 tmp &= ~(0x3 << shift);
3205 tmp |= drvstr << shift;
3207 __raw_writel(tmp, reg);
3211 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3212 #endif /* CONFIG_S5P_GPIO_DRVSTR */
3214 #ifdef CONFIG_PLAT_S3C24XX
3215 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3217 unsigned long flags;
3218 unsigned long misccr;
3220 local_irq_save(flags);
3221 misccr = __raw_readl(S3C24XX_MISCCR);
3224 __raw_writel(misccr, S3C24XX_MISCCR);
3225 local_irq_restore(flags);
3229 EXPORT_SYMBOL(s3c2410_modify_misccr);