2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
30 #include <mach/hardware.h>
32 #include <mach/regs-clock.h>
33 #include <mach/regs-gpio.h>
36 #include <plat/gpio-core.h>
37 #include <plat/gpio-cfg.h>
38 #include <plat/gpio-cfg-helpers.h>
39 #include <plat/gpio-fns.h>
43 #define gpio_dbg(x...) do { } while (0)
45 #define gpio_dbg(x...) printk(KERN_DEBUG x)
48 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
49 unsigned int off, samsung_gpio_pull_t pull)
51 void __iomem *reg = chip->base + 0x08;
55 pup = __raw_readl(reg);
58 __raw_writel(pup, reg);
63 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
66 void __iomem *reg = chip->base + 0x08;
68 u32 pup = __raw_readl(reg);
73 return (__force samsung_gpio_pull_t)pup;
76 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
77 unsigned int off, samsung_gpio_pull_t pull)
80 case S3C_GPIO_PULL_NONE:
83 case S3C_GPIO_PULL_UP:
86 case S3C_GPIO_PULL_DOWN:
90 return samsung_gpio_setpull_updown(chip, off, pull);
93 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
96 samsung_gpio_pull_t pull;
98 pull = samsung_gpio_getpull_updown(chip, off);
102 pull = S3C_GPIO_PULL_UP;
106 pull = S3C_GPIO_PULL_NONE;
109 pull = S3C_GPIO_PULL_DOWN;
116 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
117 unsigned int off, samsung_gpio_pull_t pull,
118 samsung_gpio_pull_t updown)
120 void __iomem *reg = chip->base + 0x08;
121 u32 pup = __raw_readl(reg);
125 else if (pull == S3C_GPIO_PULL_NONE)
130 __raw_writel(pup, reg);
134 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
136 samsung_gpio_pull_t updown)
138 void __iomem *reg = chip->base + 0x08;
139 u32 pup = __raw_readl(reg);
142 return pup ? S3C_GPIO_PULL_NONE : updown;
145 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
148 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
151 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
152 unsigned int off, samsung_gpio_pull_t pull)
154 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
157 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
160 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
163 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
164 unsigned int off, samsung_gpio_pull_t pull)
166 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
169 static int exynos4_gpio_setpull(struct samsung_gpio_chip *chip,
170 unsigned int off, samsung_gpio_pull_t pull)
172 if (pull == S3C_GPIO_PULL_UP)
175 return samsung_gpio_setpull_updown(chip, off, pull);
178 static samsung_gpio_pull_t exynos4_gpio_getpull(struct samsung_gpio_chip *chip,
181 samsung_gpio_pull_t pull;
183 pull = samsung_gpio_getpull_updown(chip, off);
186 pull = S3C_GPIO_PULL_UP;
192 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
193 * @chip: The gpio chip that is being configured.
194 * @off: The offset for the GPIO being configured.
195 * @cfg: The configuration value to set.
197 * This helper deal with the GPIO cases where the control register
198 * has two bits of configuration per gpio, which have the following
202 * 1x = special function
205 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
206 unsigned int off, unsigned int cfg)
208 void __iomem *reg = chip->base;
209 unsigned int shift = off * 2;
212 if (samsung_gpio_is_cfg_special(cfg)) {
220 con = __raw_readl(reg);
221 con &= ~(0x3 << shift);
223 __raw_writel(con, reg);
229 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
230 * @chip: The gpio chip that is being configured.
231 * @off: The offset for the GPIO being configured.
233 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
234 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
235 * S3C_GPIO_SPECIAL() macro.
238 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
243 con = __raw_readl(chip->base);
247 /* this conversion works for IN and OUT as well as special mode */
248 return S3C_GPIO_SPECIAL(con);
252 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
253 * @chip: The gpio chip that is being configured.
254 * @off: The offset for the GPIO being configured.
255 * @cfg: The configuration value to set.
257 * This helper deal with the GPIO cases where the control register has 4 bits
258 * of control per GPIO, generally in the form of:
261 * others = Special functions (dependent on bank)
263 * Note, since the code to deal with the case where there are two control
264 * registers instead of one, we do not have a separate set of functions for
268 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
269 unsigned int off, unsigned int cfg)
271 void __iomem *reg = chip->base;
272 unsigned int shift = (off & 7) * 4;
275 if (off < 8 && chip->chip.ngpio > 8)
278 if (samsung_gpio_is_cfg_special(cfg)) {
283 con = __raw_readl(reg);
284 con &= ~(0xf << shift);
286 __raw_writel(con, reg);
292 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
293 * @chip: The gpio chip that is being configured.
294 * @off: The offset for the GPIO being configured.
296 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
297 * register setting into a value the software can use, such as could be passed
298 * to samsung_gpio_setcfg_4bit().
300 * @sa samsung_gpio_getcfg_2bit
303 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
306 void __iomem *reg = chip->base;
307 unsigned int shift = (off & 7) * 4;
310 if (off < 8 && chip->chip.ngpio > 8)
313 con = __raw_readl(reg);
317 /* this conversion works for IN and OUT as well as special mode */
318 return S3C_GPIO_SPECIAL(con);
321 #ifdef CONFIG_PLAT_S3C24XX
323 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
324 * @chip: The gpio chip that is being configured.
325 * @off: The offset for the GPIO being configured.
326 * @cfg: The configuration value to set.
328 * This helper deal with the GPIO cases where the control register
329 * has one bit of configuration for the gpio, where setting the bit
330 * means the pin is in special function mode and unset means output.
333 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
334 unsigned int off, unsigned int cfg)
336 void __iomem *reg = chip->base;
337 unsigned int shift = off;
340 if (samsung_gpio_is_cfg_special(cfg)) {
343 /* Map output to 0, and SFN2 to 1 */
351 con = __raw_readl(reg);
352 con &= ~(0x1 << shift);
354 __raw_writel(con, reg);
360 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
361 * @chip: The gpio chip that is being configured.
362 * @off: The offset for the GPIO being configured.
364 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
365 * GPIO configuration value.
367 * @sa samsung_gpio_getcfg_2bit
368 * @sa samsung_gpio_getcfg_4bit
371 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
376 con = __raw_readl(chip->base);
381 return S3C_GPIO_SFN(con);
385 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
386 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
387 unsigned int off, unsigned int cfg)
389 void __iomem *reg = chip->base;
400 shift = (off & 7) * 4;
404 shift = ((off + 1) & 7) * 4;
407 shift = ((off + 1) & 7) * 4;
411 if (samsung_gpio_is_cfg_special(cfg)) {
416 con = __raw_readl(reg);
417 con &= ~(0xf << shift);
419 __raw_writel(con, reg);
425 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
428 for (; nr_chips > 0; nr_chips--, chipcfg++) {
429 if (!chipcfg->set_config)
430 chipcfg->set_config = samsung_gpio_setcfg_4bit;
431 if (!chipcfg->get_config)
432 chipcfg->get_config = samsung_gpio_getcfg_4bit;
433 if (!chipcfg->set_pull)
434 chipcfg->set_pull = samsung_gpio_setpull_updown;
435 if (!chipcfg->get_pull)
436 chipcfg->get_pull = samsung_gpio_getpull_updown;
440 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
441 .set_config = samsung_gpio_setcfg_2bit,
442 .get_config = samsung_gpio_getcfg_2bit,
445 #ifdef CONFIG_PLAT_S3C24XX
446 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
447 .set_config = s3c24xx_gpio_setcfg_abank,
448 .get_config = s3c24xx_gpio_getcfg_abank,
452 static struct samsung_gpio_cfg exynos4_gpio_cfg = {
453 .set_pull = exynos4_gpio_setpull,
454 .get_pull = exynos4_gpio_getpull,
455 .set_config = samsung_gpio_setcfg_4bit,
456 .get_config = samsung_gpio_getcfg_4bit,
459 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
460 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
462 .set_config = s5p64x0_gpio_setcfg_rbank,
463 .get_config = samsung_gpio_getcfg_4bit,
464 .set_pull = samsung_gpio_setpull_updown,
465 .get_pull = samsung_gpio_getpull_updown,
469 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
484 .set_config = samsung_gpio_setcfg_2bit,
485 .get_config = samsung_gpio_getcfg_2bit,
489 .set_config = samsung_gpio_setcfg_2bit,
490 .get_config = samsung_gpio_getcfg_2bit,
494 .set_config = samsung_gpio_setcfg_2bit,
495 .get_config = samsung_gpio_getcfg_2bit,
498 .set_config = samsung_gpio_setcfg_2bit,
499 .get_config = samsung_gpio_getcfg_2bit,
502 .set_pull = exynos4_gpio_setpull,
503 .get_pull = exynos4_gpio_getpull,
507 .set_pull = exynos4_gpio_setpull,
508 .get_pull = exynos4_gpio_getpull,
513 * Default routines for controlling GPIO, based on the original S3C24XX
514 * GPIO functions which deal with the case where each gpio bank of the
515 * chip is as following:
517 * base + 0x00: Control register, 2 bits per gpio
518 * gpio n: 2 bits starting at (2*n)
519 * 00 = input, 01 = output, others mean special-function
520 * base + 0x04: Data register, 1 bit per gpio
524 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
526 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
527 void __iomem *base = ourchip->base;
531 samsung_gpio_lock(ourchip, flags);
533 con = __raw_readl(base + 0x00);
534 con &= ~(3 << (offset * 2));
536 __raw_writel(con, base + 0x00);
538 samsung_gpio_unlock(ourchip, flags);
542 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
543 unsigned offset, int value)
545 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
546 void __iomem *base = ourchip->base;
551 samsung_gpio_lock(ourchip, flags);
553 dat = __raw_readl(base + 0x04);
554 dat &= ~(1 << offset);
557 __raw_writel(dat, base + 0x04);
559 con = __raw_readl(base + 0x00);
560 con &= ~(3 << (offset * 2));
561 con |= 1 << (offset * 2);
563 __raw_writel(con, base + 0x00);
564 __raw_writel(dat, base + 0x04);
566 samsung_gpio_unlock(ourchip, flags);
571 * The samsung_gpiolib_4bit routines are to control the gpio banks where
572 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
575 * base + 0x00: Control register, 4 bits per gpio
576 * gpio n: 4 bits starting at (4*n)
577 * 0000 = input, 0001 = output, others mean special-function
578 * base + 0x04: Data register, 1 bit per gpio
581 * Note, since the data register is one bit per gpio and is at base + 0x4
582 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
583 * state of the output.
586 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
589 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
590 void __iomem *base = ourchip->base;
593 con = __raw_readl(base + GPIOCON_OFF);
594 con &= ~(0xf << con_4bit_shift(offset));
595 __raw_writel(con, base + GPIOCON_OFF);
597 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
602 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
603 unsigned int offset, int value)
605 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
606 void __iomem *base = ourchip->base;
610 con = __raw_readl(base + GPIOCON_OFF);
611 con &= ~(0xf << con_4bit_shift(offset));
612 con |= 0x1 << con_4bit_shift(offset);
614 dat = __raw_readl(base + GPIODAT_OFF);
619 dat &= ~(1 << offset);
621 __raw_writel(dat, base + GPIODAT_OFF);
622 __raw_writel(con, base + GPIOCON_OFF);
623 __raw_writel(dat, base + GPIODAT_OFF);
625 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
631 * The next set of routines are for the case where the GPIO configuration
632 * registers are 4 bits per GPIO but there is more than one register (the
633 * bank has more than 8 GPIOs.
635 * This case is the similar to the 4 bit case, but the registers are as
638 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
639 * gpio n: 4 bits starting at (4*n)
640 * 0000 = input, 0001 = output, others mean special-function
641 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
642 * gpio n: 4 bits starting at (4*n)
643 * 0000 = input, 0001 = output, others mean special-function
644 * base + 0x08: Data register, 1 bit per gpio
647 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
648 * routines we store the 'base + 0x4' address so that these routines see
649 * the data register at ourchip->base + 0x04.
652 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
655 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
656 void __iomem *base = ourchip->base;
657 void __iomem *regcon = base;
665 con = __raw_readl(regcon);
666 con &= ~(0xf << con_4bit_shift(offset));
667 __raw_writel(con, regcon);
669 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
674 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
675 unsigned int offset, int value)
677 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
678 void __iomem *base = ourchip->base;
679 void __iomem *regcon = base;
682 unsigned con_offset = offset;
689 con = __raw_readl(regcon);
690 con &= ~(0xf << con_4bit_shift(con_offset));
691 con |= 0x1 << con_4bit_shift(con_offset);
693 dat = __raw_readl(base + GPIODAT_OFF);
698 dat &= ~(1 << offset);
700 __raw_writel(dat, base + GPIODAT_OFF);
701 __raw_writel(con, regcon);
702 __raw_writel(dat, base + GPIODAT_OFF);
704 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
709 #ifdef CONFIG_PLAT_S3C24XX
710 /* The next set of routines are for the case of s3c24xx bank a */
712 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
717 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
718 unsigned offset, int value)
720 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
721 void __iomem *base = ourchip->base;
726 local_irq_save(flags);
728 con = __raw_readl(base + 0x00);
729 dat = __raw_readl(base + 0x04);
731 dat &= ~(1 << offset);
735 __raw_writel(dat, base + 0x04);
737 con &= ~(1 << offset);
739 __raw_writel(con, base + 0x00);
740 __raw_writel(dat, base + 0x04);
742 local_irq_restore(flags);
747 /* The next set of routines are for the case of s5p64x0 bank r */
749 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
752 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
753 void __iomem *base = ourchip->base;
754 void __iomem *regcon = base;
774 samsung_gpio_lock(ourchip, flags);
776 con = __raw_readl(regcon);
777 con &= ~(0xf << con_4bit_shift(offset));
778 __raw_writel(con, regcon);
780 samsung_gpio_unlock(ourchip, flags);
785 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
786 unsigned int offset, int value)
788 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
789 void __iomem *base = ourchip->base;
790 void __iomem *regcon = base;
794 unsigned con_offset = offset;
796 switch (con_offset) {
812 samsung_gpio_lock(ourchip, flags);
814 con = __raw_readl(regcon);
815 con &= ~(0xf << con_4bit_shift(con_offset));
816 con |= 0x1 << con_4bit_shift(con_offset);
818 dat = __raw_readl(base + GPIODAT_OFF);
822 dat &= ~(1 << offset);
824 __raw_writel(con, regcon);
825 __raw_writel(dat, base + GPIODAT_OFF);
827 samsung_gpio_unlock(ourchip, flags);
832 static void samsung_gpiolib_set(struct gpio_chip *chip,
833 unsigned offset, int value)
835 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
836 void __iomem *base = ourchip->base;
840 samsung_gpio_lock(ourchip, flags);
842 dat = __raw_readl(base + 0x04);
843 dat &= ~(1 << offset);
846 __raw_writel(dat, base + 0x04);
848 samsung_gpio_unlock(ourchip, flags);
851 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
853 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
856 val = __raw_readl(ourchip->base + 0x04);
864 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
865 * for use with the configuration calls, and other parts of the s3c gpiolib
868 * Not all s3c support code will need this, as some configurations of cpu
869 * may only support one or two different configuration options and have an
870 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
871 * the machine support file should provide its own samsung_gpiolib_getchip()
872 * and any other necessary functions.
875 #ifdef CONFIG_S3C_GPIO_TRACK
876 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
878 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
883 gpn = chip->chip.base;
884 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
885 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
886 s3c_gpios[gpn] = chip;
889 #endif /* CONFIG_S3C_GPIO_TRACK */
892 * samsung_gpiolib_add() - add the Samsung gpio_chip.
893 * @chip: The chip to register
895 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
896 * information and makes the necessary alterations for the platform and
897 * notes the information for use with the configuration systems and any
898 * other parts of the system.
901 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
903 struct gpio_chip *gc = &chip->chip;
910 spin_lock_init(&chip->lock);
912 if (!gc->direction_input)
913 gc->direction_input = samsung_gpiolib_2bit_input;
914 if (!gc->direction_output)
915 gc->direction_output = samsung_gpiolib_2bit_output;
917 gc->set = samsung_gpiolib_set;
919 gc->get = samsung_gpiolib_get;
922 if (chip->pm != NULL) {
923 if (!chip->pm->save || !chip->pm->resume)
924 printk(KERN_ERR "gpio: %s has missing PM functions\n",
927 printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
930 /* gpiochip_add() prints own failure message on error. */
931 ret = gpiochip_add(gc);
933 s3c_gpiolib_track(chip);
936 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
937 int nr_chips, void __iomem *base)
940 struct gpio_chip *gc = &chip->chip;
942 for (i = 0 ; i < nr_chips; i++, chip++) {
943 /* skip banks not present on SoC */
944 if (chip->chip.base >= S3C_GPIO_END)
948 chip->config = &s3c24xx_gpiocfg_default;
950 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
951 if ((base != NULL) && (chip->base == NULL))
952 chip->base = base + ((i) * 0x10);
954 if (!gc->direction_input)
955 gc->direction_input = samsung_gpiolib_2bit_input;
956 if (!gc->direction_output)
957 gc->direction_output = samsung_gpiolib_2bit_output;
959 samsung_gpiolib_add(chip);
963 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
964 int nr_chips, void __iomem *base,
969 for (i = 0 ; i < nr_chips; i++, chip++) {
970 chip->chip.direction_input = samsung_gpiolib_2bit_input;
971 chip->chip.direction_output = samsung_gpiolib_2bit_output;
974 chip->config = &samsung_gpio_cfgs[7];
976 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
977 if ((base != NULL) && (chip->base == NULL))
978 chip->base = base + ((i) * offset);
980 samsung_gpiolib_add(chip);
985 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
986 * @chip: The gpio chip that is being configured.
987 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
989 * This helper deal with the GPIO cases where the control register has 4 bits
990 * of control per GPIO, generally in the form of:
993 * others = Special functions (dependent on bank)
995 * Note, since the code to deal with the case where there are two control
996 * registers instead of one, we do not have a separate set of function
997 * (samsung_gpiolib_add_4bit2_chips)for each case.
1000 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1001 int nr_chips, void __iomem *base)
1005 for (i = 0 ; i < nr_chips; i++, chip++) {
1006 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1007 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1010 chip->config = &samsung_gpio_cfgs[2];
1012 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1013 if ((base != NULL) && (chip->base == NULL))
1014 chip->base = base + ((i) * 0x20);
1016 samsung_gpiolib_add(chip);
1020 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1023 for (; nr_chips > 0; nr_chips--, chip++) {
1024 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1025 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1028 chip->config = &samsung_gpio_cfgs[2];
1030 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1032 samsung_gpiolib_add(chip);
1036 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1039 for (; nr_chips > 0; nr_chips--, chip++) {
1040 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1041 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1044 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1046 samsung_gpiolib_add(chip);
1050 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1052 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1054 return samsung_chip->irq_base + offset;
1057 #ifdef CONFIG_PLAT_S3C24XX
1058 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1061 return IRQ_EINT0 + offset;
1064 return IRQ_EINT4 + offset - 4;
1070 #ifdef CONFIG_PLAT_S3C64XX
1071 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1073 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1076 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1078 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1082 struct samsung_gpio_chip s3c24xx_gpios[] = {
1083 #ifdef CONFIG_PLAT_S3C24XX
1085 .config = &s3c24xx_gpiocfg_banka,
1087 .base = S3C2410_GPA(0),
1088 .owner = THIS_MODULE,
1091 .direction_input = s3c24xx_gpiolib_banka_input,
1092 .direction_output = s3c24xx_gpiolib_banka_output,
1096 .base = S3C2410_GPB(0),
1097 .owner = THIS_MODULE,
1103 .base = S3C2410_GPC(0),
1104 .owner = THIS_MODULE,
1110 .base = S3C2410_GPD(0),
1111 .owner = THIS_MODULE,
1117 .base = S3C2410_GPE(0),
1119 .owner = THIS_MODULE,
1124 .base = S3C2410_GPF(0),
1125 .owner = THIS_MODULE,
1128 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1131 .irq_base = IRQ_EINT8,
1133 .base = S3C2410_GPG(0),
1134 .owner = THIS_MODULE,
1137 .to_irq = samsung_gpiolib_to_irq,
1141 .base = S3C2410_GPH(0),
1142 .owner = THIS_MODULE,
1147 /* GPIOS for the S3C2443 and later devices. */
1149 .base = S3C2440_GPJCON,
1151 .base = S3C2410_GPJ(0),
1152 .owner = THIS_MODULE,
1157 .base = S3C2443_GPKCON,
1159 .base = S3C2410_GPK(0),
1160 .owner = THIS_MODULE,
1165 .base = S3C2443_GPLCON,
1167 .base = S3C2410_GPL(0),
1168 .owner = THIS_MODULE,
1173 .base = S3C2443_GPMCON,
1175 .base = S3C2410_GPM(0),
1176 .owner = THIS_MODULE,
1185 * GPIO bank summary:
1187 * Bank GPIOs Style SlpCon ExtInt Group
1193 * F 16 2Bit Yes 4 [1]
1195 * H 10 4Bit[2] Yes 6
1196 * I 16 2Bit Yes None
1197 * J 12 2Bit Yes None
1198 * K 16 4Bit[2] No None
1199 * L 15 4Bit[2] No None
1200 * M 6 4Bit No IRQ_EINT
1201 * N 16 2Bit No IRQ_EINT
1206 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1207 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1210 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1211 #ifdef CONFIG_PLAT_S3C64XX
1214 .base = S3C64XX_GPA(0),
1215 .ngpio = S3C64XX_GPIO_A_NR,
1220 .base = S3C64XX_GPB(0),
1221 .ngpio = S3C64XX_GPIO_B_NR,
1226 .base = S3C64XX_GPC(0),
1227 .ngpio = S3C64XX_GPIO_C_NR,
1232 .base = S3C64XX_GPD(0),
1233 .ngpio = S3C64XX_GPIO_D_NR,
1237 .config = &samsung_gpio_cfgs[0],
1239 .base = S3C64XX_GPE(0),
1240 .ngpio = S3C64XX_GPIO_E_NR,
1244 .base = S3C64XX_GPG_BASE,
1246 .base = S3C64XX_GPG(0),
1247 .ngpio = S3C64XX_GPIO_G_NR,
1251 .base = S3C64XX_GPM_BASE,
1252 .config = &samsung_gpio_cfgs[1],
1254 .base = S3C64XX_GPM(0),
1255 .ngpio = S3C64XX_GPIO_M_NR,
1257 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1263 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1264 #ifdef CONFIG_PLAT_S3C64XX
1266 .base = S3C64XX_GPH_BASE + 0x4,
1268 .base = S3C64XX_GPH(0),
1269 .ngpio = S3C64XX_GPIO_H_NR,
1273 .base = S3C64XX_GPK_BASE + 0x4,
1274 .config = &samsung_gpio_cfgs[0],
1276 .base = S3C64XX_GPK(0),
1277 .ngpio = S3C64XX_GPIO_K_NR,
1281 .base = S3C64XX_GPL_BASE + 0x4,
1282 .config = &samsung_gpio_cfgs[1],
1284 .base = S3C64XX_GPL(0),
1285 .ngpio = S3C64XX_GPIO_L_NR,
1287 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1293 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1294 #ifdef CONFIG_PLAT_S3C64XX
1296 .base = S3C64XX_GPF_BASE,
1297 .config = &samsung_gpio_cfgs[6],
1299 .base = S3C64XX_GPF(0),
1300 .ngpio = S3C64XX_GPIO_F_NR,
1304 .config = &samsung_gpio_cfgs[7],
1306 .base = S3C64XX_GPI(0),
1307 .ngpio = S3C64XX_GPIO_I_NR,
1311 .config = &samsung_gpio_cfgs[7],
1313 .base = S3C64XX_GPJ(0),
1314 .ngpio = S3C64XX_GPIO_J_NR,
1318 .config = &samsung_gpio_cfgs[6],
1320 .base = S3C64XX_GPO(0),
1321 .ngpio = S3C64XX_GPIO_O_NR,
1325 .config = &samsung_gpio_cfgs[6],
1327 .base = S3C64XX_GPP(0),
1328 .ngpio = S3C64XX_GPIO_P_NR,
1332 .config = &samsung_gpio_cfgs[6],
1334 .base = S3C64XX_GPQ(0),
1335 .ngpio = S3C64XX_GPIO_Q_NR,
1339 .base = S3C64XX_GPN_BASE,
1340 .irq_base = IRQ_EINT(0),
1341 .config = &samsung_gpio_cfgs[5],
1343 .base = S3C64XX_GPN(0),
1344 .ngpio = S3C64XX_GPIO_N_NR,
1346 .to_irq = samsung_gpiolib_to_irq,
1353 * S5P6440 GPIO bank summary:
1355 * Bank GPIOs Style SlpCon ExtInt Group
1359 * F 2 2Bit Yes 4 [1]
1361 * H 10 4Bit[2] Yes 6
1362 * I 16 2Bit Yes None
1363 * J 12 2Bit Yes None
1364 * N 16 2Bit No IRQ_EINT
1366 * R 15 4Bit[2] Yes 8
1369 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1370 #ifdef CONFIG_CPU_S5P6440
1373 .base = S5P6440_GPA(0),
1374 .ngpio = S5P6440_GPIO_A_NR,
1379 .base = S5P6440_GPB(0),
1380 .ngpio = S5P6440_GPIO_B_NR,
1385 .base = S5P6440_GPC(0),
1386 .ngpio = S5P6440_GPIO_C_NR,
1390 .base = S5P64X0_GPG_BASE,
1392 .base = S5P6440_GPG(0),
1393 .ngpio = S5P6440_GPIO_G_NR,
1400 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1401 #ifdef CONFIG_CPU_S5P6440
1403 .base = S5P64X0_GPH_BASE + 0x4,
1405 .base = S5P6440_GPH(0),
1406 .ngpio = S5P6440_GPIO_H_NR,
1413 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1414 #ifdef CONFIG_CPU_S5P6440
1416 .base = S5P64X0_GPR_BASE + 0x4,
1417 .config = &s5p64x0_gpio_cfg_rbank,
1419 .base = S5P6440_GPR(0),
1420 .ngpio = S5P6440_GPIO_R_NR,
1427 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1428 #ifdef CONFIG_CPU_S5P6440
1430 .base = S5P64X0_GPF_BASE,
1431 .config = &samsung_gpio_cfgs[6],
1433 .base = S5P6440_GPF(0),
1434 .ngpio = S5P6440_GPIO_F_NR,
1438 .base = S5P64X0_GPI_BASE,
1439 .config = &samsung_gpio_cfgs[4],
1441 .base = S5P6440_GPI(0),
1442 .ngpio = S5P6440_GPIO_I_NR,
1446 .base = S5P64X0_GPJ_BASE,
1447 .config = &samsung_gpio_cfgs[4],
1449 .base = S5P6440_GPJ(0),
1450 .ngpio = S5P6440_GPIO_J_NR,
1454 .base = S5P64X0_GPN_BASE,
1455 .config = &samsung_gpio_cfgs[5],
1457 .base = S5P6440_GPN(0),
1458 .ngpio = S5P6440_GPIO_N_NR,
1462 .base = S5P64X0_GPP_BASE,
1463 .config = &samsung_gpio_cfgs[6],
1465 .base = S5P6440_GPP(0),
1466 .ngpio = S5P6440_GPIO_P_NR,
1474 * S5P6450 GPIO bank summary:
1476 * Bank GPIOs Style SlpCon ExtInt Group
1482 * G 14 4Bit[2] Yes 5
1483 * H 10 4Bit[2] Yes 6
1484 * I 16 2Bit Yes None
1485 * J 12 2Bit Yes None
1487 * N 16 2Bit No IRQ_EINT
1489 * Q 14 2Bit Yes None
1490 * R 15 4Bit[2] Yes None
1493 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1494 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1497 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1498 #ifdef CONFIG_CPU_S5P6450
1501 .base = S5P6450_GPA(0),
1502 .ngpio = S5P6450_GPIO_A_NR,
1507 .base = S5P6450_GPB(0),
1508 .ngpio = S5P6450_GPIO_B_NR,
1513 .base = S5P6450_GPC(0),
1514 .ngpio = S5P6450_GPIO_C_NR,
1519 .base = S5P6450_GPD(0),
1520 .ngpio = S5P6450_GPIO_D_NR,
1524 .base = S5P6450_GPK_BASE,
1526 .base = S5P6450_GPK(0),
1527 .ngpio = S5P6450_GPIO_K_NR,
1534 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1535 #ifdef CONFIG_CPU_S5P6450
1537 .base = S5P64X0_GPG_BASE + 0x4,
1539 .base = S5P6450_GPG(0),
1540 .ngpio = S5P6450_GPIO_G_NR,
1544 .base = S5P64X0_GPH_BASE + 0x4,
1546 .base = S5P6450_GPH(0),
1547 .ngpio = S5P6450_GPIO_H_NR,
1554 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1555 #ifdef CONFIG_CPU_S5P6450
1557 .base = S5P64X0_GPR_BASE + 0x4,
1558 .config = &s5p64x0_gpio_cfg_rbank,
1560 .base = S5P6450_GPR(0),
1561 .ngpio = S5P6450_GPIO_R_NR,
1568 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1569 #ifdef CONFIG_CPU_S5P6450
1571 .base = S5P64X0_GPF_BASE,
1572 .config = &samsung_gpio_cfgs[6],
1574 .base = S5P6450_GPF(0),
1575 .ngpio = S5P6450_GPIO_F_NR,
1579 .base = S5P64X0_GPI_BASE,
1580 .config = &samsung_gpio_cfgs[4],
1582 .base = S5P6450_GPI(0),
1583 .ngpio = S5P6450_GPIO_I_NR,
1587 .base = S5P64X0_GPJ_BASE,
1588 .config = &samsung_gpio_cfgs[4],
1590 .base = S5P6450_GPJ(0),
1591 .ngpio = S5P6450_GPIO_J_NR,
1595 .base = S5P64X0_GPN_BASE,
1596 .config = &samsung_gpio_cfgs[5],
1598 .base = S5P6450_GPN(0),
1599 .ngpio = S5P6450_GPIO_N_NR,
1603 .base = S5P64X0_GPP_BASE,
1604 .config = &samsung_gpio_cfgs[6],
1606 .base = S5P6450_GPP(0),
1607 .ngpio = S5P6450_GPIO_P_NR,
1611 .base = S5P6450_GPQ_BASE,
1612 .config = &samsung_gpio_cfgs[5],
1614 .base = S5P6450_GPQ(0),
1615 .ngpio = S5P6450_GPIO_Q_NR,
1619 .base = S5P6450_GPS_BASE,
1620 .config = &samsung_gpio_cfgs[6],
1622 .base = S5P6450_GPS(0),
1623 .ngpio = S5P6450_GPIO_S_NR,
1631 * S5PC100 GPIO bank summary:
1633 * Bank GPIOs Style INT Type
1634 * A0 8 4Bit GPIO_INT0
1635 * A1 5 4Bit GPIO_INT1
1636 * B 8 4Bit GPIO_INT2
1637 * C 5 4Bit GPIO_INT3
1638 * D 7 4Bit GPIO_INT4
1639 * E0 8 4Bit GPIO_INT5
1640 * E1 6 4Bit GPIO_INT6
1641 * F0 8 4Bit GPIO_INT7
1642 * F1 8 4Bit GPIO_INT8
1643 * F2 8 4Bit GPIO_INT9
1644 * F3 4 4Bit GPIO_INT10
1645 * G0 8 4Bit GPIO_INT11
1646 * G1 3 4Bit GPIO_INT12
1647 * G2 7 4Bit GPIO_INT13
1648 * G3 7 4Bit GPIO_INT14
1649 * H0 8 4Bit WKUP_INT
1650 * H1 8 4Bit WKUP_INT
1651 * H2 8 4Bit WKUP_INT
1652 * H3 8 4Bit WKUP_INT
1653 * I 8 4Bit GPIO_INT15
1654 * J0 8 4Bit GPIO_INT16
1655 * J1 5 4Bit GPIO_INT17
1656 * J2 8 4Bit GPIO_INT18
1657 * J3 8 4Bit GPIO_INT19
1658 * J4 4 4Bit GPIO_INT20
1669 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1670 #ifdef CONFIG_CPU_S5PC100
1673 .base = S5PC100_GPA0(0),
1674 .ngpio = S5PC100_GPIO_A0_NR,
1679 .base = S5PC100_GPA1(0),
1680 .ngpio = S5PC100_GPIO_A1_NR,
1685 .base = S5PC100_GPB(0),
1686 .ngpio = S5PC100_GPIO_B_NR,
1691 .base = S5PC100_GPC(0),
1692 .ngpio = S5PC100_GPIO_C_NR,
1697 .base = S5PC100_GPD(0),
1698 .ngpio = S5PC100_GPIO_D_NR,
1703 .base = S5PC100_GPE0(0),
1704 .ngpio = S5PC100_GPIO_E0_NR,
1709 .base = S5PC100_GPE1(0),
1710 .ngpio = S5PC100_GPIO_E1_NR,
1715 .base = S5PC100_GPF0(0),
1716 .ngpio = S5PC100_GPIO_F0_NR,
1721 .base = S5PC100_GPF1(0),
1722 .ngpio = S5PC100_GPIO_F1_NR,
1727 .base = S5PC100_GPF2(0),
1728 .ngpio = S5PC100_GPIO_F2_NR,
1733 .base = S5PC100_GPF3(0),
1734 .ngpio = S5PC100_GPIO_F3_NR,
1739 .base = S5PC100_GPG0(0),
1740 .ngpio = S5PC100_GPIO_G0_NR,
1745 .base = S5PC100_GPG1(0),
1746 .ngpio = S5PC100_GPIO_G1_NR,
1751 .base = S5PC100_GPG2(0),
1752 .ngpio = S5PC100_GPIO_G2_NR,
1757 .base = S5PC100_GPG3(0),
1758 .ngpio = S5PC100_GPIO_G3_NR,
1763 .base = S5PC100_GPI(0),
1764 .ngpio = S5PC100_GPIO_I_NR,
1769 .base = S5PC100_GPJ0(0),
1770 .ngpio = S5PC100_GPIO_J0_NR,
1775 .base = S5PC100_GPJ1(0),
1776 .ngpio = S5PC100_GPIO_J1_NR,
1781 .base = S5PC100_GPJ2(0),
1782 .ngpio = S5PC100_GPIO_J2_NR,
1787 .base = S5PC100_GPJ3(0),
1788 .ngpio = S5PC100_GPIO_J3_NR,
1793 .base = S5PC100_GPJ4(0),
1794 .ngpio = S5PC100_GPIO_J4_NR,
1799 .base = S5PC100_GPK0(0),
1800 .ngpio = S5PC100_GPIO_K0_NR,
1805 .base = S5PC100_GPK1(0),
1806 .ngpio = S5PC100_GPIO_K1_NR,
1811 .base = S5PC100_GPK2(0),
1812 .ngpio = S5PC100_GPIO_K2_NR,
1817 .base = S5PC100_GPK3(0),
1818 .ngpio = S5PC100_GPIO_K3_NR,
1823 .base = S5PC100_GPL0(0),
1824 .ngpio = S5PC100_GPIO_L0_NR,
1829 .base = S5PC100_GPL1(0),
1830 .ngpio = S5PC100_GPIO_L1_NR,
1835 .base = S5PC100_GPL2(0),
1836 .ngpio = S5PC100_GPIO_L2_NR,
1841 .base = S5PC100_GPL3(0),
1842 .ngpio = S5PC100_GPIO_L3_NR,
1847 .base = S5PC100_GPL4(0),
1848 .ngpio = S5PC100_GPIO_L4_NR,
1852 .base = (S5P_VA_GPIO + 0xC00),
1853 .irq_base = IRQ_EINT(0),
1855 .base = S5PC100_GPH0(0),
1856 .ngpio = S5PC100_GPIO_H0_NR,
1858 .to_irq = samsung_gpiolib_to_irq,
1861 .base = (S5P_VA_GPIO + 0xC20),
1862 .irq_base = IRQ_EINT(8),
1864 .base = S5PC100_GPH1(0),
1865 .ngpio = S5PC100_GPIO_H1_NR,
1867 .to_irq = samsung_gpiolib_to_irq,
1870 .base = (S5P_VA_GPIO + 0xC40),
1871 .irq_base = IRQ_EINT(16),
1873 .base = S5PC100_GPH2(0),
1874 .ngpio = S5PC100_GPIO_H2_NR,
1876 .to_irq = samsung_gpiolib_to_irq,
1879 .base = (S5P_VA_GPIO + 0xC60),
1880 .irq_base = IRQ_EINT(24),
1882 .base = S5PC100_GPH3(0),
1883 .ngpio = S5PC100_GPIO_H3_NR,
1885 .to_irq = samsung_gpiolib_to_irq,
1892 * Followings are the gpio banks in S5PV210/S5PC110
1894 * The 'config' member when left to NULL, is initialized to the default
1895 * structure samsung_gpio_cfgs[3] in the init function below.
1897 * The 'base' member is also initialized in the init function below.
1898 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1899 * uses the above macro and depends on the banks being listed in order here.
1902 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1903 #ifdef CONFIG_CPU_S5PV210
1906 .base = S5PV210_GPA0(0),
1907 .ngpio = S5PV210_GPIO_A0_NR,
1912 .base = S5PV210_GPA1(0),
1913 .ngpio = S5PV210_GPIO_A1_NR,
1918 .base = S5PV210_GPB(0),
1919 .ngpio = S5PV210_GPIO_B_NR,
1924 .base = S5PV210_GPC0(0),
1925 .ngpio = S5PV210_GPIO_C0_NR,
1930 .base = S5PV210_GPC1(0),
1931 .ngpio = S5PV210_GPIO_C1_NR,
1936 .base = S5PV210_GPD0(0),
1937 .ngpio = S5PV210_GPIO_D0_NR,
1942 .base = S5PV210_GPD1(0),
1943 .ngpio = S5PV210_GPIO_D1_NR,
1948 .base = S5PV210_GPE0(0),
1949 .ngpio = S5PV210_GPIO_E0_NR,
1954 .base = S5PV210_GPE1(0),
1955 .ngpio = S5PV210_GPIO_E1_NR,
1960 .base = S5PV210_GPF0(0),
1961 .ngpio = S5PV210_GPIO_F0_NR,
1966 .base = S5PV210_GPF1(0),
1967 .ngpio = S5PV210_GPIO_F1_NR,
1972 .base = S5PV210_GPF2(0),
1973 .ngpio = S5PV210_GPIO_F2_NR,
1978 .base = S5PV210_GPF3(0),
1979 .ngpio = S5PV210_GPIO_F3_NR,
1984 .base = S5PV210_GPG0(0),
1985 .ngpio = S5PV210_GPIO_G0_NR,
1990 .base = S5PV210_GPG1(0),
1991 .ngpio = S5PV210_GPIO_G1_NR,
1996 .base = S5PV210_GPG2(0),
1997 .ngpio = S5PV210_GPIO_G2_NR,
2002 .base = S5PV210_GPG3(0),
2003 .ngpio = S5PV210_GPIO_G3_NR,
2008 .base = S5PV210_GPI(0),
2009 .ngpio = S5PV210_GPIO_I_NR,
2014 .base = S5PV210_GPJ0(0),
2015 .ngpio = S5PV210_GPIO_J0_NR,
2020 .base = S5PV210_GPJ1(0),
2021 .ngpio = S5PV210_GPIO_J1_NR,
2026 .base = S5PV210_GPJ2(0),
2027 .ngpio = S5PV210_GPIO_J2_NR,
2032 .base = S5PV210_GPJ3(0),
2033 .ngpio = S5PV210_GPIO_J3_NR,
2038 .base = S5PV210_GPJ4(0),
2039 .ngpio = S5PV210_GPIO_J4_NR,
2044 .base = S5PV210_MP01(0),
2045 .ngpio = S5PV210_GPIO_MP01_NR,
2050 .base = S5PV210_MP02(0),
2051 .ngpio = S5PV210_GPIO_MP02_NR,
2056 .base = S5PV210_MP03(0),
2057 .ngpio = S5PV210_GPIO_MP03_NR,
2062 .base = S5PV210_MP04(0),
2063 .ngpio = S5PV210_GPIO_MP04_NR,
2068 .base = S5PV210_MP05(0),
2069 .ngpio = S5PV210_GPIO_MP05_NR,
2073 .base = (S5P_VA_GPIO + 0xC00),
2074 .irq_base = IRQ_EINT(0),
2076 .base = S5PV210_GPH0(0),
2077 .ngpio = S5PV210_GPIO_H0_NR,
2079 .to_irq = samsung_gpiolib_to_irq,
2082 .base = (S5P_VA_GPIO + 0xC20),
2083 .irq_base = IRQ_EINT(8),
2085 .base = S5PV210_GPH1(0),
2086 .ngpio = S5PV210_GPIO_H1_NR,
2088 .to_irq = samsung_gpiolib_to_irq,
2091 .base = (S5P_VA_GPIO + 0xC40),
2092 .irq_base = IRQ_EINT(16),
2094 .base = S5PV210_GPH2(0),
2095 .ngpio = S5PV210_GPIO_H2_NR,
2097 .to_irq = samsung_gpiolib_to_irq,
2100 .base = (S5P_VA_GPIO + 0xC60),
2101 .irq_base = IRQ_EINT(24),
2103 .base = S5PV210_GPH3(0),
2104 .ngpio = S5PV210_GPIO_H3_NR,
2106 .to_irq = samsung_gpiolib_to_irq,
2113 * Followings are the gpio banks in EXYNOS4210
2115 * The 'config' member when left to NULL, is initialized to the default
2116 * structure samsung_gpio_cfgs[3] in the init function below.
2118 * The 'base' member is also initialized in the init function below.
2119 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2120 * uses the above macro and depends on the banks being listed in order here.
2123 static struct samsung_gpio_chip exynos4_gpios_1[] = {
2124 #ifdef CONFIG_ARCH_EXYNOS4
2127 .base = EXYNOS4_GPA0(0),
2128 .ngpio = EXYNOS4_GPIO_A0_NR,
2133 .base = EXYNOS4_GPA1(0),
2134 .ngpio = EXYNOS4_GPIO_A1_NR,
2139 .base = EXYNOS4_GPB(0),
2140 .ngpio = EXYNOS4_GPIO_B_NR,
2145 .base = EXYNOS4_GPC0(0),
2146 .ngpio = EXYNOS4_GPIO_C0_NR,
2151 .base = EXYNOS4_GPC1(0),
2152 .ngpio = EXYNOS4_GPIO_C1_NR,
2157 .base = EXYNOS4_GPD0(0),
2158 .ngpio = EXYNOS4_GPIO_D0_NR,
2163 .base = EXYNOS4_GPD1(0),
2164 .ngpio = EXYNOS4_GPIO_D1_NR,
2169 .base = EXYNOS4_GPE0(0),
2170 .ngpio = EXYNOS4_GPIO_E0_NR,
2175 .base = EXYNOS4_GPE1(0),
2176 .ngpio = EXYNOS4_GPIO_E1_NR,
2181 .base = EXYNOS4_GPE2(0),
2182 .ngpio = EXYNOS4_GPIO_E2_NR,
2187 .base = EXYNOS4_GPE3(0),
2188 .ngpio = EXYNOS4_GPIO_E3_NR,
2193 .base = EXYNOS4_GPE4(0),
2194 .ngpio = EXYNOS4_GPIO_E4_NR,
2199 .base = EXYNOS4_GPF0(0),
2200 .ngpio = EXYNOS4_GPIO_F0_NR,
2205 .base = EXYNOS4_GPF1(0),
2206 .ngpio = EXYNOS4_GPIO_F1_NR,
2211 .base = EXYNOS4_GPF2(0),
2212 .ngpio = EXYNOS4_GPIO_F2_NR,
2217 .base = EXYNOS4_GPF3(0),
2218 .ngpio = EXYNOS4_GPIO_F3_NR,
2225 static struct samsung_gpio_chip exynos4_gpios_2[] = {
2226 #ifdef CONFIG_ARCH_EXYNOS4
2229 .base = EXYNOS4_GPJ0(0),
2230 .ngpio = EXYNOS4_GPIO_J0_NR,
2235 .base = EXYNOS4_GPJ1(0),
2236 .ngpio = EXYNOS4_GPIO_J1_NR,
2241 .base = EXYNOS4_GPK0(0),
2242 .ngpio = EXYNOS4_GPIO_K0_NR,
2247 .base = EXYNOS4_GPK1(0),
2248 .ngpio = EXYNOS4_GPIO_K1_NR,
2253 .base = EXYNOS4_GPK2(0),
2254 .ngpio = EXYNOS4_GPIO_K2_NR,
2259 .base = EXYNOS4_GPK3(0),
2260 .ngpio = EXYNOS4_GPIO_K3_NR,
2265 .base = EXYNOS4_GPL0(0),
2266 .ngpio = EXYNOS4_GPIO_L0_NR,
2271 .base = EXYNOS4_GPL1(0),
2272 .ngpio = EXYNOS4_GPIO_L1_NR,
2277 .base = EXYNOS4_GPL2(0),
2278 .ngpio = EXYNOS4_GPIO_L2_NR,
2282 .config = &samsung_gpio_cfgs[8],
2284 .base = EXYNOS4_GPY0(0),
2285 .ngpio = EXYNOS4_GPIO_Y0_NR,
2289 .config = &samsung_gpio_cfgs[8],
2291 .base = EXYNOS4_GPY1(0),
2292 .ngpio = EXYNOS4_GPIO_Y1_NR,
2296 .config = &samsung_gpio_cfgs[8],
2298 .base = EXYNOS4_GPY2(0),
2299 .ngpio = EXYNOS4_GPIO_Y2_NR,
2303 .config = &samsung_gpio_cfgs[8],
2305 .base = EXYNOS4_GPY3(0),
2306 .ngpio = EXYNOS4_GPIO_Y3_NR,
2310 .config = &samsung_gpio_cfgs[8],
2312 .base = EXYNOS4_GPY4(0),
2313 .ngpio = EXYNOS4_GPIO_Y4_NR,
2317 .config = &samsung_gpio_cfgs[8],
2319 .base = EXYNOS4_GPY5(0),
2320 .ngpio = EXYNOS4_GPIO_Y5_NR,
2324 .config = &samsung_gpio_cfgs[8],
2326 .base = EXYNOS4_GPY6(0),
2327 .ngpio = EXYNOS4_GPIO_Y6_NR,
2331 .base = (S5P_VA_GPIO2 + 0xC00),
2332 .config = &samsung_gpio_cfgs[9],
2333 .irq_base = IRQ_EINT(0),
2335 .base = EXYNOS4_GPX0(0),
2336 .ngpio = EXYNOS4_GPIO_X0_NR,
2338 .to_irq = samsung_gpiolib_to_irq,
2341 .base = (S5P_VA_GPIO2 + 0xC20),
2342 .config = &samsung_gpio_cfgs[9],
2343 .irq_base = IRQ_EINT(8),
2345 .base = EXYNOS4_GPX1(0),
2346 .ngpio = EXYNOS4_GPIO_X1_NR,
2348 .to_irq = samsung_gpiolib_to_irq,
2351 .base = (S5P_VA_GPIO2 + 0xC40),
2352 .config = &samsung_gpio_cfgs[9],
2353 .irq_base = IRQ_EINT(16),
2355 .base = EXYNOS4_GPX2(0),
2356 .ngpio = EXYNOS4_GPIO_X2_NR,
2358 .to_irq = samsung_gpiolib_to_irq,
2361 .base = (S5P_VA_GPIO2 + 0xC60),
2362 .config = &samsung_gpio_cfgs[9],
2363 .irq_base = IRQ_EINT(24),
2365 .base = EXYNOS4_GPX3(0),
2366 .ngpio = EXYNOS4_GPIO_X3_NR,
2368 .to_irq = samsung_gpiolib_to_irq,
2374 static struct samsung_gpio_chip exynos4_gpios_3[] = {
2375 #ifdef CONFIG_ARCH_EXYNOS4
2378 .base = EXYNOS4_GPZ(0),
2379 .ngpio = EXYNOS4_GPIO_Z_NR,
2386 /* TODO: cleanup soc_is_* */
2387 static __init int samsung_gpiolib_init(void)
2389 struct samsung_gpio_chip *chip;
2393 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2395 if (soc_is_s3c24xx()) {
2396 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
2397 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
2398 } else if (soc_is_s3c64xx()) {
2399 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
2400 ARRAY_SIZE(s3c64xx_gpios_2bit),
2401 S3C64XX_VA_GPIO + 0xE0, 0x20);
2402 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
2403 ARRAY_SIZE(s3c64xx_gpios_4bit),
2405 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2406 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2407 } else if (soc_is_s5p6440()) {
2408 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2409 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2410 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2411 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
2412 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
2413 ARRAY_SIZE(s5p6440_gpios_4bit2));
2414 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
2415 ARRAY_SIZE(s5p6440_gpios_rbank));
2416 } else if (soc_is_s5p6450()) {
2417 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
2418 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
2419 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
2420 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
2421 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
2422 ARRAY_SIZE(s5p6450_gpios_4bit2));
2423 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
2424 ARRAY_SIZE(s5p6450_gpios_rbank));
2425 } else if (soc_is_s5pc100()) {
2427 chip = s5pc100_gpios_4bit;
2428 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
2430 for (i = 0; i < nr_chips; i++, chip++) {
2431 if (!chip->config) {
2432 chip->config = &samsung_gpio_cfgs[3];
2433 chip->group = group++;
2436 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
2437 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2438 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2440 } else if (soc_is_s5pv210()) {
2442 chip = s5pv210_gpios_4bit;
2443 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
2445 for (i = 0; i < nr_chips; i++, chip++) {
2446 if (!chip->config) {
2447 chip->config = &samsung_gpio_cfgs[3];
2448 chip->group = group++;
2451 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
2452 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
2453 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2455 } else if (soc_is_exynos4210()) {
2459 chip = exynos4_gpios_1;
2460 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2462 for (i = 0; i < nr_chips; i++, chip++) {
2463 if (!chip->config) {
2464 chip->config = &exynos4_gpio_cfg;
2465 chip->group = group++;
2468 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1, nr_chips, S5P_VA_GPIO1);
2471 chip = exynos4_gpios_2;
2472 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2474 for (i = 0; i < nr_chips; i++, chip++) {
2475 if (!chip->config) {
2476 chip->config = &exynos4_gpio_cfg;
2477 chip->group = group++;
2480 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2, nr_chips, S5P_VA_GPIO2);
2483 chip = exynos4_gpios_3;
2484 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2486 for (i = 0; i < nr_chips; i++, chip++) {
2487 if (!chip->config) {
2488 chip->config = &exynos4_gpio_cfg;
2489 chip->group = group++;
2492 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3, nr_chips, S5P_VA_GPIO3);
2494 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2495 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2496 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2499 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
2505 core_initcall(samsung_gpiolib_init);
2507 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
2509 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2510 unsigned long flags;
2517 offset = pin - chip->chip.base;
2519 samsung_gpio_lock(chip, flags);
2520 ret = samsung_gpio_do_setcfg(chip, offset, config);
2521 samsung_gpio_unlock(chip, flags);
2525 EXPORT_SYMBOL(s3c_gpio_cfgpin);
2527 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
2532 for (; nr > 0; nr--, start++) {
2533 ret = s3c_gpio_cfgpin(start, cfg);
2540 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
2542 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
2543 unsigned int cfg, samsung_gpio_pull_t pull)
2547 for (; nr > 0; nr--, start++) {
2548 s3c_gpio_setpull(start, pull);
2549 ret = s3c_gpio_cfgpin(start, cfg);
2556 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
2558 unsigned s3c_gpio_getcfg(unsigned int pin)
2560 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2561 unsigned long flags;
2566 offset = pin - chip->chip.base;
2568 samsung_gpio_lock(chip, flags);
2569 ret = samsung_gpio_do_getcfg(chip, offset);
2570 samsung_gpio_unlock(chip, flags);
2575 EXPORT_SYMBOL(s3c_gpio_getcfg);
2577 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
2579 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2580 unsigned long flags;
2586 offset = pin - chip->chip.base;
2588 samsung_gpio_lock(chip, flags);
2589 ret = samsung_gpio_do_setpull(chip, offset, pull);
2590 samsung_gpio_unlock(chip, flags);
2594 EXPORT_SYMBOL(s3c_gpio_setpull);
2596 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
2598 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2599 unsigned long flags;
2604 offset = pin - chip->chip.base;
2606 samsung_gpio_lock(chip, flags);
2607 pup = samsung_gpio_do_getpull(chip, offset);
2608 samsung_gpio_unlock(chip, flags);
2611 return (__force samsung_gpio_pull_t)pup;
2613 EXPORT_SYMBOL(s3c_gpio_getpull);
2615 /* gpiolib wrappers until these are totally eliminated */
2617 void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
2621 WARN_ON(to); /* should be none of these left */
2624 /* if pull is enabled, try first with up, and if that
2625 * fails, try using down */
2627 ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
2629 s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
2631 s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
2634 EXPORT_SYMBOL(s3c2410_gpio_pullup);
2636 void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
2638 /* do this via gpiolib until all users removed */
2640 gpio_request(pin, "temporary");
2641 gpio_set_value(pin, to);
2644 EXPORT_SYMBOL(s3c2410_gpio_setpin);
2646 unsigned int s3c2410_gpio_getpin(unsigned int pin)
2648 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2649 unsigned long offs = pin - chip->chip.base;
2651 return __raw_readl(chip->base + 0x04) & (1 << offs);
2653 EXPORT_SYMBOL(s3c2410_gpio_getpin);
2655 #ifdef CONFIG_S5P_GPIO_DRVSTR
2656 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
2658 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2667 off = pin - chip->chip.base;
2669 reg = chip->base + 0x0C;
2671 drvstr = __raw_readl(reg);
2672 drvstr = drvstr >> shift;
2675 return (__force s5p_gpio_drvstr_t)drvstr;
2677 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
2679 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
2681 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2690 off = pin - chip->chip.base;
2692 reg = chip->base + 0x0C;
2694 tmp = __raw_readl(reg);
2695 tmp &= ~(0x3 << shift);
2696 tmp |= drvstr << shift;
2698 __raw_writel(tmp, reg);
2702 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
2703 #endif /* CONFIG_S5P_GPIO_DRVSTR */
2705 #ifdef CONFIG_PLAT_S3C24XX
2706 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
2708 unsigned long flags;
2709 unsigned long misccr;
2711 local_irq_save(flags);
2712 misccr = __raw_readl(S3C24XX_MISCCR);
2715 __raw_writel(misccr, S3C24XX_MISCCR);
2716 local_irq_restore(flags);
2720 EXPORT_SYMBOL(s3c2410_modify_misccr);